1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <arch/bootblock.h>
4 #include <device/pci_ops.h>
5 #include <southbridge/intel/common/early_spi.h>
6 #include "pch.h"
7 #include "chip.h"
8
enable_port80_on_lpc(void)9 static void enable_port80_on_lpc(void)
10 {
11 RCBA32(GCS) &= ~4;
12 }
13
set_spi_speed(void)14 static void set_spi_speed(void)
15 {
16 u32 fdod;
17 u8 ssfc;
18
19 /* Observe SPI Descriptor Component Section 0 */
20 RCBA32(0x38b0) = 0x1000;
21
22 /* Extract the Write/Erase SPI Frequency from descriptor */
23 fdod = RCBA32(0x38b4);
24 fdod >>= 24;
25 fdod &= 7;
26
27 /* Set Software Sequence frequency to match */
28 ssfc = RCBA8(0x3893);
29 ssfc &= ~7;
30 ssfc |= fdod;
31 RCBA8(0x3893) = ssfc;
32 }
33
early_lpc_init(void)34 static void early_lpc_init(void)
35 {
36 const struct device *dev = pcidev_on_root(0x1f, 0);
37 const struct southbridge_intel_ibexpeak_config *config = NULL;
38
39 /*
40 * Enable some common LPC IO ranges:
41 * - 0x2e/0x2f, 0x4e/0x4f often SuperIO
42 * - 0x60/0x64, 0x62/0x66 often KBC/EC
43 * - 0x3f0-0x3f5/0x3f7 FDD
44 * - 0x378-0x37f and 0x778-0x77f LPT
45 * - 0x2f8-0x2ff COMB
46 * - 0x3f8-0x3ff COMA
47 * - 0x208-0x20f GAMEH
48 * - 0x200-0x207 GAMEL
49 */
50 pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
51 | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN
52 | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
53 | COMB_LPC_EN | COMA_LPC_EN);
54 pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
55
56 /* Clear PWR_FLR */
57 pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
58 (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1);
59
60 pci_write_config32(PCH_LPC_DEV, ETR3,
61 pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR);
62
63 /* Set up generic decode ranges */
64 if (!dev)
65 return;
66 if (dev->chip_info)
67 config = dev->chip_info;
68 if (!config)
69 return;
70
71 pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec);
72 pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec);
73 pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec);
74 pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
75 }
76
bootblock_early_southbridge_init(void)77 void bootblock_early_southbridge_init(void)
78 {
79 enable_spi_prefetching_and_caching();
80
81 /* Enable RCBA */
82 pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0);
83 pci_write_config32(lpc_dev, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
84
85 enable_port80_on_lpc();
86 set_spi_speed();
87
88 /* Enable upper 128bytes of CMOS */
89 RCBA32(RC) = (1 << 2);
90
91 early_lpc_init();
92 }
93