1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <arch/cpu.h>
4 #include <console/console.h>
5 #include <device/pci_ops.h>
6 #include <device/pci_def.h>
7 #include <northbridge/intel/ironlake/ironlake.h>
8 #include "pch.h"
9
10 /* This sets up magic Chipset Initialization Registers */
pch_setup_cir(int chipset_type)11 void pch_setup_cir(int chipset_type)
12 {
13 printk(BIOS_DEBUG, "Setting up Chipset Initialization Registers (CIR)\n");
14
15 uint16_t lpc_id = pci_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID);
16 struct cpuinfo_x86 c;
17 uint32_t cir22;
18
19 pci_or_config8(PCH_LPC_DEV, GEN_PMCON_3, 0xfb);
20
21 RCBA32_OR(GCS, 0x40); /* FERR# MUX enable */
22
23 RCBA8(0x3430) |= 0xfc;
24
25 RCBA32(CIR7) = 0xf;
26
27 RCBA32(CIR9) = 0;
28
29 switch (lpc_id) {
30 case 0x3b01:
31 case 0x3b03:
32 case 0x3b05:
33 case 0x3b07:
34 case 0x3b09:
35 case 0x3b0b:
36 case 0x3b0d:
37 case 0x3b0f:
38 RCBA32_AND_OR(CIR6, 0xff1fff7f, 0x600000);
39 break;
40 }
41
42 RCBA32_OR(0x3310, 0x31);
43
44 /* Intel 5 Series Chipset and Intel 3400 Series Chipset
45 External Design Specification (EDS) 13.8.1.1 */
46 if (chipset_type == IRONLAKE_DESKTOP)
47 pci_or_config32(PCH_LPC_DEV, GEN_PMCON_1, 1 << 3);
48
49 pci_write_config8(PCH_LPC_DEV, CIR4, 0x45);
50
51 RCBA32(CIR8) = 0x4000000;
52 pci_write_config32(PCH_LPC_DEV, PMIR, 0xc0000300);
53 RCBA32(0x3318) = 0x1020000; /* undocumented */
54 get_fms(&c, cpuid_eax(1));
55 if (c.x86_model == 0x1e) {
56 /* Lynnfield/Clarksfield */
57 RCBA32(CIR13) = 0xfffff;
58 RCBA32(CIR14) = 0x61080;
59 RCBA32(CIR16) = 0x7f8f9f80;
60 RCBA32(CIR18) = 0x3900;
61 RCBA32(CIR19) = 0x20002;
62 RCBA32(CIR20) = 0x44b00;
63 RCBA32(CIR21) = 0x02000;
64 cir22 = 0x20000;
65 } else if (c.x86_model == 0x1f || c.x86_model == 0x25) {
66 /* Auburndale/Havendale + Arrandale/Clarkdale */
67 RCBA32(CIR10) = 0xfff80;
68 RCBA32(CIR15) = 0x7f8f9fff;
69 RCBA32(CIR17) = 0x2900;
70 RCBA32(CIR19) = 0x10001;
71 RCBA32(CIR20) = 0x1004b;
72 RCBA32(CIR21) = 0x8;
73 cir22 = 0x10000;
74 } else {
75 die("unsupported CPU model: %x!\n", c.x86_model);
76 }
77
78 /* EDS, 10.1.77: Program this register after all registers in the
79 3330-33D3 range and D31:F0:A9h are already programmed */
80 RCBA32(CIR22) = cir22;
81 }
82