1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <device/mmio.h>
4 #include <device/pci_ops.h>
5 #include "pch.h"
6 #include "cpu/intel/model_2065x/model_2065x.h"
7 #include <cpu/x86/msr.h>
8
9 /* Early thermal init, must be done prior to giving ME its memory
10 which is done at the end of raminit. */
early_thermal_init(void)11 void early_thermal_init(void)
12 {
13 pci_devfn_t dev;
14 msr_t msr;
15
16 dev = PCI_DEV(0x0, 0x1f, 0x6);
17
18 /* Program address for temporary BAR. */
19 pci_write_config32(dev, 0x40, 0x40000000);
20 pci_write_config32(dev, 0x44, 0x0);
21
22 /* Activate temporary BAR. */
23 pci_write_config32(dev, 0x40,
24 pci_read_config32(dev, 0x40) | 5);
25
26 /* Perform init. */
27 /* Configure TJmax. */
28 msr = rdmsr(MSR_TEMPERATURE_TARGET);
29 write16((u16 *)0x40000012, ((msr.lo >> 16) & 0xff) << 6);
30 /* Northbridge temperature slope and offset. */
31 write16((u16 *)0x40000016, 0x7746);
32 /* Enable thermal data reporting, processor, PCH and northbridge. */
33 write16((u16 *)0x4000001a,
34 (read16((u16 *)0x4000001a) & ~0xf) | 0x10f0);
35
36 /* Disable temporary BAR. */
37 pci_write_config32(dev, 0x40,
38 pci_read_config32(dev, 0x40) & ~1);
39 pci_write_config32(dev, 0x40, 0);
40 }
41