1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <types.h>
4 #include <arch/io.h>
5 #include <device/pci_ops.h>
6 #include <console/console.h>
7 #include <device/pci_def.h>
8 #include <cpu/intel/em64t101_save_state.h>
9 #include <cpu/intel/model_2065x/model_2065x.h>
10 #include <southbridge/intel/common/finalize.h>
11 #include <southbridge/intel/common/pmbase.h>
12 #include <southbridge/intel/ibexpeak/me.h>
13 #include "pch.h"
14
15 /* We are using PCIe accesses for now
16 * 1. the chipset can do it
17 * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
18 */
19 #include <northbridge/intel/ironlake/ironlake.h>
20 #include <southbridge/intel/common/gpio.h>
21 #include <southbridge/intel/common/pmutil.h>
22
southbridge_gate_memory_reset_real(int offset,u16 use,u16 io,u16 lvl)23 static void southbridge_gate_memory_reset_real(int offset,
24 u16 use, u16 io, u16 lvl)
25 {
26 u32 reg32;
27
28 /* Make sure it is set as GPIO */
29 reg32 = inl(use);
30 if (!(reg32 & (1 << offset))) {
31 reg32 |= (1 << offset);
32 outl(reg32, use);
33 }
34
35 /* Make sure it is set as output */
36 reg32 = inl(io);
37 if (reg32 & (1 << offset)) {
38 reg32 &= ~(1 << offset);
39 outl(reg32, io);
40 }
41
42 /* Drive the output low */
43 reg32 = inl(lvl);
44 reg32 &= ~(1 << offset);
45 outl(reg32, lvl);
46 }
47
48 /*
49 * Drive GPIO 60 low to gate memory reset in S3.
50 *
51 * Intel reference designs all use GPIO 60 but it is
52 * not a requirement and boards could use a different pin.
53 */
southbridge_gate_memory_reset(void)54 void southbridge_gate_memory_reset(void)
55 {
56 u16 gpiobase;
57
58 gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
59 if (!gpiobase)
60 return;
61
62 if (CONFIG_DRAM_RESET_GATE_GPIO >= 32)
63 southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO - 32,
64 gpiobase + GPIO_USE_SEL2,
65 gpiobase + GP_IO_SEL2,
66 gpiobase + GP_LVL2);
67 else
68 southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO,
69 gpiobase + GPIO_USE_SEL,
70 gpiobase + GP_IO_SEL,
71 gpiobase + GP_LVL);
72 }
73
southbridge_smi_monitor(void)74 void southbridge_smi_monitor(void)
75 {
76 #define IOTRAP(x) (trap_sts & (1 << x))
77 u32 trap_sts, trap_cycle;
78 u32 data, mask = 0;
79 int i;
80
81 trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
82 RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
83
84 trap_cycle = RCBA32(0x1e10);
85 for (i = 16; i < 20; i++) {
86 if (trap_cycle & (1 << i))
87 mask |= (0xff << ((i - 16) << 3));
88 }
89
90 /* IOTRAP(3) SMI function call */
91 if (IOTRAP(3)) {
92 return;
93 }
94
95 /* IOTRAP(2) currently unused
96 * IOTRAP(1) currently unused */
97
98 /* IOTRAP(0) SMIC */
99 if (IOTRAP(0)) {
100 if (!(trap_cycle & (1 << 24))) { // It's a write
101 printk(BIOS_DEBUG, "SMI1 command\n");
102 data = RCBA32(0x1e18);
103 data &= mask;
104 // if (smi1)
105 // southbridge_smi_command(data);
106 // return;
107 }
108 // Fall through to debug
109 }
110
111 printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
112 for (i = 0; i < 4; i++) {
113 if (IOTRAP(i))
114 printk(BIOS_DEBUG, " TRAP = %d\n", i);
115 }
116 printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
117 printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
118 printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
119
120 if (!(trap_cycle & (1 << 24))) {
121 /* Write Cycle */
122 data = RCBA32(0x1e18);
123 printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);
124 }
125 #undef IOTRAP
126 }
127
southbridge_finalize_all(void)128 void southbridge_finalize_all(void)
129 {
130 /* TODO: Finalize ME */
131 intel_pch_finalize_smm();
132 intel_ironlake_finalize_smm();
133 intel_model_2065x_finalize_smm();
134 }
135