1## SPDX-License-Identifier: GPL-2.0-only 2 3ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y) 4 5bootblock-y += bootblock.c 6 7ramstage-y += pch.c 8ramstage-y += iobp.c 9ramstage-y += azalia.c 10ramstage-y += fadt.c 11ramstage-y += lpc.c 12ramstage-y += pcie.c 13ramstage-y += sata.c 14ramstage-y += usb_ehci.c 15ramstage-y += usb_xhci.c 16ramstage-y += me.c 17ramstage-y += smbus.c 18ramstage-y += hda_verb.c 19ramstage-$(CONFIG_INTEL_LYNXPOINT_LP) += serialio.c 20 21ifneq ($(CONFIG_VARIANT_DIR),) 22ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/hda_verb.c 23endif 24 25ramstage-y += me_status.c 26ramstage-y += acpi.c 27 28ramstage-$(CONFIG_ELOG) += elog.c 29 30ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c 31smm-y += smihandler.c pch.c 32smm-y += pmutil.c usb_ehci.c usb_xhci.c 33 34bootblock-y += early_pch.c 35romstage-y += early_usb.c early_me.c me_status.c early_pch.c 36romstage-y += pmutil.c 37romstage-y += iobp.c 38 39romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c 40subdirs-$(CONFIG_USE_NATIVE_RAMINIT) += hsio 41 42romstage-$(CONFIG_USE_BROADWELL_MRC) += early_pch_native.c early_usb_native.c iobp.c thermal.c 43subdirs-$(CONFIG_USE_BROADWELL_MRC) += hsio 44 45ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) 46romstage-y += lp_gpio.c 47ramstage-y += lp_gpio.c 48smm-y += lp_gpio.c 49verstage-y += lp_gpio.c 50bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += uart_init.c 51bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += iobp.c 52all-$(CONFIG_SERIALIO_UART_CONSOLE) += uart.c 53smm-$(CONFIG_SERIALIO_UART_CONSOLE) += uart.c 54endif 55 56verstage-y += pmutil.c 57 58CPPFLAGS_common += -I$(src)/southbridge/intel/lynxpoint/include 59 60endif 61