1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include "me.h"
5
6 /* HFS1[3:0] Current Working State Values */
7 static const char *me_cws_values[] = {
8 [ME_HFS_CWS_RESET] = "Reset",
9 [ME_HFS_CWS_INIT] = "Initializing",
10 [ME_HFS_CWS_REC] = "Recovery",
11 [ME_HFS_CWS_NORMAL] = "Normal",
12 [ME_HFS_CWS_WAIT] = "Platform Disable Wait",
13 [ME_HFS_CWS_TRANS] = "OP State Transition",
14 [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In",
15 };
16
17 /* HFS1[8:6] Current Operation State Values */
18 static const char *me_opstate_values[] = {
19 [ME_HFS_STATE_PREBOOT] = "Preboot",
20 [ME_HFS_STATE_M0_UMA] = "M0 with UMA",
21 [ME_HFS_STATE_M3] = "M3 without UMA",
22 [ME_HFS_STATE_M0] = "M0 without UMA",
23 [ME_HFS_STATE_BRINGUP] = "Bring up",
24 [ME_HFS_STATE_ERROR] = "M0 without UMA but with error"
25 };
26
27 /* HFS[19:16] Current Operation Mode Values */
28 static const char *me_opmode_values[] = {
29 [ME_HFS_MODE_NORMAL] = "Normal",
30 [ME_HFS_MODE_DEBUG] = "Debug",
31 [ME_HFS_MODE_DIS] = "Soft Temporary Disable",
32 [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper",
33 [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message"
34 };
35
36 /* HFS[15:12] Error Code Values */
37 static const char *me_error_values[] = {
38 [ME_HFS_ERROR_NONE] = "No Error",
39 [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure",
40 [ME_HFS_ERROR_IMAGE] = "Image Failure",
41 [ME_HFS_ERROR_DEBUG] = "Debug Failure"
42 };
43
44 /* HFS2[31:28] ME Progress Code */
45 static const char *me_progress_values[] = {
46 [ME_HFS2_PHASE_ROM] = "ROM Phase",
47 [ME_HFS2_PHASE_BUP] = "BUP Phase",
48 [ME_HFS2_PHASE_UKERNEL] = "uKernel Phase",
49 [ME_HFS2_PHASE_POLICY] = "Policy Module",
50 [ME_HFS2_PHASE_MODULE_LOAD] = "Module Loading",
51 [ME_HFS2_PHASE_UNKNOWN] = "Unknown",
52 [ME_HFS2_PHASE_HOST_COMM] = "Host Communication"
53 };
54
55 /* HFS2[27:24] Power Management Event */
56 static const char *me_pmevent_values[] = {
57 [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = "Clean Moff->Mx wake",
58 [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = "Moff->Mx wake after an error",
59 [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = "Clean global reset",
60 [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = "Global reset after an error",
61 [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = "Clean Intel ME reset",
62 [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = "Intel ME reset due to exception",
63 [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = "Pseudo-global reset",
64 [ME_HFS2_PMEVENT_S0MO_SXM3] = "S0/M0->Sx/M3",
65 [ME_HFS2_PMEVENT_SXM3_S0M0] = "Sx/M3->S0/M0",
66 [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = "Non-power cycle reset",
67 [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = "Power cycle reset through M3",
68 [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = "Power cycle reset through Moff",
69 [ME_HFS2_PMEVENT_SXMX_SXMOFF] = "Sx/Mx->Sx/Moff"
70 };
71
72 /* Progress Code 0 states */
73 static const char *me_progress_rom_values[] = {
74 [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN",
75 [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE"
76 };
77
78 /* Progress Code 1 states */
79 static const char *me_progress_bup_values[] = {
80 [ME_HFS2_STATE_BUP_INIT] = "Initialization starts",
81 [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = "Disable the host wake event",
82 [ME_HFS2_STATE_BUP_FLOW_DET] = "Flow determination start process",
83 [ME_HFS2_STATE_BUP_VSCC_ERR] = "Error reading/matching the VSCC table in the descriptor",
84 [ME_HFS2_STATE_BUP_CHECK_STRAP] = "Check to see if straps say ME DISABLED",
85 [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = "Timeout waiting for PWROK",
86 [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = "Possibly handle BUP manufacturing override strap",
87 [ME_HFS2_STATE_BUP_M3] = "Bringup in M3",
88 [ME_HFS2_STATE_BUP_M0] = "Bringup in M0",
89 [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = "Flow detection error",
90 [ME_HFS2_STATE_BUP_M3_CLK_ERR] = "M3 clock switching error",
91 [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = "Host error - CPU reset timeout, DID timeout, memory missing",
92 [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = "M3 kernel load",
93 [ME_HFS2_STATE_BUP_T32_MISSING] = "T34 missing - cannot program ICC",
94 [ME_HFS2_STATE_BUP_WAIT_DID] = "Waiting for DID BIOS message",
95 [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = "Waiting for DID BIOS message failure",
96 [ME_HFS2_STATE_BUP_DID_NO_FAIL] = "DID reported no error",
97 [ME_HFS2_STATE_BUP_ENABLE_UMA] = "Enabling UMA",
98 [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = "Enabling UMA error",
99 [ME_HFS2_STATE_BUP_SEND_DID_ACK] = "Sending DID Ack to BIOS",
100 [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = "Sending DID Ack to BIOS error",
101 [ME_HFS2_STATE_BUP_M0_CLK] = "Switching clocks in M0",
102 [ME_HFS2_STATE_BUP_M0_CLK_ERR] = "Switching clocks in M0 error",
103 [ME_HFS2_STATE_BUP_TEMP_DIS] = "ME in temp disable",
104 [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = "M0 kernel load",
105 };
106
107 /* Progress Code 3 states */
108 static const char *me_progress_policy_values[] = {
109 [ME_HFS2_STATE_POLICY_ENTRY] = "Entry into Policy Module",
110 [ME_HFS2_STATE_POLICY_RCVD_S3] = "Received S3 entry",
111 [ME_HFS2_STATE_POLICY_RCVD_S4] = "Received S4 entry",
112 [ME_HFS2_STATE_POLICY_RCVD_S5] = "Received S5 entry",
113 [ME_HFS2_STATE_POLICY_RCVD_UPD] = "Received UPD entry",
114 [ME_HFS2_STATE_POLICY_RCVD_PCR] = "Received PCR entry",
115 [ME_HFS2_STATE_POLICY_RCVD_NPCR] = "Received NPCR entry",
116 [ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE] = "Received host wake",
117 [ME_HFS2_STATE_POLICY_RCVD_AC_DC] = "Received AC<>DC switch",
118 [ME_HFS2_STATE_POLICY_RCVD_DID] = "Received DRAM Init Done",
119 [ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND] = "VSCC Data not found for flash device",
120 [ME_HFS2_STATE_POLICY_VSCC_INVALID] = "VSCC Table is not valid",
121 [ME_HFS2_STATE_POLICY_FPB_ERR] = "Flash Partition Boundary is outside address space",
122 [ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR] = "ME cannot access the chipset descriptor region",
123 [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = "Required VSCC values for flash parts do not match",
124 };
125
intel_me_status(union me_hfs hfs,union me_hfs2 hfs2)126 void intel_me_status(union me_hfs hfs, union me_hfs2 hfs2)
127 {
128 if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG)
129 return;
130
131 /* Check Current States */
132 printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n",
133 hfs.fpt_bad ? "BAD" : "OK");
134 printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n",
135 hfs.ft_bup_ld_flr ? "YES" : "NO");
136 printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n",
137 hfs.fw_init_complete ? "YES" : "NO");
138 printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n",
139 hfs.mfg_mode ? "YES" : "NO");
140 printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n",
141 hfs.boot_options_present ? "YES" : "NO");
142 printk(BIOS_DEBUG, "ME: Update In Progress : %s\n",
143 hfs.update_in_progress ? "YES" : "NO");
144 printk(BIOS_DEBUG, "ME: Current Working State : %s\n",
145 me_cws_values[hfs.working_state]);
146 printk(BIOS_DEBUG, "ME: Current Operation State : %s\n",
147 me_opstate_values[hfs.operation_state]);
148 printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n",
149 me_opmode_values[hfs.operation_mode]);
150 printk(BIOS_DEBUG, "ME: Error Code : %s\n",
151 me_error_values[hfs.error_code]);
152 printk(BIOS_DEBUG, "ME: Progress Phase : %s\n",
153 me_progress_values[hfs2.progress_code]);
154 printk(BIOS_DEBUG, "ME: Power Management Event : %s\n",
155 me_pmevent_values[hfs2.current_pmevent]);
156
157 printk(BIOS_DEBUG, "ME: Progress Phase State : ");
158 switch (hfs2.progress_code) {
159 case ME_HFS2_PHASE_ROM: /* ROM Phase */
160 printk(BIOS_DEBUG, "%s",
161 me_progress_rom_values[hfs2.current_state]);
162 break;
163
164 case ME_HFS2_PHASE_BUP: /* Bringup Phase */
165 if (hfs2.current_state < ARRAY_SIZE(me_progress_bup_values)
166 && me_progress_bup_values[hfs2.current_state])
167 printk(BIOS_DEBUG, "%s",
168 me_progress_bup_values[hfs2.current_state]);
169 else
170 printk(BIOS_DEBUG, "0x%02x", hfs2.current_state);
171 break;
172
173 case ME_HFS2_PHASE_POLICY: /* Policy Module Phase */
174 if (hfs2.current_state < ARRAY_SIZE(me_progress_policy_values)
175 && me_progress_policy_values[hfs2.current_state])
176 printk(BIOS_DEBUG, "%s",
177 me_progress_policy_values[hfs2.current_state]);
178 else
179 printk(BIOS_DEBUG, "0x%02x", hfs2.current_state);
180 break;
181
182 case ME_HFS2_PHASE_HOST_COMM: /* Host Communication Phase */
183 if (!hfs2.current_state)
184 printk(BIOS_DEBUG, "Host communication established");
185 else
186 printk(BIOS_DEBUG, "0x%02x", hfs2.current_state);
187 break;
188
189 default:
190 printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x",
191 hfs2.progress_code, hfs2.current_state);
192 }
193 printk(BIOS_DEBUG, "\n");
194 }
195