1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <device/device.h>
4 #include <device/pnp.h>
5 #include <superio/conf_mode.h>
6 #include <pc80/keyboard.h>
7 #include <superio/common/ssdt.h>
8 #include <acpi/acpi.h>
9 #include "ast2400.h"
10 #include "chip.h"
11
ast2400_init(struct device * dev)12 static void ast2400_init(struct device *dev)
13 {
14 struct superio_aspeed_ast2400_config *conf = dev->chip_info;
15
16 if (!dev->enabled)
17 return;
18
19 if (conf && conf->use_espi) {
20 pnp_enter_conf_mode(dev);
21 pnp_set_logical_device(dev);
22 /* In ESPI mode must write 0 to IRQ level on every LDN */
23 pnp_write_config(dev, 0x71, 0);
24 pnp_exit_conf_mode(dev);
25 }
26
27 switch (dev->path.pnp.device) {
28 case AST2400_KBC:
29 pc_keyboard_init(NO_AUX_DEVICE);
30 break;
31 }
32 }
33
34 #if CONFIG(HAVE_ACPI_TABLES)
35 /* Provide ACPI HIDs for generic Super I/O SSDT */
ast2400_acpi_hid(const struct device * dev)36 static const char *ast2400_acpi_hid(const struct device *dev)
37 {
38 /* Sanity checks */
39 if (dev->path.type != DEVICE_PATH_PNP)
40 return NULL;
41 if (dev->path.pnp.port == 0)
42 return NULL;
43 if ((dev->path.pnp.device & 0xff) > AST2400_MAILBOX)
44 return NULL;
45
46 switch (dev->path.pnp.device & 0xff) {
47 case AST2400_SUART1: /* fallthrough */
48 case AST2400_SUART2: /* fallthrough */
49 case AST2400_SUART3: /* fallthrough */
50 case AST2400_SUART4:
51 return ACPI_HID_COM;
52 case AST2400_KBC:
53 return ACPI_HID_KEYBOARD;
54 default:
55 return ACPI_HID_PNP;
56 }
57 }
58 #endif
59
60 static struct device_operations ops = {
61 .read_resources = pnp_read_resources,
62 .set_resources = pnp_set_resources,
63 .enable_resources = pnp_enable_resources,
64 .enable = pnp_enable,
65 .init = ast2400_init,
66 .ops_pnp_mode = &pnp_conf_mode_a5a5_aa,
67 #if CONFIG(HAVE_ACPI_TABLES)
68 .acpi_fill_ssdt = superio_common_fill_ssdt_generator,
69 .acpi_name = superio_common_ldn_acpi_name,
70 .acpi_hid = ast2400_acpi_hid,
71 #endif
72 };
73
74 static struct pnp_info pnp_dev_info[] = {
75 { NULL, AST2400_SUART1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, },
76 { NULL, AST2400_SUART2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, },
77 { NULL, AST2400_SWC, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3
78 | PNP_IRQ0, 0xfff8, 0xfff8, 0xfff8, 0xfff8, },
79 { NULL, AST2400_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1
80 | PNP_MSC0, 0xffff, 0xffff, },
81 { NULL, AST2400_GPIO, PNP_IRQ0, }, // GPIO LDN has no IO Region
82 { NULL, AST2400_SUART3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, },
83 { NULL, AST2400_SUART4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, },
84 { NULL, AST2400_ILPC2AHB, PNP_IRQ0 },
85 { NULL, AST2400_MAILBOX, PNP_IO0 | PNP_IRQ0, 0xfffe, },
86 };
87
enable_dev(struct device * dev)88 static void enable_dev(struct device *dev)
89 {
90 struct superio_aspeed_ast2400_config *conf = dev->chip_info;
91
92 if (conf && conf->use_espi) {
93 /* UART3 and UART4 are not usable in ESPI mode */
94 for (size_t i = 0; i < ARRAY_SIZE(pnp_dev_info); i++) {
95 if ((pnp_dev_info[i].function == AST2400_SUART3) ||
96 (pnp_dev_info[i].function == AST2400_SUART4))
97 pnp_dev_info[i].function = PNP_SKIP_FUNCTION;
98 }
99 }
100
101 pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info),
102 pnp_dev_info);
103 }
104
105 struct chip_operations superio_aspeed_ast2400_ops = {
106 .name = "ASpeed AST2400/AST2500 Super I/O",
107 .enable_dev = enable_dev,
108 };
109