1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3/* 4 * Include this file into a mainboard's DSDT _SB device tree and it will 5 * expose the F81803A SuperIO and some of its functionality. 6 * 7 * It allows the change of IO ports, IRQs and DMA settings on logical 8 * devices, disabling and reenabling logical devices and controlling power 9 * saving mode on logical devices or the whole chip. 10 * 11 * LDN State 12 * 0x1 UARTA Implemented, partially tested 13 * 0x2 UARTB Implemented, partially tested 14 * 0x4 HWM Not implemented 15 * 0x5 KBC Not implemented 16 * 0x6 GPIO6 Not implemented 17 * 0x7 WDT0&PLED Not implemented 18 * 0xa ACPI/PME/ERP Partially implemented 19 * 20 * Controllable through preprocessor defines: 21 * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) 22 * SUPERIO_PNP_BASE I/o address of the first PnP configuration register 23 * F81803A_SHOW_UARTA If defined, UARTA will be exposed. 24 * F81803A_SHOW_UARTB If defined, UARTB will be exposed. 25 * F81803A_SHOW_HWMON If defined, the hardware monitor will be exposed. 26 * F81803A_SHOW_PME If defined, the PME/EARP/ACPI will be exposed. 27 * 28 * Known issue: 29 * Do not enable UARTA and UARTB simultaneously, Linux boot will crash. 30 * Select one or the other. 31 */ 32#undef SUPERIO_CHIP_NAME 33#define SUPERIO_CHIP_NAME F81803A 34#include <superio/acpi/pnp.asl> 35 36#undef PNP_DEFAULT_PSC 37#define PNP_DEFAULT_PSC Return (0) /* no power management */ 38 39Device(SUPERIO_DEV) { 40 Name (_HID, EisaId("PNP0A05")) 41 Name (_STR, Unicode("Fintek F81803A Super I/O")) 42 Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) 43 44 /* Mutex for accesses to the configuration ports */ 45 Mutex(CRMX, 1) 46 47 /* SuperIO configuration ports */ 48 OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) 49 Field (CREG, ByteAcc, NoLock, Preserve) 50 { 51 PNP_ADDR_REG, 8, 52 PNP_DATA_REG, 8 53 } 54 IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) 55 { 56 Offset (0x07), 57 PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ 58 Offset (0x30), 59 PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ 60 Offset (0x60), 61 PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ 62 PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ 63 Offset (0x62), 64 PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ 65 PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ 66 Offset (0x70), 67 PNP_IRQ0, 8, /* First IRQ */ 68 offset(0xFB), 69 APC5, 8, /* PME ACPI Control Register 5 */ 70 } 71 72 Method(_CRS) 73 { 74 /* Announce the used i/o ports to the OS */ 75 Return (ResourceTemplate () { 76 IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) 77 }) 78 } 79 80 #undef PNP_ENTER_MAGIC_1ST 81 #undef PNP_ENTER_MAGIC_2ND 82 #undef PNP_ENTER_MAGIC_3RD 83 #undef PNP_ENTER_MAGIC_4TH 84 #undef PNP_EXIT_MAGIC_1ST 85 #undef PNP_EXIT_SPECIAL_REG 86 #undef PNP_EXIT_SPECIAL_VAL 87 #define PNP_ENTER_MAGIC_1ST 0x87 88 #define PNP_ENTER_MAGIC_2ND 0x87 89 #define PNP_EXIT_MAGIC_1ST 0xaa 90 #include <superio/acpi/pnp_config.asl> 91 92#ifdef F81803A_SHOW_UARTA 93 #undef SUPERIO_UART_LDN 94 #undef SUPERIO_UART_PM_REG 95 #undef SUPERIO_UART_PM_VAL 96 #undef SUPERIO_UART_PM_LDN 97 #define SUPERIO_UART_LDN 1 98 99 Device (SUPERIO_ID(SER, SUPERIO_UART_LDN)) { 100 Name (_HID, EisaId ("PNP0501")) 101 Name (_UID, SUPERIO_UID(SER, SUPERIO_UART_LDN)) 102 103 Method (_STA) 104 { 105 PNP_GENERIC_STA(SUPERIO_UART_LDN) 106 } 107 108 Method (_CRS, 0, Serialized) 109 { 110 Name (CRS, ResourceTemplate () { 111 IO (Decode16, 0x0000, 0x0000, 0x08, 0x08, IO0) 112 IRQNoFlags (IR0) {} 113 }) 114 ENTER_CONFIG_MODE (SUPERIO_UART_LDN) 115 PNP_READ_IO(PNP_IO0, CRS, IO0) 116 PNP_READ_IRQ(PNP_IRQ0, CRS, IR0) 117 EXIT_CONFIG_MODE () 118 Return (CRS) 119 } 120 121 Name (_PRS, ResourceTemplate () 122 { 123 StartDependentFn (0,0) { 124 IO (Decode16, 0x03f8, 0x03f8, 0x08, 0x08) 125 IRQNoFlags () {3,4,5,7,9,10,11,12} 126 } 127 StartDependentFn (0,0) { 128 IO (Decode16, 0x02f8, 0x02f8, 0x08, 0x08) 129 IRQNoFlags () {3,4,5,7,9,10,11,12} 130 } 131 StartDependentFn (1,0) { 132 IO (Decode16, 0x03e8, 0x03e8, 0x08, 0x08) 133 IRQNoFlags () {3,4,5,7,9,10,11,12} 134 } 135 StartDependentFn (1,0) { 136 IO (Decode16, 0x02e8, 0x02e8, 0x08, 0x08) 137 IRQNoFlags () {3,4,5,7,9,10,11,12} 138 } 139 StartDependentFn (2,0) { 140 IO (Decode16, 0x0100, 0x0ff8, 0x08, 0x08) 141 IRQNoFlags () {3,4,5,7,9,10,11,12} 142 } 143 EndDependentFn() 144 }) 145 146 Method (_SRS, 1, Serialized) 147 { 148 Name (TMPL, ResourceTemplate () { 149 IO (Decode16, 0x0000, 0x0000, 0x00, 0x00, IO0) 150 IRQNoFlags (IR0) {} 151 }) 152 ENTER_CONFIG_MODE (SUPERIO_UART_LDN) 153 PNP_WRITE_IO(PNP_IO0, Arg0, IO0) 154 PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0) 155 PNP_DEVICE_ACTIVE = 1 156 EXIT_CONFIG_MODE () 157 } 158 } 159#endif 160 161#ifdef F81803A_SHOW_UARTB 162 #undef SUPERIO_UART_LDN 163 #undef SUPERIO_UART_PM_REG 164 #undef SUPERIO_UART_PM_VAL 165 #undef SUPERIO_UART_PM_LDN 166 #define SUPERIO_UART_LDN 2 167 168 Device (SUPERIO_ID(SER, SUPERIO_UART_LDN)) { 169 Name (_HID, EisaId ("PNP0501")) 170 Name (_UID, SUPERIO_UID(SER, SUPERIO_UART_LDN)) 171 172 Method (_STA) 173 { 174 PNP_GENERIC_STA(SUPERIO_UART_LDN) 175 } 176 177 Method (_CRS, 0, Serialized) 178 { 179 Name (CRS, ResourceTemplate () { 180 IO (Decode16, 0x0000, 0x0000, 0x08, 0x08, IO0) 181 IRQNoFlags (IR0) {} 182 }) 183 ENTER_CONFIG_MODE (SUPERIO_UART_LDN) 184 PNP_READ_IO(PNP_IO0, CRS, IO0) 185 PNP_READ_IRQ(PNP_IRQ0, CRS, IR0) 186 EXIT_CONFIG_MODE () 187 Return (CRS) 188 } 189 190 Name (_PRS, ResourceTemplate () 191 { 192 StartDependentFn (0,0) { 193 IO (Decode16, 0x03f8, 0x03f8, 0x08, 0x08) 194 IRQNoFlags () {3,4,5,7,9,10,11,12} 195 } 196 StartDependentFn (0,0) { 197 IO (Decode16, 0x02f8, 0x02f8, 0x08, 0x08) 198 IRQNoFlags () {3,4,5,7,9,10,11,12} 199 } 200 StartDependentFn (1,0) { 201 IO (Decode16, 0x03e8, 0x03e8, 0x08, 0x08) 202 IRQNoFlags () {3,4,5,7,9,10,11,12} 203 } 204 StartDependentFn (1,0) { 205 IO (Decode16, 0x02e8, 0x02e8, 0x08, 0x08) 206 IRQNoFlags () {3,4,5,7,9,10,11,12} 207 } 208 StartDependentFn (2,0) { 209 IO (Decode16, 0x0100, 0x0ff8, 0x08, 0x08) 210 IRQNoFlags () {3,4,5,7,9,10,11,12} 211 } 212 EndDependentFn() 213 }) 214 215 Method (_SRS, 1, Serialized) 216 { 217 Name (TMPL, ResourceTemplate () { 218 IO (Decode16, 0x0000, 0x0000, 0x00, 0x00, IO0) 219 IRQNoFlags (IR0) {} 220 }) 221 ENTER_CONFIG_MODE (SUPERIO_UART_LDN) 222 PNP_WRITE_IO(PNP_IO0, Arg0, IO0) 223 PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0) 224 PNP_DEVICE_ACTIVE = 1 225 EXIT_CONFIG_MODE () 226 } 227 } 228#endif 229 230#ifdef F81803A_SHOW_PME 231 #undef SUPERIO_PME_LDN 232 #define SUPERIO_PME_LDN 0x0A 233 234 OperationRegion(APCx, SystemIO, APC5, 0x01) 235 Field(APCx, ByteAcc, Nolock, Preserve) /* bits in PME ACPI CONTROL Reg 5*/ 236 { 237 , 7, /*Control Reg 5 */ 238 PSIN, 1 /* PSIN_FLAG */ 239 } 240 241 /* routine to clear PSIN_FLAG in ACPI_CONTROL_REG_5 of SIO */ 242 Method(CPSI, 0, Serialized) 243 { 244 /* DBG0("SIO CPSI") */ 245 ENTER_CONFIG_MODE(SUPERIO_PME_LDN) 246 PSIN = 1 247 EXIT_CONFIG_MODE() 248 } 249#endif 250} 251