1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3/* 4 * Include this file into a mainboard's DSDT _SB device tree and it will 5 * expose the W83627DHG SuperIO and some of its functionality. 6 * 7 * It allows the change of IO ports, IRQs and DMA settings on logical 8 * devices, disabling and reenabling logical devices and controlling power 9 * saving mode on logical devices or the whole chip. 10 * 11 * LDN State 12 * 0x0 FDC Not implemented 13 * 0x1 PP Not implemented 14 * 0x2 UARTA Implemented, partially tested 15 * 0x3 UARTB UART only, partially tested 16 * 0x5 KBC Implemented, untested 17 * 0x6 SPI Not implemented 18 * 0x7 GPIO6 Not implemented 19 * 0x8 WDT0&PLED Not implemented 20 * 0x9 GPIO2-5 Not implemented 21 * 0xa ACPI Not implemented 22 * 0xb HWM Resources, PM only 23 * 0xc PECI&SST Not implemented 24 * 25 * Controllable through preprocessor defines: 26 * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) 27 * SUPERIO_PNP_BASE I/o address of the first PnP configuration register 28 * W83627DHG_SHOW_UARTA If defined, UARTA will be exposed. 29 * W83627DHG_SHOW_UARTB If defined, UARTB will be exposed. 30 * W83627DHG_SHOW_KBC If defined, the KBC will be exposed. 31 * W83627DHG_SHOW_PS2M If defined, PS/2 mouse support will be exposed. 32 * W83627DHG_SHOW_HWMON If defined, the hardware monitor will be exposed. 33 */ 34 35#undef SUPERIO_CHIP_NAME 36#define SUPERIO_CHIP_NAME W83627DHG 37#include <superio/acpi/pnp.asl> 38 39Device(SUPERIO_DEV) { 40 Name (_HID, EisaId("PNP0A05")) 41 Name (_STR, Unicode("Winbond W83627DHG Super I/O")) 42 Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) 43 44 /* Mutex for accesses to the configuration ports */ 45 Mutex(CRMX, 1) 46 47 /* SuperIO configuration ports */ 48 OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) 49 Field (CREG, ByteAcc, NoLock, Preserve) 50 { 51 PNP_ADDR_REG, 8, 52 PNP_DATA_REG, 8 53 } 54 IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) 55 { 56 Offset (0x07), 57 PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ 58 59 Offset (0x22), 60 FDPW, 1, /* FDC Power Down */ 61 , 2, 62 PRPW, 1, /* PRT Power Down */ 63 UAPW, 1, /* UART A Power Down */ 64 UBPW, 1, /* UART B Power Down */ 65 HWPW, 1, /* HWM Power Down */ 66 Offset (0x23), 67 IPD, 1, /* Immediate Chip Power Down */ 68 69 Offset (0x30), 70 PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ 71 72 Offset (0x60), 73 PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ 74 PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ 75 Offset (0x62), 76 PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ 77 PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ 78 79 Offset (0x70), 80 PNP_IRQ0, 8, /* First IRQ */ 81 Offset (0x72), 82 PNP_IRQ1, 8, /* Second IRQ */ 83 84 Offset (0x74), 85 PNP_DMA0, 8, /* DMA */ 86 87 Offset (0xf3), 88 SULM, 8, /* Suspend LED Mode Register */ 89 } 90 91 Method (_CRS) 92 { 93 /* Announce the used i/o ports to the OS */ 94 Return (ResourceTemplate () { 95 IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) 96 }) 97 } 98 99 #undef PNP_ENTER_MAGIC_1ST 100 #undef PNP_ENTER_MAGIC_2ND 101 #undef PNP_ENTER_MAGIC_3RD 102 #undef PNP_ENTER_MAGIC_4TH 103 #undef PNP_EXIT_MAGIC_1ST 104 #undef PNP_EXIT_SPECIAL_REG 105 #undef PNP_EXIT_SPECIAL_VAL 106 #define PNP_ENTER_MAGIC_1ST 0x87 107 #define PNP_ENTER_MAGIC_2ND 0x87 108 #define PNP_EXIT_MAGIC_1ST 0xaa 109 #include <superio/acpi/pnp_config.asl> 110 111 /* PM: indicate IPD (Immediate Power Down) bit state as D0/D3 */ 112 Method (_PSC) { 113 ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) 114 Local0 = IPD 115 EXIT_CONFIG_MODE () 116 If (Local0) { Return (3) } 117 Else { Return (0) } 118 } 119 120 /* PM: Switch to D0 by setting IPD low */ 121 Method (_PS0) { 122 ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) 123 IPD = 0 124 EXIT_CONFIG_MODE () 125 } 126 127 /* PM: Switch to D3 by setting IPD high */ 128 Method (_PS3) { 129 ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) 130 IPD = 1 131 EXIT_CONFIG_MODE () 132 } 133 134 /* Suspend LED: Write given three-bit value into appropriate register. 135 From the datasheet: 136 000 - drive pin constantly high 137 001 - drive 0.5Hz pulses 138 010 - drive pin constantly low 139 011 - drive 2Hz pulses 140 100 - drive 1Hz pulses 141 101 - drive 4Hz pulses 142 110 - drive 0.25Hz pulses 143 111 - drive 0.25Hz pulses 144 (all pulses with 50% duty cycle) */ 145 #define SUPERIO_SUSL_LDN 9 146 Method (SUSL, 1, Serialized) { 147 ENTER_CONFIG_MODE (SUPERIO_SUSL_LDN) 148 Local0 = SULM 149 Local0 &= 0x1f 150 Local0 |= (Arg0 << 5) 151 SULM = Local0 152 EXIT_CONFIG_MODE () 153 } 154 155#ifdef W83627DHG_SHOW_UARTA 156 #undef SUPERIO_UART_LDN 157 #undef SUPERIO_UART_DDN 158 #undef SUPERIO_UART_PM_REG 159 #undef SUPERIO_UART_PM_VAL 160 #undef SUPERIO_UART_PM_LDN 161 #define SUPERIO_UART_LDN 2 162 #define SUPERIO_UART_PM_REG UAPW 163 #define SUPERIO_UART_PM_VAL 0 164 #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE 165 #include <superio/acpi/pnp_uart.asl> 166#endif 167 168#ifdef W83627DHG_SHOW_UARTB 169 #undef SUPERIO_UART_LDN 170 #undef SUPERIO_UART_DDN 171 #undef SUPERIO_UART_PM_REG 172 #undef SUPERIO_UART_PM_VAL 173 #undef SUPERIO_UART_PM_LDN 174 #define SUPERIO_UART_LDN 3 175 #define SUPERIO_UART_PM_REG UBPW 176 #define SUPERIO_UART_PM_VAL 0 177 #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE 178 #include <superio/acpi/pnp_uart.asl> 179#endif 180 181#ifdef W83627DHG_SHOW_KBC 182 #undef SUPERIO_KBC_LDN 183 #undef SUPERIO_KBC_PS2M 184 #undef SUPERIO_KBC_PS2LDN 185 #define SUPERIO_KBC_LDN 5 186#ifdef W83627DHG_SHOW_PS2M 187 #define SUPERIO_KBC_PS2M 1 188#endif 189 #include <superio/acpi/pnp_kbc.asl> 190#endif 191 192#ifdef W83627DHG_SHOW_HWMON 193 #undef SUPERIO_PNP_LDN 194 #undef SUPERIO_PNP_DDN 195 #undef SUPERIO_PNP_NO_DIS 196 #undef SUPERIO_PNP_PM_REG 197 #undef SUPERIO_PNP_PM_VAL 198 #undef SUPERIO_PNP_PM_LDN 199 #undef SUPERIO_PNP_IO0 200 #undef SUPERIO_PNP_IO1 201 #undef SUPERIO_PNP_IRQ0 202 #undef SUPERIO_PNP_IRQ1 203 #undef SUPERIO_PNP_DMA 204 #define SUPERIO_PNP_LDN 11 205 #define SUPERIO_PNP_PM_REG HWPW 206 #define SUPERIO_PNP_PM_VAL 0 207 #define SUPERIO_PNP_PM_LDN PNP_NO_LDN_CHANGE 208 #define SUPERIO_PNP_IO0 0x08, 0x08 209 #define SUPERIO_PNP_IRQ0 1 210 #include <superio/acpi/pnp_generic.asl> 211#endif 212} 213