1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <arch/io.h>
4 #include <device/pnp_ops.h>
5 #include <stdint.h>
6 #include "w83627dhg.h"
7
pnp_enter_ext_func_mode(pnp_devfn_t dev)8 void pnp_enter_ext_func_mode(pnp_devfn_t dev)
9 {
10 u16 port = dev >> 8;
11 outb(0x87, port);
12 outb(0x87, port);
13 }
14
pnp_exit_ext_func_mode(pnp_devfn_t dev)15 void pnp_exit_ext_func_mode(pnp_devfn_t dev)
16 {
17 u16 port = dev >> 8;
18 outb(0xaa, port);
19 }
20
21 /**
22 * Select Pin 89, Pin 90 function as I2C interface SDA, SCL.
23 * {Pin 89, Pin 90} function can be selected as {GP33, GP32}, or
24 * {RSTOUT3#, RSTOUT2#} or {SDA, SCL}
25 */
w83627dhg_enable_i2c(pnp_devfn_t dev)26 void w83627dhg_enable_i2c(pnp_devfn_t dev)
27 {
28 u8 val;
29
30 pnp_enter_ext_func_mode(dev);
31 pnp_set_logical_device(dev);
32
33 val = pnp_read_config(dev, 0x2A);
34 val |= 1 << 1;
35 pnp_write_config(dev, 0x2A, val);
36
37 pnp_exit_ext_func_mode(dev);
38 }
39
w83627dhg_set_clksel_48(pnp_devfn_t dev)40 void w83627dhg_set_clksel_48(pnp_devfn_t dev)
41 {
42 u8 reg8;
43
44 pnp_enter_ext_func_mode(dev);
45 reg8 = pnp_read_config(dev, 0x24);
46 reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */
47 pnp_write_config(dev, 0x24, reg8);
48 pnp_exit_ext_func_mode(dev);
49 }
50