1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 #include <commonlib/helpers.h>
6
7 static const struct pad_config gpio_table[] = {
8 /* A16 : SD_OC_ODL */
9 PAD_CFG_GPI(GPP_A16, NONE, DEEP),
10 /* A18 : LAN_PE_ISOLATE_ODL */
11 PAD_CFG_GPO(GPP_A18, 1, DEEP),
12 /* A23 : M2_WLAN_INT_ODL */
13 PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
14
15 /* B5 : LAN_CLKREQ_ODL */
16 PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
17
18 /* C0 : SMBCLK */
19 PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
20 /* C1 : SMBDATA */
21 PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
22 /* C6: M2_WLAN_WAKE_ODL */
23 PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE),
24 /* C7 : LAN_WAKE_ODL */
25 PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE),
26 /* C10 : PCH_PCON_RST_ODL */
27 PAD_CFG_GPO(GPP_C10, 1, DEEP),
28 /* C11 : PCH_PCON_PDB_ODL */
29 PAD_CFG_GPO(GPP_C11, 1, DEEP),
30 /* C15 : WLAN_OFF_L */
31 PAD_CFG_GPO(GPP_C15, 1, DEEP),
32
33 /* E2 : EN_PP_MST_OD */
34 PAD_CFG_GPO(GPP_E2, 1, DEEP),
35 /* E9 : USB_A0_OC_ODL */
36 PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
37 /* E10 : USB_A1_OC_ODL */
38 PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
39
40 /* F11 : EMMC_CMD */
41 PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
42 /* F12 : EMMC_DATA0 */
43 PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
44 /* F13 : EMMC_DATA1 */
45 PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
46 /* F14 : EMMC_DATA2 */
47 PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
48 /* F15 : EMMC_DATA3 */
49 PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
50 /* F16 : EMMC_DATA4 */
51 PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
52 /* F17 : EMMC_DATA5 */
53 PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
54 /* F18 : EMMC_DATA6 */
55 PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
56 /* F19 : EMMC_DATA7 */
57 PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
58 /* F20 : EMMC_RCLK */
59 PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
60 /* F21 : EMMC_CLK */
61 PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
62 /* F22 : EMMC_RST_L */
63 PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
64
65 /* H4: PCH_I2C_PCON_SDA */
66 PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
67 /* H5: PCH_I2C_PCON_SCL */
68 PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
69 /* H22 : PWM_PP3300_BIOZZER */
70 PAD_CFG_GPO(GPP_H22, 0, DEEP),
71 };
72
override_gpio_table(size_t * num)73 const struct pad_config *override_gpio_table(size_t *num)
74 {
75 *num = ARRAY_SIZE(gpio_table);
76 return gpio_table;
77 }
78
79 /* Early pad configuration in bootblock */
80 static const struct pad_config early_gpio_table[] = {
81 /* B14 : GPP_B14_STRAP */
82 PAD_NC(GPP_B14, NONE),
83 /* B22 : GPP_B22_STRAP */
84 PAD_NC(GPP_B22, NONE),
85 /* E19 : GPP_E19_STRAP */
86 PAD_NC(GPP_E19, NONE),
87 /* E21 : GPP_E21_STRAP */
88 PAD_NC(GPP_E21, NONE),
89 /* B15 : H1_SLAVE_SPI_CS_L */
90 PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
91 /* B16 : H1_SLAVE_SPI_CLK */
92 PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
93 /* B17 : H1_SLAVE_SPI_MISO_R */
94 PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
95 /* B18 : H1_SLAVE_SPI_MOSI_R */
96 PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
97 /* C14 : BT_DISABLE_L */
98 PAD_CFG_GPO(GPP_C14, 0, DEEP),
99 /* PCH_WP_OD */
100 PAD_CFG_GPI(GPP_C20, NONE, DEEP),
101 /* C21 : H1_PCH_INT_ODL */
102 PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
103 /* C23 : WLAN_PE_RST# */
104 PAD_CFG_GPO(GPP_C23, 1, DEEP),
105 /* E1 : M2_SSD_PEDET */
106 PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
107 /* E5 : SATA_DEVSLP1 */
108 PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
109 };
110
variant_early_gpio_table(size_t * num)111 const struct pad_config *variant_early_gpio_table(size_t *num)
112 {
113 *num = ARRAY_SIZE(early_gpio_table);
114 return early_gpio_table;
115 }
116