1chip soc/intel/cannonlake 2 # Auto-switch between X4 NVMe and X2 NVMe. 3 register "TetonGlacierMode" = "1" 4 5 register "SerialIoDevMode" = "{ 6 [PchSerialIoIndexI2C0] = PchSerialIoDisabled, 7 [PchSerialIoIndexI2C1] = PchSerialIoDisabled, 8 [PchSerialIoIndexI2C2] = PchSerialIoPci, 9 [PchSerialIoIndexI2C3] = PchSerialIoPci, 10 [PchSerialIoIndexI2C4] = PchSerialIoPci, 11 [PchSerialIoIndexI2C5] = PchSerialIoPci, 12 [PchSerialIoIndexSPI0] = PchSerialIoPci, 13 [PchSerialIoIndexSPI1] = PchSerialIoPci, 14 [PchSerialIoIndexSPI2] = PchSerialIoDisabled, 15 [PchSerialIoIndexUART0] = PchSerialIoSkipInit, 16 [PchSerialIoIndexUART1] = PchSerialIoDisabled, 17 [PchSerialIoIndexUART2] = PchSerialIoDisabled, 18 }" 19 20 # USB configuration 21 register "usb2_ports[0]" = "{ 22 .enable = 1, 23 .ocpin = OC2, 24 .tx_bias = USB2_BIAS_0MV, 25 .tx_emp_enable = USB2_PRE_EMP_ON, 26 .pre_emp_bias = USB2_BIAS_11P25MV, 27 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, 28 }" # Type-A Port 2 29 register "usb2_ports[1]" = "{ 30 .enable = 1, 31 .ocpin = OC1, 32 .tx_bias = USB2_BIAS_0MV, 33 .tx_emp_enable = USB2_PRE_EMP_ON, 34 .pre_emp_bias = USB2_BIAS_28P15MV, 35 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, 36 }" # Type-A Port 1 37 register "usb2_ports[2]" = "{ 38 .enable = 1, 39 .ocpin = OC3, 40 .tx_bias = USB2_BIAS_0MV, 41 .tx_emp_enable = USB2_PRE_EMP_ON, 42 .pre_emp_bias = USB2_BIAS_28P15MV, 43 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, 44 }" # Type-A Port 3 45 register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 46 register "usb2_ports[4]" = "{ 47 .enable = 1, 48 .ocpin = OC_SKIP, 49 .tx_bias = USB2_BIAS_0MV, 50 .tx_emp_enable = USB2_PRE_EMP_ON, 51 .pre_emp_bias = USB2_BIAS_28P15MV, 52 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, 53 }" # Type-A Port 4 54 register "usb2_ports[5]" = "{ 55 .enable = 1, 56 .ocpin = OC0, 57 .tx_bias = USB2_BIAS_0MV, 58 .tx_emp_enable = USB2_PRE_EMP_ON, 59 .pre_emp_bias = USB2_BIAS_28P15MV, 60 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, 61 }" # Type-A port 0 62 register "usb2_ports[6]" = "USB2_PORT_EMPTY" 63 register "usb2_ports[7]" = "USB2_PORT_EMPTY" 64 register "usb2_ports[8]" = "USB2_PORT_EMPTY" 65 register "usb2_ports[9]" = "{ 66 .enable = 1, 67 .ocpin = OC_SKIP, 68 .tx_bias = USB2_BIAS_0MV, 69 .tx_emp_enable = USB2_PRE_EMP_ON, 70 .pre_emp_bias = USB2_BIAS_28P15MV, 71 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, 72 }" # BT 73 74 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 75 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 76 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 77 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C 78 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 79 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 80 81 # Bitmap for Wake Enable on USB attach/detach 82 register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ 83 USB_PORT_WAKE_ENABLE(2) | \ 84 USB_PORT_WAKE_ENABLE(3) | \ 85 USB_PORT_WAKE_ENABLE(5) | \ 86 USB_PORT_WAKE_ENABLE(6)" 87 register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ 88 USB_PORT_WAKE_ENABLE(2) | \ 89 USB_PORT_WAKE_ENABLE(3) | \ 90 USB_PORT_WAKE_ENABLE(5) | \ 91 USB_PORT_WAKE_ENABLE(6)" 92 93 # Enable eMMC HS400 94 register "ScsEmmcHs400Enabled" = "1" 95 96 # EMMC Tx CMD Delay 97 # Refer to EDS-Vol2-14.3.7. 98 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. 99 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. 100 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" 101 102 # EMMC TX DATA Delay 1 103 # Refer to EDS-Vol2-14.3.8. 104 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. 105 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. 106 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" 107 108 # EMMC TX DATA Delay 2 109 # Refer to EDS-Vol2-14.3.9. 110 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. 111 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. 112 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. 113 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. 114 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" 115 116 # EMMC RX CMD/DATA Delay 1 117 # Refer to EDS-Vol2-14.3.10. 118 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. 119 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. 120 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. 121 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. 122 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" 123 124 # EMMC RX CMD/DATA Delay 2 125 # Refer to EDS-Vol2-14.3.12. 126 # [17:16] stands for Rx Clock before Output Buffer, 127 # 00: Rx clock after output buffer, 128 # 01: Rx clock before output buffer, 129 # 10: Automatic selection based on working mode. 130 # 11: Reserved 131 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. 132 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. 133 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" 134 135 # EMMC Rx Strobe Delay 136 # Refer to EDS-Vol2-14.3.11. 137 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. 138 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. 139 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" 140 141 # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. 142 register "PchHdaAudioLinkSsp1" = "0" 143 register "PchHdaAudioLinkDmic0" = "0" 144 145 # Intel Common SoC Config 146 #+-------------------+---------------------------+ 147 #| Field | Value | 148 #+-------------------+---------------------------+ 149 #| GSPI0 | cr50 TPM. Early init is | 150 #| | required to set up a BAR | 151 #| | for TPM communication | 152 #| | before memory is up | 153 #| I2C0 | RFU | 154 #| I2C2 | PS175 | 155 #| I2C3 | MST | 156 #| I2C4 | Audio | 157 #+-------------------+---------------------------+ 158 register "common_soc_config" = "{ 159 .gspi[0] = { 160 .speed_mhz = 1, 161 .early_init = 1, 162 }, 163 .i2c[0] = { 164 .speed = I2C_SPEED_FAST, 165 .rise_time_ns = 0, 166 .fall_time_ns = 0, 167 }, 168 .i2c[2] = { 169 .speed = I2C_SPEED_FAST, 170 .rise_time_ns = 60, 171 .fall_time_ns = 60, 172 }, 173 .i2c[3] = { 174 .speed = I2C_SPEED_FAST, 175 .rise_time_ns = 60, 176 .fall_time_ns = 60, 177 }, 178 .i2c[4] = { 179 .speed = I2C_SPEED_FAST, 180 .rise_time_ns = 60, 181 .fall_time_ns = 60, 182 }, 183 }" 184 185 # PCIe port 7 for LAN 186 register "PcieRpEnable[6]" = "1" 187 register "PcieRpLtrEnable[6]" = "1" 188 # PCIe port 11 (x2) for NVMe hybrid storage devices 189 register "PcieRpEnable[10]" = "1" 190 register "PcieRpLtrEnable[10]" = "1" 191 # Uses CLK SRC 0 192 register "PcieClkSrcUsage[0]" = "6" 193 register "PcieClkSrcClkReq[0]" = "0" 194 195 # GPIO for SD card detect 196 register "sdcard_cd_gpio" = "vSD3_CD_B" 197 198 # SATA port 1 Gen3 Strength 199 # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB 200 register "sata_port[1].TxGen3DeEmphEnable" = "1" 201 register "sata_port[1].TxGen3DeEmph" = "0x20" 202 203 device domain 0 on 204 device pci 04.0 on 205 chip drivers/intel/dptf 206 ## Active Policy 207 register "policies.active[0]" = "{.target=DPTF_CPU, 208 .thresholds={TEMP_PCT(90, 85), 209 TEMP_PCT(85, 75), 210 TEMP_PCT(80, 65), 211 TEMP_PCT(75, 55), 212 TEMP_PCT(70, 45),}}" 213 register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, 214 .thresholds={TEMP_PCT(50, 85), 215 TEMP_PCT(47, 75), 216 TEMP_PCT(45, 65), 217 TEMP_PCT(42, 55), 218 TEMP_PCT(39, 45),}}" 219 220 ## Passive Policy 221 register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" 222 register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" 223 224 ## Critical Policy 225 register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" 226 register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" 227 228 ## Power Limits Control 229 # PL1 is fixed at 15W, avg over 28-32s interval 230 # 25-64W PL2 in 1000mW increments, avg over 28-32s interval 231 register "controls.power_limits.pl1" = "{ 232 .min_power = 15000, 233 .max_power = 15000, 234 .time_window_min = 28 * MSECS_PER_SEC, 235 .time_window_max = 32 * MSECS_PER_SEC, 236 .granularity = 200,}" 237 register "controls.power_limits.pl2" = "{ 238 .min_power = 25000, 239 .max_power = 64000, 240 .time_window_min = 28 * MSECS_PER_SEC, 241 .time_window_max = 32 * MSECS_PER_SEC, 242 .granularity = 1000,}" 243 244 ## Charger Performance Control (Control, mA) 245 register "controls.charger_perf[0]" = "{ 255, 1700 }" 246 register "controls.charger_perf[1]" = "{ 24, 1500 }" 247 register "controls.charger_perf[2]" = "{ 16, 1000 }" 248 register "controls.charger_perf[3]" = "{ 8, 500 }" 249 250 ## Fan Performance Control (Percent, Speed, Noise, Power) 251 register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" 252 register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" 253 register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" 254 register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" 255 register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" 256 register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" 257 register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" 258 register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" 259 register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" 260 register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" 261 262 # Fan options 263 register "options.fan.fine_grained_control" = "1" 264 register "options.fan.step_size" = "2" 265 266 device generic 0 on end 267 end 268 end # DPTF 0x1903 269 device pci 14.0 on 270 chip drivers/usb/acpi 271 device usb 0.0 on 272 chip drivers/usb/acpi 273 register "desc" = ""USB2 Type-A Front Left"" 274 register "type" = "UPC_TYPE_A" 275 register "group" = "ACPI_PLD_GROUP(0, 0)" 276 device usb 2.0 on end 277 end 278 chip drivers/usb/acpi 279 register "desc" = ""USB2 Type-C Port Rear"" 280 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" 281 register "group" = "ACPI_PLD_GROUP(1, 3)" 282 device usb 2.1 on end 283 end 284 chip drivers/usb/acpi 285 register "desc" = ""USB2 Type-A Front Right"" 286 register "type" = "UPC_TYPE_A" 287 register "group" = "ACPI_PLD_GROUP(0, 1)" 288 device usb 2.2 on end 289 end 290 chip drivers/usb/acpi 291 register "desc" = ""USB2 Type-A Rear Right"" 292 register "type" = "UPC_TYPE_A" 293 register "group" = "ACPI_PLD_GROUP(1, 2)" 294 device usb 2.3 on end 295 end 296 chip drivers/usb/acpi 297 register "desc" = ""USB2 Type-A Rear Middle"" 298 register "type" = "UPC_TYPE_A" 299 register "group" = "ACPI_PLD_GROUP(1, 1)" 300 device usb 2.4 on end 301 end 302 chip drivers/usb/acpi 303 register "desc" = ""USB2 Type-A Rear Left"" 304 register "type" = "UPC_TYPE_A" 305 register "group" = "ACPI_PLD_GROUP(1, 0)" 306 device usb 2.5 on end 307 end 308 chip drivers/usb/acpi 309 device usb 2.6 off end 310 end 311 chip drivers/usb/acpi 312 register "desc" = ""USB3 Type-A Front Left"" 313 register "type" = "UPC_TYPE_USB3_A" 314 register "group" = "ACPI_PLD_GROUP(0, 0)" 315 device usb 3.0 on end 316 end 317 chip drivers/usb/acpi 318 register "desc" = ""USB3 Type-A Front Right"" 319 register "type" = "UPC_TYPE_USB3_A" 320 register "group" = "ACPI_PLD_GROUP(0, 1)" 321 device usb 3.1 on end 322 end 323 chip drivers/usb/acpi 324 register "desc" = ""USB3 Type-A Rear Right"" 325 register "type" = "UPC_TYPE_USB3_A" 326 register "group" = "ACPI_PLD_GROUP(1, 2)" 327 device usb 3.2 on end 328 end 329 chip drivers/usb/acpi 330 register "desc" = ""USB3 Type-C Rear"" 331 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" 332 register "group" = "ACPI_PLD_GROUP(1, 3)" 333 device usb 3.3 on end 334 end 335 chip drivers/usb/acpi 336 register "desc" = ""USB3 Type-A Rear Left"" 337 register "type" = "UPC_TYPE_USB3_A" 338 register "group" = "ACPI_PLD_GROUP(1, 0)" 339 device usb 3.4 on end 340 end 341 chip drivers/usb/acpi 342 register "desc" = ""USB3 Type-A Rear Middle"" 343 register "type" = "UPC_TYPE_USB3_A" 344 register "group" = "ACPI_PLD_GROUP(1, 1)" 345 device usb 3.5 on end 346 end 347 end 348 end 349 end # USB xHCI 350 device pci 15.0 off 351 # RFU - Reserved for Future Use. 352 end # I2C #0 353 device pci 15.1 off end # I2C #1 354 device pci 15.2 on 355 chip drivers/i2c/generic 356 register "hid" = ""1AF80175"" 357 register "name" = ""PS17"" 358 register "desc" = ""Parade PS175"" 359 device i2c 4a on end 360 end 361 end # I2C #2, PCON PS175. 362 device pci 15.3 on 363 chip drivers/i2c/generic 364 register "hid" = ""10EC2142"" 365 register "name" = ""RTD2"" 366 register "desc" = ""Realtek RTD2142"" 367 device i2c 4a on end 368 end 369 end # I2C #3, Realtek RTD2142. 370 device pci 19.0 on 371 chip drivers/i2c/generic 372 register "hid" = ""10EC5682"" 373 register "name" = ""RT58"" 374 register "desc" = ""Realtek RT5682"" 375 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" 376 register "property_count" = "1" 377 # Set the jd_src to RT5668_JD1 for jack detection 378 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" 379 register "property_list[0].name" = ""realtek,jd-src"" 380 register "property_list[0].integer" = "1" 381 device i2c 1a on end 382 end 383 end #I2C #4 384 device pci 1a.0 on end # eMMC 385 device pci 1c.6 on 386 chip drivers/net 387 register "customized_leds" = "0x05af" 388 register "wake" = "GPE0_DW1_07" # GPP_C7 389 register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" 390 register "stop_delay_ms" = "12" # NIC needs time to quiesce 391 register "stop_off_delay_ms" = "1" 392 register "has_power_resource" = "1" 393 register "device_index" = "0" 394 device pci 00.0 on end 395 end 396 end # RTL8111H Ethernet NIC 397 device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) 398 device pci 1e.3 off end # GSPI #1 399 end 400 401 # VR Settings Configuration for 4 Domains 402 #+----------------+-------+-------+-------+-------+ 403 #| Domain/Setting | SA | IA | GTUS | GTS | 404 #+----------------+-------+-------+-------+-------+ 405 #| Psi1Threshold | 20A | 20A | 20A | 20A | 406 #| Psi2Threshold | 5A | 5A | 5A | 5A | 407 #| Psi3Threshold | 1A | 1A | 1A | 1A | 408 #| Psi3Enable | 1 | 1 | 1 | 1 | 409 #| Psi4Enable | 1 | 1 | 1 | 1 | 410 #| ImonSlope | 0 | 0 | 0 | 0 | 411 #| ImonOffset | 0 | 0 | 0 | 0 | 412 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 413 #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | 414 #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | 415 #+----------------+-------+-------+-------+-------+ 416 #Note: IccMax settings are moved to SoC code 417 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ 418 .vr_config_enable = 1, 419 .psi1threshold = VR_CFG_AMP(20), 420 .psi2threshold = VR_CFG_AMP(5), 421 .psi3threshold = VR_CFG_AMP(1), 422 .psi3enable = 1, 423 .psi4enable = 1, 424 .imon_slope = 0x0, 425 .imon_offset = 0x0, 426 .icc_max = 0, 427 .voltage_limit = 1520, 428 .ac_loadline = 1004, 429 .dc_loadline = 1004, 430 }" 431 432 register "domain_vr_config[VR_IA_CORE]" = "{ 433 .vr_config_enable = 1, 434 .psi1threshold = VR_CFG_AMP(20), 435 .psi2threshold = VR_CFG_AMP(5), 436 .psi3threshold = VR_CFG_AMP(1), 437 .psi3enable = 1, 438 .psi4enable = 1, 439 .imon_slope = 0x0, 440 .imon_offset = 0x0, 441 .icc_max = 0, 442 .voltage_limit = 1520, 443 .ac_loadline = 181, 444 .dc_loadline = 181, 445 }" 446 447 register "domain_vr_config[VR_GT_UNSLICED]" = "{ 448 .vr_config_enable = 1, 449 .psi1threshold = VR_CFG_AMP(20), 450 .psi2threshold = VR_CFG_AMP(5), 451 .psi3threshold = VR_CFG_AMP(1), 452 .psi3enable = 1, 453 .psi4enable = 1, 454 .imon_slope = 0x0, 455 .imon_offset = 0x0, 456 .icc_max = 0, 457 .voltage_limit = 1520, 458 .ac_loadline = 319, 459 .dc_loadline = 319, 460 }" 461 462 register "domain_vr_config[VR_GT_SLICED]" = "{ 463 .vr_config_enable = 1, 464 .psi1threshold = VR_CFG_AMP(20), 465 .psi2threshold = VR_CFG_AMP(5), 466 .psi3threshold = VR_CFG_AMP(1), 467 .psi3enable = 1, 468 .psi4enable = 1, 469 .imon_slope = 0x0, 470 .imon_offset = 0x0, 471 .icc_max = 0, 472 .voltage_limit = 1520, 473 .ac_loadline = 319, 474 .dc_loadline = 319, 475 }" 476 477end 478