1 #include <stdint.h>
2
3 #include <arm/api.h>
4 #include <arm/midr.h>
5 #include <cpuinfo.h>
6 #include <cpuinfo/internal-api.h>
7 #include <cpuinfo/log.h>
8
cpuinfo_arm_decode_cache(enum cpuinfo_uarch uarch,uint32_t cluster_cores,uint32_t midr,const struct cpuinfo_arm_chipset chipset[restrict static1],uint32_t cluster_id,uint32_t arch_version,struct cpuinfo_cache l1i[restrict static1],struct cpuinfo_cache l1d[restrict static1],struct cpuinfo_cache l2[restrict static1],struct cpuinfo_cache l3[restrict static1])9 void cpuinfo_arm_decode_cache(
10 enum cpuinfo_uarch uarch,
11 uint32_t cluster_cores,
12 uint32_t midr,
13 const struct cpuinfo_arm_chipset chipset[restrict static 1],
14 uint32_t cluster_id,
15 uint32_t arch_version,
16 struct cpuinfo_cache l1i[restrict static 1],
17 struct cpuinfo_cache l1d[restrict static 1],
18 struct cpuinfo_cache l2[restrict static 1],
19 struct cpuinfo_cache l3[restrict static 1]) {
20 switch (uarch) {
21 #if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_7A__) && !defined(__ARM_ARCH_8A__)
22 case cpuinfo_uarch_xscale:
23 switch (midr_get_part(midr) >> 8) {
24 case 2:
25 /*
26 * PXA 210/25X/26X
27 *
28 * See "Computer Organization and
29 * Design, Revised Printing: The
30 * Hardware/Software Interface" by David
31 * A. Patterson, John L. Hennessy
32 */
33 *l1i = (struct cpuinfo_cache){
34 .size = 16 * 1024, .associativity = 32, .line_size = 32};
35 *l1d = (struct cpuinfo_cache){
36 .size = 16 * 1024, .associativity = 4, .line_size = 64};
37 break;
38 case 4:
39 /* PXA 27X */
40 *l1i = (struct cpuinfo_cache){
41 .size = 32 * 1024, .associativity = 32, .line_size = 32};
42 *l1d = (struct cpuinfo_cache){
43 .size = 32 * 1024, .associativity = 32, .line_size = 32};
44 break;
45 case 6:
46 /*
47 * PXA 3XX
48 *
49 * See
50 * http://download.intel.com/design/intelxscale/31628302.pdf
51 */
52 *l1i = (struct cpuinfo_cache){
53 .size = 32 * 1024, .associativity = 4, .line_size = 32};
54 *l1d = (struct cpuinfo_cache){
55 .size = 32 * 1024, .associativity = 4, .line_size = 32};
56 *l2 = (struct cpuinfo_cache){
57 .size = 256 * 1024, .associativity = 8, .line_size = 32};
58 break;
59 }
60 break;
61 case cpuinfo_uarch_arm11:
62 *l1i = (struct cpuinfo_cache){.size = 16 * 1024, .associativity = 4, .line_size = 32};
63 *l1d = (struct cpuinfo_cache){.size = 16 * 1024, .associativity = 4, .line_size = 32};
64 break;
65 #endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_7A__) && \
66 !defined(__ARM_ARCH_8A__) */
67 #if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__)
68 case cpuinfo_uarch_cortex_a5:
69 /*
70 * Cortex-A5 Technical Reference Manual:
71 * 7.1.1. Memory system
72 * The Cortex-A5 processor has separate instruction
73 * and data caches. The caches have the following
74 * features:
75 * - Data cache is 4-way set-associative.
76 * - Instruction cache is 2-way set-associative.
77 * - The cache line length is eight words.
78 * - You can configure the instruction and data
79 * caches independently during implementation to sizes
80 * of 4KB, 8KB, 16KB, 32KB, or 64KB. 1.1.3. System
81 * design components PrimeCell Level 2 Cache Controller
82 * (PL310) The addition of an on-chip secondary cache,
83 * also referred to as a Level 2 or L2 cache, is a
84 * recognized method of improving the performance of
85 * ARM-based systems when significant memory traffic is
86 * generated by the processor. The PrimeCell Level 2
87 * Cache Controller reduces the number of external
88 * memory accesses and has been optimized for use with
89 * the Cortex-A5 processor. 8.1.7. Exclusive L2 cache
90 * The Cortex-A5 processor can be connected to an L2
91 * cache that supports an exclusive cache mode. This
92 * mode must be activated both in the Cortex-A5
93 * processor and in the L2 cache controller.
94 *
95 * +--------------------+-----------+-----------+----------+-----------+
96 * | Processor model | L1D cache | L1I cache | L2
97 * cache | Reference |
98 * +--------------------+-----------+-----------+----------+-----------+
99 * | Qualcomm MSM7225A | | | | |
100 * | Qualcomm MSM7625A | | | | |
101 * | Qualcomm MSM7227A | | | | |
102 * | Qualcomm MSM7627A | 32K | 32K | 256K
103 * | Wiki [1] | | Qualcomm MSM7225AB | | | |
104 * | | Qualcomm MSM7225AB | | | | |
105 * | Qualcomm QSD8250 | | | | |
106 * | Qualcomm QSD8650 | | | | |
107 * +--------------------+-----------+-----------+----------+-----------+
108 * | Spreadtrum SC6821 | 32K | 32K | ?
109 * | | | Spreadtrum SC6825 | 32K | 32K
110 * | 256K | Wiki [2] | | Spreadtrum SC8810 | ?
111 * | ? | ? | | | Spreadtrum
112 * SC8825 | 32K | 32K | ? | |
113 * +--------------------+-----------+-----------+----------+-----------+
114 *
115 * [1]
116 * https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_systems-on-chip#Snapdragon_S1
117 * [2] https://en.wikipedia.org/wiki/Spreadtrum
118 */
119 *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 32};
120 *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 32};
121 *l2 = (struct cpuinfo_cache){
122 .size = 256 * 1024,
123 /*
124 * Follow NXP specification: "Eight-way
125 * set-associative 512 kB L2 cache with 32B line
126 * size" Reference:
127 * http://www.nxp.com/assets/documents/data/en/application-notes/AN4947.pdf
128 */
129 .associativity = 8,
130 .line_size = 32};
131 break;
132 case cpuinfo_uarch_cortex_a7:
133 /*
134 * Cortex-A7 MPCore Technical Reference Manual:
135 * 6.1. About the L1 memory system
136 * The L1 memory system consists of separate
137 * instruction and data caches. You can configure the
138 * instruction and data caches independently during
139 * implementation to sizes of 8KB, 16KB, 32KB, or 64KB.
140 *
141 * The L1 instruction memory system has the following
142 * features:
143 * - Instruction side cache line length of 32-bytes.
144 * - 2-way set-associative instruction cache.
145 *
146 * The L1 data memory system has the following
147 * features:
148 * - Data side cache line length of 64-bytes.
149 * - 4-way set-associative data cache.
150 *
151 * 7.1. About the L2 Memory system
152 * The L2 memory system consists of an:
153 * - Optional tightly-coupled L2 cache that includes:
154 * - Configurable L2 cache size of 128KB, 256KB,
155 * 512KB, and 1MB.
156 * - Fixed line length of 64 bytes
157 * - 8-way set-associative cache structure
158 *
159 * +--------------------+-------+-----------+-----------+-----------+-----------+
160 * | Processor model | Cores | L1D cache | L1I cache
161 * | L2 cache | Reference |
162 * +--------------------+-------+-----------+-----------+-----------+-----------+
163 * | Allwinner A20 | 2 | 32K | 32K |
164 * 256K | [1] | | Allwinner A23 | 2 | 32K
165 * | 32K | 256K | [2] | | Allwinner A31 |
166 * 4 | 32K | 32K | 1M | [3] | |
167 * Allwinner A31s | 4 | 32K | 32K |
168 * 1M | [4] | | Allwinner A33 | 4 | 32K
169 * | 32K | 512K | [5] | | Allwinner A80
170 * Octa | 4(+4) | 32K | 32K | 512K(+2M) | [6]
171 * | | Allwinner A81T | 8 | 32K | 32K |
172 * 1M | [7] |
173 * +--------------------+-------+-----------+-----------+-----------+-----------+
174 * | Broadcom BCM2836 | 4 | 32K | 32K |
175 * 512K | [8]
176 * |
177 * +--------------------+-------+-----------+-----------+-----------+-----------+
178 * | Kirin 920 | 4(+4) | ? | ? |
179 * 512K | [9]
180 * |
181 * +--------------------+-------+-----------+-----------+-----------+-----------+
182 *
183 * [1] https://linux-sunxi.org/A20
184 * [2] https://linux-sunxi.org/A23
185 * [3]
186 * http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20datasheet%20V1.3%2020131106.pdf
187 * [4]
188 * https://github.com/allwinner-zh/documents/blob/master/A31s/A31s_Datasheet_v1.5_20150510.pdf
189 * [5]
190 * http://dl.linux-sunxi.org/A33/A33_Datasheet_release1.0.pdf
191 * [6]
192 * https://linux-sunxi.org/images/1/10/A80_Datasheet_Revision_1.0_0404.pdf
193 * [7]
194 * http://dl.linux-sunxi.org/A83T/A83T_datasheet_Revision_1.1.pdf
195 * [8]
196 * https://www.raspberrypi.org/forums/viewtopic.php?t=98428
197 * [9]
198 * http://www.gizmochina.com/2014/10/07/hisilicon-kirin-920-tear-down/
199 */
200 *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 32};
201 *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64};
202 *l2 = (struct cpuinfo_cache){
203 .size = 128 * 1024 * cluster_cores, .associativity = 8, .line_size = 64};
204 break;
205 case cpuinfo_uarch_cortex_a8:
206 /*
207 * Cortex-A8 Technical Reference Manual:
208 * 7.1. About the L1 memory system
209 * The L1 memory system consists of separate
210 * instruction and data caches in a Harvard arrangement.
211 * The L1 memory system provides the core with:
212 * - fixed line length of 64 bytes
213 * - support for 16KB or 32KB caches
214 * - 4-way set associative cache structure
215 * 8.1. About the L2 memory system
216 * The L2 memory system is tightly coupled to the L1
217 * data cache and L1 instruction cache. The key features
218 * of the L2 memory system include:
219 * - configurable cache size of 0KB, 128KB, 256KB,
220 * 512KB, and 1MB
221 * - fixed line length of 64 bytes
222 * - 8-way set associative cache structure
223 *
224 * +----------------------+-----------+-----------+-----------+-----------+
225 * | Processor model | L1D cache | L1I cache | L2
226 * cache | Reference
227 * |
228 * +----------------------+-----------+-----------+-----------+-----------+
229 * | Exynos 3 Single 3110 | 32K | 32K |
230 * 512K | [1] |
231 * +----------------------+-----------+-----------+-----------+-----------+
232 * | TI DM 3730 | 32K | 32K |
233 * 256K | [2] |
234 * +----------------------+-----------+-----------+-----------+-----------+
235 *
236 * [1]
237 * https://en.wikichip.org/w/images/0/04/Exynos_3110.pdf
238 * [2] https://www.ti.com/lit/ds/symlink/dm3725.pdf
239 */
240 *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64};
241 *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64};
242 *l2 = (struct cpuinfo_cache){.associativity = 8, .line_size = 64};
243 switch (chipset->vendor) {
244 case cpuinfo_arm_chipset_vendor_samsung:
245 l2->size = 512 * 1024;
246 break;
247 default:
248 l2->size = 256 * 1024;
249 break;
250 }
251
252 break;
253 case cpuinfo_uarch_cortex_a9:
254 /*
255 * ARM Cortex‑A9 Technical Reference Manual:
256 * 7.1.1 Memory system
257 * The Cortex‑A9 processor has separate instruction
258 * and data caches. The caches have the following
259 * features:
260 * - Both caches are 4-way set-associative.
261 * - The cache line length is eight words.
262 * - You can configure the instruction and data
263 * caches independently during implementation to sizes
264 * of 16KB, 32KB, or 64KB. 8.1.5 Exclusive L2 cache The
265 * Cortex‑A9 processor can be connected to an L2 cache
266 * that supports an exclusive cache mode. This mode must
267 * be activated both in the Cortex‑A9 processor and in
268 * the L2 cache controller.
269 *
270 * +--------------------+-------+-----------+-----------+-----------+-----------+
271 * | Processor model | Cores | L1D cache | L1I cache
272 * | L2 cache | Reference |
273 * +--------------------+-------+-----------+-----------+-----------+-----------+
274 * | Exynos 4 Dual 4210 | 2 | 32K | 32K |
275 * 1M | [1] | | Exynos 4 Dual 4212 | 2 | 32K
276 * | 32K | 1M | [2] | | Exynos 4 Quad
277 * 4412 | 4 | 32K | 32K | 1M | [3]
278 * | | Exynos 4 Quad 4415 | 4 | 32K | 32K
279 * | 1M | | | TI OMAP 4430 | 2 | 32K
280 * | 32K | 1M | [4] | | TI OMAP 4460 |
281 * 2 | 32K | 32K | 1M | [5] |
282 * +--------------------+-------+-----------+-----------+-----------+-----------+
283 *
284 * [1]
285 * http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_45nm_User_Manaul_Public_REV1.00-0.pdf
286 * [2]
287 * http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_32nm_User_Manaul_Public_REV100-0.pdf
288 * [3]
289 * http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Quad_User_Manaul_Public_REV1.00-0.pdf
290 * [4]
291 * https://www.hotchips.org/wp-content/uploads/hc_archives/hc21/2_mon/HC21.24.400.ClientProcessors-Epub/HC21.24.421.Witt-OMAP4430.pdf
292 * [5]
293 * http://www.anandtech.com/show/5310/samsung-galaxy-nexus-ice-cream-sandwich-review/9
294 */
295
296 /* Use Exynos 4 specs */
297 *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 32};
298 *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 32};
299 *l2 = (struct cpuinfo_cache){
300 .size = 1024 * 1024,
301 /* OMAP4460 in Pandaboard ES has 16-way
302 set-associative L2 cache */
303 .associativity = 16,
304 .line_size = 32};
305 break;
306 case cpuinfo_uarch_cortex_a15:
307 /*
308 * 6.1. About the L1 memory system
309 * The L1 memory system consists of separate
310 * instruction and data caches. The L1 instruction
311 * memory system has the following features:
312 * - 32KB 2-way set-associative instruction cache.
313 * - Fixed line length of 64 bytes.
314 * The L1 data memory system has the following
315 * features:
316 * - 32KB 2-way set-associative data cache.
317 * - Fixed line length of 64 bytes.
318 * 7.1. About the L2 memory system
319 * The features of the L2 memory system include:
320 * - Configurable L2 cache size of 512KB, 1MB, 2MB
321 * and 4MB.
322 * - Fixed line length of 64 bytes.
323 * - 16-way set-associative cache structure.
324 *
325 * +--------------------+-------+-----------+-----------+-----------+-----------+
326 * | Processor model | Cores | L1D cache | L1I cache
327 * | L2 cache | Reference |
328 * +--------------------+-------+-----------+-----------+-----------+-----------+
329 * | Exynos 5 Dual 5250 | 2 | 32K | 32K |
330 * 1M | [1] | | Exynos 5 Hexa 5260 | 2(+4) | 32K
331 * | 32K | 1M(+512K) | [2] | | Exynos 5 Octa
332 * 5410 | 4(+4) | 32K | 32K | 2M(+512K) |
333 * [3] | | Exynos 5 Octa 5420 | 4(+4) | 32K |
334 * 32K | 2M(+512K) | [3] | | Exynos 5 Octa 5422 |
335 * 4(+4) | 32K | 32K | 2M(+512K) | [3] |
336 * | Exynos 5 Octa 5430 | 4(+4) | 32K | 32K |
337 * 2M(+512K) | [3] | | Exynos 5 Octa 5800 | 4(+4)
338 * | 32K | 32K | 2M(+512K) | [3] | |
339 * Kirin 920 | 4(+4) | ? | ? |
340 * 2M(+512K) | [4] |
341 * +--------------------+-------+-----------+-----------+-----------+-----------+
342 *
343 * [1]
344 * http://www.arndaleboard.org/wiki/downloads/supports/Exynos_5_Dual_User_Manaul_Public_REV1.00.pdf
345 * [2]
346 * http://www.yicsystem.com/wp-content/uploads/2014/08/Espresso5260P-Guide-Book.pdf
347 * [3]
348 * http://www.anandtech.com/show/6768/samsung-details-exynos-5-octa-architecture-power-at-isscc-13
349 * [4]
350 * http://www.gizmochina.com/2014/10/07/hisilicon-kirin-920-tear-down/
351 */
352 *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 64};
353 *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 64};
354 *l2 = (struct cpuinfo_cache){
355 .size = cluster_cores * 512 * 1024, .associativity = 16, .line_size = 64};
356 break;
357 case cpuinfo_uarch_cortex_a17:
358 /*
359 * ARM Cortex-A17 MPCore Processor Technical Reference
360 * Manual: 6.1. About the L1 memory system The L1 memory
361 * system consists of separate instruction and data
362 * caches. The size of the instruction cache is
363 * implemented as either 32KB or 64KB. The size of the
364 * data cache is 32KB.
365 *
366 * The L1 instruction cache has the following
367 * features:
368 * - Instruction side cache line length of 64-bytes.
369 * - 4-way set-associative instruction cache.
370 *
371 * The L1 data cache has the following features:
372 * - Data side cache line length of 64-bytes.
373 * - 4-way set-associative data cache.
374 *
375 * 7.1. About the L2 Memory system
376 * An integrated L2 cache:
377 * - The cache size is implemented as either 256KB,
378 * 512KB, 1MB, 2MB, 4MB or 8MB.
379 * - A fixed line length of 64 bytes.
380 * - 16-way set-associative cache structure.
381 *
382 * +------------------+-------+-----------+-----------+-----------+-----------+
383 * | Processor model | Cores | L1D cache | L1I cache |
384 * L2 cache | Reference |
385 * +------------------+-------+-----------+-----------+-----------+-----------+
386 * | MediaTek MT6595 | 4(+4) | 32K | 32K |
387 * 2M(+512K) | [1] |
388 * +------------------+-------+-----------+-----------+-----------+-----------+
389 *
390 * [1] https://blog.osakana.net/archives/5268
391 */
392 *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64};
393 *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64};
394 *l2 = (struct cpuinfo_cache){
395 .size = cluster_cores * 512 * 1024, .associativity = 16, .line_size = 64};
396 break;
397 #endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__) */
398 case cpuinfo_uarch_cortex_a35:
399 /*
400 * ARM Cortex‑A35 Processor Technical Reference Manual:
401 * 6.1. About the L1 memory system
402 * The L1 memory system includes several power-saving
403 * and performance-enhancing features. These include
404 * separate instruction and data caches, which can be
405 * configured independently during implementation to
406 * sizes of 8KB, 16KB, 32KB, or 64KB.
407 *
408 * L1 instruction-side memory system
409 * A dedicated instruction cache that:
410 * - is virtually indexed and physically tagged.
411 * - is 2-way set associative.
412 * - is configurable to be 8KB, 16KB, 32KB, or
413 * 64KB.
414 * - uses a cache line length of 64 bytes.
415 *
416 * L1 data-side memory system
417 * A dedicated data cache that:
418 * - is physically indexed and physically tagged.
419 * - is 4-way set associative.
420 * - is configurable to be 8KB, 16KB, 32KB, or
421 * 64KB.
422 * - uses a cache line length of 64 bytes.
423 *
424 * 7.1. About the L2 memory system
425 * The L2 cache is 8-way set associative.
426 * Further features of the L2 cache are:
427 * - Configurable size of 128KB, 256KB, 512KB, and
428 * 1MB.
429 * - Fixed line length of 64 bytes.
430 * - Physically indexed and tagged.
431 *
432 * +-----------------+---------+-----------+-----------+-----------+-----------+
433 * | Processor model | Cores | L1D cache | L1I cache
434 * | L2 cache | Reference |
435 * +-----------------+---------+-----------+-----------+-----------+-----------+
436 * | MediaTek MT6599 | 4(+4+2) | ? | ? | ?
437 * | |
438 * +-----------------+---------+-----------+-----------+-----------+-----------+
439 */
440 *l1i = (struct cpuinfo_cache){
441 .size = 16 * 1024, /* assumption based on
442 low-end Cortex-A53 */
443 .associativity = 2,
444 .line_size = 64};
445 *l1d = (struct cpuinfo_cache){
446 .size = 16 * 1024, /* assumption based on
447 low-end Cortex-A53 */
448 .associativity = 4,
449 .line_size = 64};
450 *l2 = (struct cpuinfo_cache){
451 .size = 256 * 1024, /* assumption based on
452 low-end Cortex-A53 */
453 .associativity = 8,
454 .line_size = 64};
455 break;
456 case cpuinfo_uarch_cortex_a53:
457 /*
458 * ARM Cortex-A53 MPCore Processor Technical Reference
459 * Manual: 6.1. About the L1 memory system The L1 memory
460 * system consists of separate instruction and data
461 * caches. The implementer configures the instruction
462 * and data caches independently during implementation,
463 * to sizes of 8KB, 16KB, 32KB, or 64KB.
464 *
465 * The L1 Instruction memory system has the following
466 * key features:
467 * - Instruction side cache line length of 64 bytes.
468 * - 2-way set associative L1 Instruction cache.
469 *
470 * The L1 Data memory system has the following
471 * features:
472 * - Data side cache line length of 64 bytes.
473 * - 4-way set associative L1 Data cache.
474 *
475 * 7.1. About the L2 memory system
476 * The L2 memory system consists of an:
477 * - Optional tightly-coupled L2 cache that includes:
478 * - Configurable L2 cache size of 128KB, 256KB,
479 * 512KB, 1MB and 2MB.
480 * - Fixed line length of 64 bytes.
481 * - 16-way set-associative cache structure.
482 *
483 * +--------------------+-------+-----------+-----------+-----------+-----------+
484 * | Processor model | Cores | L1D cache | L1I cache
485 * | L2 cache | Reference |
486 * +--------------------+-------+-----------+-----------+-----------+-----------+
487 * | Broadcom BCM2837 | 4 | 16K | 16K |
488 * 512K | [1] | | Exynos 7420 | 4(+4) | 32K
489 * | 32K | 256K | [2, 3] | | Exynos 8890 |
490 * 4(+4) | 32K | 32K | 256K | [4] | |
491 * Rochchip RK3368 | 4+4 | 32K | 32K |
492 * 512K+256K | sysfs | | MediaTek MT8173C | 2(+2)
493 * | 32K | 32K | 512K(+1M) | sysfs | |
494 * Snapdragon 410 | 4 | 32K | 32K |
495 * 512K | [3] | | Snapdragon 630 | 4+4 |
496 * 32K | 32K | 1M+512K | sysfs | |
497 * Snapdragon 636 | 4(+4) | 32K+64K | 32K+64K |
498 * 1M+1M | sysfs | | Snapdragon 660 | 4(+4) |
499 * 32K+64K | 32K+64K | 1M+1M | sysfs | |
500 * Snapdragon 835 | 4(+4) | 32K+64K | 32K+64K |
501 * 1M(+2M) | sysfs | | Kirin 620 | 4+4 |
502 * 32K | 32K | 512K | [5]
503 * |
504 * +--------------------+-------+-----------+-----------+-----------+-----------+
505 *
506 * [1]
507 * https://www.raspberrypi.org/forums/viewtopic.php?f=91&t=145766
508 * [2]
509 * http://www.anandtech.com/show/9330/exynos-7420-deep-dive/2
510 * [3]
511 * https://www.usenix.org/system/files/conference/usenixsecurity16/sec16_paper_lipp.pdf
512 * [4]
513 * http://www.boardset.com/products/products_v8890.php
514 * [5]
515 * http://mirror.lemaker.org/Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
516 */
517 if (midr_is_qualcomm_cortex_a53_silver(midr)) {
518 /* Qualcomm-modified Cortex-A53 in Snapdragon
519 * 630/660/835 */
520
521 uint32_t l2_size = 512 * 1024;
522 switch (chipset->series) {
523 case cpuinfo_arm_chipset_series_qualcomm_msm:
524 if (chipset->model == 8998) {
525 /* Snapdragon 835
526 * (MSM8998): 1 MB L2
527 * (little cores only)
528 */
529 l2_size = 1024 * 1024;
530 }
531 break;
532 case cpuinfo_arm_chipset_series_qualcomm_snapdragon:
533 switch (chipset->model) {
534 case 630:
535 if (cluster_id == 0) {
536 /* Snapdragon
537 * 630:
538 * 1 MB
539 * L2
540 * for
541 * the
542 * big
543 * cores
544 */
545 l2_size = 1024 * 1024;
546 }
547 break;
548 case 636:
549 /* Snapdragon
550 * 636: 1 MB L2
551 * (little cores
552 * only) */
553 l2_size = 1024 * 1024;
554 break;
555 case 660:
556 /* Snapdragon
557 * 660: 1 MB L2
558 * (little cores
559 * only) */
560 l2_size = 1024 * 1024;
561 break;
562 }
563 break;
564 default:
565 break;
566 }
567
568 *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 64};
569 *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64};
570 *l2 = (struct cpuinfo_cache){.size = l2_size, .associativity = 16, .line_size = 64};
571 } else {
572 /* Standard Cortex-A53 */
573
574 /* Use conservative values by default */
575 uint32_t l1_size = 16 * 1024;
576 uint32_t l2_size = 256 * 1024;
577 switch (chipset->series) {
578 case cpuinfo_arm_chipset_series_qualcomm_msm:
579 l1_size = 32 * 1024;
580 l2_size = 512 * 1024;
581 switch (chipset->model) {
582 case 8937: /* Snapdragon
583 430 */
584 case 8940: /* Snapdragon
585 435 */
586 case 8953: /* Snapdragon
587 625 or 626
588 (8953PRO)
589 */
590 if (cluster_id == 0) {
591 /* 1M L2
592 * for
593 * big
594 * cluster
595 */
596 l2_size = 1024 * 1024;
597 }
598 break;
599 case 8952: /* Snapdragon
600 617 */
601 if (cluster_id != 0) {
602 /* 256K
603 * L2
604 * for
605 * LITTLE
606 * cluster
607 */
608 l2_size = 256 * 1024;
609 }
610 break;
611 default:
612 /* Silence
613 * compiler
614 * warning about
615 * unhandled
616 * enum values
617 */
618 break;
619 }
620 break;
621 case cpuinfo_arm_chipset_series_qualcomm_apq:
622 l1_size = 32 * 1024;
623 l2_size = 512 * 1024;
624 break;
625 case cpuinfo_arm_chipset_series_qualcomm_snapdragon:
626 l1_size = 32 * 1024;
627 l2_size = 512 * 1024;
628 if (chipset->model == 450 && cluster_id == 0) {
629 /* Snapdragon 450: 1M L2
630 * for big cluster */
631 l2_size = 1024 * 1024;
632 }
633 break;
634 case cpuinfo_arm_chipset_series_hisilicon_hi:
635 l1_size = 32 * 1024;
636 l2_size = 512 * 1024;
637 break;
638 case cpuinfo_arm_chipset_series_hisilicon_kirin:
639 l1_size = 32 * 1024;
640 switch (chipset->model) {
641 case 970: /* Kirin 970
642 */
643 l2_size = 1024 * 1024;
644 break;
645 default:
646 l2_size = 512 * 1024;
647 break;
648 }
649 break;
650 case cpuinfo_arm_chipset_series_mediatek_mt:
651 switch (chipset->model) {
652 case 8173:
653 l1_size = 32 * 1024;
654 l2_size = 512 * 1024;
655 break;
656 }
657 break;
658 case cpuinfo_arm_chipset_series_rockchip_rk:
659 l1_size = 32 * 1024;
660 switch (chipset->model) {
661 case 3368:
662 if (cluster_id == 0) {
663 /* RK3368:
664 * 512
665 * KB L2
666 * for
667 * the
668 * big
669 * cores
670 */
671 l2_size = 512 * 1024;
672 }
673 break;
674 }
675 break;
676 case cpuinfo_arm_chipset_series_broadcom_bcm:
677 switch (chipset->model) {
678 case 2837: /* BCM2837 */
679 l2_size = 512 * 1024;
680 break;
681 }
682 break;
683 case cpuinfo_arm_chipset_series_samsung_exynos:
684 l1_size = 32 * 1024;
685 break;
686 default:
687 /* Silence compiler warning
688 * about unhandled enum values
689 */
690 break;
691 }
692 *l1i = (struct cpuinfo_cache){.size = l1_size, .associativity = 2, .line_size = 64};
693 *l1d = (struct cpuinfo_cache){.size = l1_size, .associativity = 4, .line_size = 64};
694 *l2 = (struct cpuinfo_cache){.size = l2_size, .associativity = 16, .line_size = 64};
695 }
696 break;
697 case cpuinfo_uarch_cortex_a55r0:
698 case cpuinfo_uarch_cortex_a55:
699 /*
700 * ARM Cortex-A55 Core Technical Reference Manual
701 * A6.1. About the L1 memory system
702 * The Cortex®-A55 core's L1 memory system enhances
703 * core performance and power efficiency. It consists of
704 * separate instruction and data caches. You can
705 * configure instruction and data caches independently
706 * during implementation to sizes of 16KB, 32KB, or
707 * 64KB.
708 *
709 * L1 instruction-side memory system
710 * The L1 instruction-side memory system provides an
711 * instruction stream to the DPU. Its key features are:
712 * - 64-byte instruction side cache line length.
713 * - 4-way set associative L1 instruction cache.
714 *
715 * L1 data-side memory system
716 * - 64-byte data side cache line length.
717 * - 4-way set associative L1 data cache.
718 *
719 * A7.1 About the L2 memory system
720 * The Cortex-A55 L2 memory system is required to
721 * interface the Cortex-A55 cores to the L3 memory
722 * system. The L2 memory subsystem consists of:
723 * - An optional 4-way, set-associative L2 cache with
724 * a configurable size of 64KB, 128KB or 256KB. Cache
725 * lines have a fixed length of 64 bytes.
726 *
727 * The main features of the L2 memory system are:
728 * - Strictly exclusive with L1 data cache.
729 * - Pseudo-inclusive with L1 instruction cache.
730 * - Private per-core unified L2 cache.
731 *
732 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
733 * | Processor model | Cores | L1D cache | L1I cache
734 * | L2 cache | L3 cache | Reference |
735 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
736 * | Snapdragon 845 | 4(+4) | 32K | 32K |
737 * 128K | 2M | [1], sysfs | | Exynos 9810 |
738 * 4(+4) | ? | ? | None | 512K |
739 * [2] | | Kirin 980 | 4(+4) | 32K | 32K
740 * | 128K | 4M | [3] |
741 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
742 *
743 * [1]
744 * https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc
745 * [2]
746 * https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results
747 * [3] https://en.wikichip.org/wiki/hisilicon/kirin/980
748 */
749 if (midr_is_qualcomm_cortex_a55_silver(midr)) {
750 /* Qualcomm-modified Cortex-A55 in Snapdragon
751 * 670 / 710 / 845 */
752 uint32_t l3_size = 1024 * 1024;
753 switch (chipset->series) {
754 case cpuinfo_arm_chipset_series_qualcomm_snapdragon:
755 /* Snapdragon 845: 2M L3 cache
756 */
757 if (chipset->model == 845) {
758 l3_size = 2 * 1024 * 1024;
759 }
760 break;
761 default:
762 break;
763 }
764
765 *l1i = (struct cpuinfo_cache){
766 .size = 32 * 1024,
767 .associativity = 4,
768 .line_size = 64,
769 };
770 *l1d = (struct cpuinfo_cache){
771 .size = 32 * 1024,
772 .associativity = 4,
773 .line_size = 64,
774 };
775 *l2 = (struct cpuinfo_cache){
776 .size = 128 * 1024,
777 .associativity = 4,
778 .line_size = 64,
779 };
780 *l3 = (struct cpuinfo_cache){
781 .size = l3_size,
782 .associativity = 16,
783 .line_size = 64,
784 };
785 } else {
786 /* Standard Cortex-A55 */
787
788 *l1i = (struct cpuinfo_cache){
789 .size = 32 * 1024,
790 .associativity = 4,
791 .line_size = 64,
792 };
793 *l1d = (struct cpuinfo_cache){
794 .size = 32 * 1024,
795 .associativity = 4,
796 .line_size = 64,
797 };
798 if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos) {
799 *l2 = (struct cpuinfo_cache){
800 .size = 512 * 1024,
801 /* DynamIQ */
802 .associativity = 16,
803 .line_size = 64,
804 };
805 } else {
806 uint32_t l3_size = 1024 * 1024;
807 switch (chipset->series) {
808 case cpuinfo_arm_chipset_series_hisilicon_kirin:
809 /* Kirin 980: 4M L3
810 * cache */
811 if (chipset->model == 980) {
812 l3_size = 4 * 1024 * 1024;
813 }
814 break;
815 default:
816 break;
817 }
818 *l2 = (struct cpuinfo_cache){
819 .size = 128 * 1024,
820 .associativity = 4,
821 .line_size = 64,
822 };
823 *l3 = (struct cpuinfo_cache){
824 .size = l3_size,
825 /* DynamIQ */
826 .associativity = 16,
827 .line_size = 64,
828 };
829 }
830 }
831 break;
832 case cpuinfo_uarch_cortex_a57:
833 /*
834 * ARM Cortex-A57 MPCore Processor Technical Reference
835 * Manual: 6.1. About the L1 memory system The L1 memory
836 * system consists of separate instruction and data
837 * caches.
838 *
839 * The L1 instruction memory system has the following
840 * features:
841 * - 48KB 3-way set-associative instruction cache.
842 * - Fixed line length of 64 bytes.
843 *
844 * The L1 data memory system has the following
845 * features:
846 * - 32KB 2-way set-associative data cache.
847 * - Fixed line length of 64 bytes.
848 *
849 * 7.1 About the L2 memory system
850 * The features of the L2 memory system include:
851 * - Configurable L2 cache size of 512KB, 1MB, and
852 * 2MB.
853 * - Fixed line length of 64 bytes.
854 * - 16-way set-associative cache structure.
855 * - Inclusion property with L1 data caches.
856 *
857 * +--------------------+-------+-----------+-----------+-----------+-----------+
858 * | Processor model | Cores | L1D cache | L1I cache
859 * | L2 cache | Reference |
860 * +--------------------+-------+-----------+-----------+-----------+-----------+
861 * | Snapdragon 810 | 4(+4) | 32K | 48K |
862 * 2M | [1] | | Exynos 7420 | 4(+4) | 32K
863 * | 48K | 2M | [2] | | Jetson TX1 | 4
864 * | 32K | 48K | 2M | [3] |
865 * +--------------------+-------+-----------+-----------+-----------+-----------+
866 *
867 * [1]
868 * http://www.anandtech.com/show/9837/snapdragon-820-preview
869 * [2]
870 * http://www.anandtech.com/show/9330/exynos-7420-deep-dive/2
871 * [3]
872 * https://devblogs.nvidia.com/parallelforall/jetson-tx2-delivers-twice-intelligence-edge/
873 */
874 *l1i = (struct cpuinfo_cache){.size = 48 * 1024, .associativity = 3, .line_size = 64};
875 *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 64};
876 *l2 = (struct cpuinfo_cache){
877 .size = cluster_cores * 512 * 1024,
878 .associativity = 16,
879 .line_size = 64,
880 .flags = CPUINFO_CACHE_INCLUSIVE};
881 break;
882 case cpuinfo_uarch_cortex_a65: {
883 /*
884 * ARM Cortex‑A65 Core Technical Reference Manual
885 * A6.1. About the L1 memory system
886 * The L1 memory system enhances the performance and
887 * power efficiency in the Cortex‑A65 core. It consists
888 * of separate instruction and data caches. You can
889 * configure instruction and data caches independently
890 * during implementation to sizes of 32KB or 64KB.
891 *
892 * L1 instruction-side memory system
893 * The L1 instruction-side memory system provides an
894 * instruction stream to the DPU. Its key features are:
895 * - 64-byte instruction side cache line length.
896 * - 4-way set associative L1 instruction cache.
897 *
898 * L1 data-side memory system
899 * - 64-byte data side cache line length.
900 * - 4-way set associative L1 data cache.
901 *
902 * A7.1 About the L2 memory system
903 * The Cortex‑A65 L2 memory system is required to
904 * interface the Cortex‑A65 cores to the L3 memory
905 * system. The L2 memory subsystem consists of:
906 * - An optional 4-way, set-associative L2 cache with
907 * a configurable size of 64KB, 128KB, or 256KB. Cache
908 * lines have a fixed length of 64 bytes.
909 *
910 * The main features of the L2 memory system are:
911 * - Strictly exclusive with L1 data cache.
912 * - Pseudo-inclusive with L1 instruction cache.
913 * - Private per-core unified L2 cache.
914 */
915 const uint32_t l1_size = 32 * 1024;
916 const uint32_t l2_size = 128 * 1024;
917 const uint32_t l3_size = 512 * 1024;
918 *l1i = (struct cpuinfo_cache){
919 .size = l1_size,
920 .associativity = 4,
921 .line_size = 64,
922 };
923 *l1d = (struct cpuinfo_cache){
924 .size = l1_size,
925 .associativity = 4,
926 .line_size = 64,
927 };
928 *l2 = (struct cpuinfo_cache){
929 .size = l2_size, .associativity = 4, .line_size = 64, .flags = CPUINFO_CACHE_INCLUSIVE};
930 *l3 = (struct cpuinfo_cache){
931 .size = l3_size,
932 /* DynamIQ */
933 .associativity = 16,
934 .line_size = 64,
935 };
936 break;
937 }
938 case cpuinfo_uarch_cortex_a72: {
939 /*
940 * ARM Cortex-A72 MPCore Processor Technical Reference
941 * Manual 6.1. About the L1 memory system The L1 memory
942 * system consists of separate instruction and data
943 * caches.
944 *
945 * The L1 instruction memory system has the following
946 * features:
947 * - 48KB 3-way set-associative instruction cache.
948 * - Fixed line length of 64 bytes.
949 *
950 * The L1 data memory system has the following
951 * features:
952 * - 32KB 2-way set-associative data cache.
953 * - Fixed cache line length of 64 bytes.
954 *
955 * 7.1 About the L2 memory system
956 * The features of the L2 memory system include:
957 * - Configurable L2 cache size of 512KB, 1MB, 2MB
958 * and 4MB.
959 * - Fixed line length of 64 bytes.
960 * - Banked pipeline structures.
961 * - Inclusion property with L1 data caches.
962 * - 16-way set-associative cache structure.
963 *
964 * +---------------------+---------+-----------+-----------+------------+-----------+
965 * | Processor model | Cores | L1D cache | L1I
966 * cache | L2 cache | Reference |
967 * +---------------------+---------+-----------+-----------+------------+-----------+
968 * | Snapdragon 650 | 2(+4) | 32K(+32K) |
969 * 48K(+32K) | 1M(+512K) | [1] | | Snapdragon 652 |
970 * 4(+4) | 32K(+32K) | 48K(+32K) | 1M(+512K) | [2]
971 * | | Snapdragon 653 | 4(+4) | 32K(+32K) |
972 * 48K(+32K) | 1M(+512K) | [3] | | HiSilicon
973 * Kirin 950 | 4(+4) | 32K+32K | 48K+32K | ? |
974 * | | HiSilicon Kirin 955 | 4(+4) | 32K+32K |
975 * 48K+32K | ? | | | MediaTek
976 * MT8173C | 2(+2) | 32K(+32K) | 48K(+32K) |
977 * 1M(+512K) | sysfs | | MediaTek Helio X20 |
978 * 2(+4+4) | ? | ? | ? | | |
979 * MediaTek Helio X23 | 2(+4+4) | ? | ? |
980 * ? | | | MediaTek Helio X25 | 2(+4+4) | ? |
981 * ? | ? | | | MediaTek Helio X27 |
982 * 2(+4+4) | ? | ? | ? | | |
983 * Broadcom BCM2711 | 4 | 32K | 48K |
984 * 1M | [4] |
985 * +---------------------+---------+-----------+-----------+------------+-----------+
986 *
987 * [1]
988 * http://pdadb.net/index.php?m=processor&id=578&c=qualcomm_snapdragon_618_msm8956__snapdragon_650
989 * [2]
990 * http://pdadb.net/index.php?m=processor&id=667&c=qualcomm_snapdragon_620_apq8076__snapdragon_652
991 * [3]
992 * http://pdadb.net/index.php?m=processor&id=692&c=qualcomm_snapdragon_653_msm8976sg__msm8976_pro
993 * [4]
994 * https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/README.md
995 */
996 uint32_t l2_size;
997 switch (chipset->series) {
998 case cpuinfo_arm_chipset_series_hisilicon_kirin:
999 l2_size = 2 * 1024 * 1024;
1000 break;
1001 default:
1002 l2_size = 1024 * 1024;
1003 break;
1004 }
1005
1006 *l1i = (struct cpuinfo_cache){.size = 48 * 1024, .associativity = 3, .line_size = 64};
1007 *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 64};
1008 *l2 = (struct cpuinfo_cache){
1009 .size = l2_size,
1010 .associativity = 16,
1011 .line_size = 64,
1012 .flags = CPUINFO_CACHE_INCLUSIVE};
1013 break;
1014 }
1015 case cpuinfo_uarch_cortex_a73: {
1016 /*
1017 * ARM Cortex‑A73 MPCore Processor Technical Reference
1018 * Manual 6.1. About the L1 memory system The L1 memory
1019 * system consists of separate instruction and data
1020 * caches. The size of the instruction cache is 64KB.
1021 * The size of the data cache is configurable to either
1022 * 32KB or 64KB.
1023 *
1024 * The L1 instruction memory system has the following
1025 * key features:
1026 * - Virtually Indexed, Physically Tagged (VIPT),
1027 * four-way set-associative instruction cache.
1028 * - Fixed cache line length of 64 bytes.
1029 *
1030 * The L1 data memory system has the following
1031 * features:
1032 * - ...the data cache behaves like an eight-way set
1033 * associative PIPT cache (for 32KB configurations) and
1034 * a 16-way set associative PIPT cache (for 64KB
1035 * configurations).
1036 * - Fixed cache line length of 64 bytes.
1037 *
1038 * 7.1 About the L2 memory system
1039 * The L2 memory system consists of:
1040 * - A tightly-integrated L2 cache with:
1041 * - A configurable size of 256KB, 512KB, 1MB, 2MB,
1042 * 4MB, or 8MB.
1043 * - A 16-way, set-associative structure.
1044 * - A fixed line length of 64 bytes.
1045 *
1046 * The ARM Cortex A73 - Artemis Unveiled [1]
1047 * "ARM still envisions that most vendors will choose
1048 * to use configurations of 1 to 2MB in consumer
1049 * products. The L2 cache is inclusive of the L1 cache.
1050 * "
1051 *
1052 * +---------------------+---------+-----------+-----------+-----------+-----------+
1053 * | Processor model | Cores | L1D cache | L1I
1054 * cache | L2 cache | Reference |
1055 * +---------------------+---------+-----------+-----------+-----------+-----------+
1056 * | HiSilicon Kirin 960 | 4(+4) | 64K+32K |
1057 * 64K+32K | ? | [2] | | MediaTek Helio X30
1058 * | 2(+4+4) | ? | 64K+ ? | ? | | |
1059 * Snapdragon 636 | 4(+4) | 64K(+32K) | 64K(+32K)
1060 * | 1M(+1M) | sysfs | | Snapdragon 660 | 4(+4)
1061 * | 64K+32K | 64K+32K | 1M(+1M) | [3] | |
1062 * Snapdragon 835 | 4(+4) | 64K+32K | 64K+32K
1063 * | 2M(+1M) | sysfs |
1064 * +---------------------+---------+-----------+-----------+-----------+-----------+
1065 *
1066 * [1]
1067 * http://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2
1068 * [2]
1069 * http://www.anandtech.com/show/11088/hisilicon-kirin-960-performance-and-power/3
1070 * [3]
1071 * https://arstechnica.com/gadgets/2017/05/qualcomms-snapdragon-660-and-630-bring-more-high-end-features-to-midrange-chips/
1072 */
1073 uint32_t l1d_size = 32 * 1024;
1074 uint32_t l2_size = 512 * 1024;
1075 switch (chipset->series) {
1076 case cpuinfo_arm_chipset_series_hisilicon_kirin:
1077 l1d_size = 64 * 1024;
1078 l2_size = 2 * 1024 * 1024;
1079 break;
1080 case cpuinfo_arm_chipset_series_mediatek_mt:
1081 l1d_size = 64 * 1024;
1082 l2_size = 1 * 1024 * 1024; /* TODO: verify assumption
1083 */
1084 break;
1085 default:
1086 switch (midr) {
1087 case UINT32_C(0x51AF8001): /* Kryo 280
1088 Gold */
1089 l1d_size = 64 * 1024;
1090 l2_size = 2 * 1024 * 1024;
1091 break;
1092 case UINT32_C(0x51AF8002): /* Kryo 260
1093 Gold */
1094 l1d_size = 64 * 1024;
1095 l2_size = 1 * 1024 * 1024;
1096 break;
1097 }
1098 }
1099
1100 *l1i = (struct cpuinfo_cache){.size = 64 * 1024, .associativity = 4, .line_size = 64};
1101 *l1d = (struct cpuinfo_cache){
1102 .size = l1d_size, .associativity = (l1d_size >> 12), .line_size = 64};
1103 *l2 = (struct cpuinfo_cache){
1104 .size = l2_size,
1105 .associativity = 16,
1106 .line_size = 64,
1107 .flags = CPUINFO_CACHE_INCLUSIVE};
1108 break;
1109 }
1110 case cpuinfo_uarch_cortex_a75: {
1111 /*
1112 * ARM Cortex-A75 Core Technical Reference Manual
1113 * A6.1. About the L1 memory system
1114 * The L1 memory system consists of separate
1115 * instruction and data caches. Both have a fixed size
1116 * of 64KB.
1117 *
1118 * A6.1.1 L1 instruction-side memory system
1119 * The L1 instruction memory system has the following
1120 * key features:
1121 * - Virtually Indexed, Physically Tagged (VIPT),
1122 * four-way set-associative instruction cache.
1123 * - Fixed cache line length of 64 bytes.
1124 *
1125 * A6.1.2 L1 data-side memory system
1126 * The L1 data memory system has the following
1127 * features:
1128 * - Physically Indexed, Physically Tagged (PIPT),
1129 * 16-way set-associative L1 data cache.
1130 * - Fixed cache line length of 64 bytes.
1131 * - Pseudo-random cache replacement policy.
1132 *
1133 * A7.1 About the L2 memory system
1134 * The L2 memory subsystem consist of:
1135 * - An 8-way set associative L2 cache with a
1136 * configurable size of 256KB or 512KB. Cache lines have
1137 * a fixed length of 64 bytes.
1138 *
1139 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1140 * | Processor model | Cores | L1D cache | L1I cache
1141 * | L2 cache | L3 cache | Reference |
1142 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1143 * | Snapdragon 845 | 4(+4) | 64K | 64K |
1144 * 256K | 2M | [1], sysfs |
1145 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1146 *
1147 * [1]
1148 * https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc
1149 */
1150 uint32_t l3_size = 1024 * 1024;
1151 switch (chipset->series) {
1152 case cpuinfo_arm_chipset_series_qualcomm_snapdragon:
1153 /* Snapdragon 845: 2M L3 cache */
1154 if (chipset->model == 845) {
1155 l3_size = 2 * 1024 * 1024;
1156 }
1157 break;
1158 default:
1159 break;
1160 }
1161 *l1i = (struct cpuinfo_cache){.size = 64 * 1024, .associativity = 4, .line_size = 64};
1162 *l1d = (struct cpuinfo_cache){.size = 64 * 1024, .associativity = 16, .line_size = 64};
1163 *l2 = (struct cpuinfo_cache){.size = 256 * 1024, .associativity = 8, .line_size = 64};
1164 *l3 = (struct cpuinfo_cache){.size = l3_size, .associativity = 16, .line_size = 64};
1165 break;
1166 }
1167 case cpuinfo_uarch_cortex_a76: {
1168 /*
1169 * ARM Cortex-A76 Core Technical Reference Manual
1170 * A6.1. About the L1 memory system
1171 * The L1 memory system consists of separate
1172 * instruction and data caches. Both have a fixed size
1173 * of 64KB.
1174 *
1175 * A6.1.1 L1 instruction-side memory system
1176 * The L1 instruction memory system has the following
1177 * key features:
1178 * - Virtually Indexed, Physically Tagged (VIPT),
1179 * which behaves as a Physically Indexed, Physically
1180 * Tagged (PIPT) 4-way set-associative L1 data cache.
1181 * - Fixed cache line length of 64 bytes.
1182 *
1183 * A6.1.2 L1 data-side memory system
1184 * The L1 data memory system has the following
1185 * features:
1186 * - Virtually Indexed, Physically Tagged (VIPT),
1187 * which behaves as a Physically Indexed, Physically
1188 * Tagged (PIPT) 4-way set-associative L1 data cache.
1189 * - Fixed cache line length of 64 bytes.
1190 * - Pseudo-LRU cache replacement policy.
1191 *
1192 * A7.1 About the L2 memory system
1193 * The L2 memory subsystem consist of:
1194 * - An 8-way set associative L2 cache with a
1195 * configurable size of 128KB, 256KB or 512KB. Cache
1196 * lines have a fixed length of 64 bytes.
1197 * - Strictly inclusive with L1 data cache. Weakly
1198 * inclusive with L1 instruction cache.
1199 * - Dynamic biased replacement policy.
1200 * - Modified Exclusive Shared Invalid (MESI)
1201 * coherency.
1202 *
1203 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1204 * | Processor model | Cores | L1D cache | L1I cache
1205 * | L2 cache | L3 cache | Reference |
1206 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1207 * | Kirin 980 | 4(+4) | 64K | 64K |
1208 * 512K | 4M | [1], [2] |
1209 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1210 *
1211 * [1]
1212 * https://www.anandtech.com/show/13298/hisilicon-announces-the-kirin-980-first-a76-g76-on-7nm
1213 * [2] https://en.wikichip.org/wiki/hisilicon/kirin/980
1214 */
1215 uint32_t l2_size = 256 * 1024;
1216 uint32_t l3_size = 1024 * 1024;
1217 switch (chipset->series) {
1218 case cpuinfo_arm_chipset_series_hisilicon_kirin:
1219 /* Kirin 980: 512K L2 cache + 4M L3
1220 * cache */
1221 if (chipset->model == 980) {
1222 l2_size = 512 * 1024;
1223 l3_size = 4 * 1024 * 1024;
1224 }
1225 break;
1226 default:
1227 break;
1228 }
1229 *l1i = (struct cpuinfo_cache){
1230 .size = 64 * 1024,
1231 .associativity = 4,
1232 .line_size = 64,
1233 };
1234 *l1d = (struct cpuinfo_cache){
1235 .size = 64 * 1024,
1236 .associativity = 4,
1237 .line_size = 64,
1238 };
1239 *l2 = (struct cpuinfo_cache){
1240 .size = l2_size,
1241 .associativity = 8,
1242 .line_size = 64,
1243 .flags = CPUINFO_CACHE_INCLUSIVE,
1244 };
1245 *l3 = (struct cpuinfo_cache){
1246 .size = l3_size,
1247 .associativity = 16,
1248 .line_size = 64,
1249 };
1250 break;
1251 }
1252 case cpuinfo_uarch_cortex_a77: {
1253 /*
1254 * ARM Cortex-A77 Core Technical Reference Manual
1255 * A6.1. About the L1 memory system
1256 * The L1 memory system consists of separate
1257 * instruction and data caches. Both have a fixed size
1258 * of 64KB.
1259 *
1260 * A6.1.1 L1 instruction-side memory system
1261 * The L1 instruction memory system has the following
1262 * key features:
1263 * - Virtually Indexed, Physically Tagged (VIPT),
1264 * which behaves as a Physically Indexed, Physically
1265 * Tagged (PIPT) 4-way set-associative L1 data cache.
1266 * - Fixed cache line length of 64 bytes.
1267 *
1268 * A6.1.2 L1 data-side memory system
1269 * The L1 data memory system has the following
1270 * features:
1271 * - Virtually Indexed, Physically Tagged (VIPT),
1272 * which behaves as a Physically Indexed, Physically
1273 * Tagged (PIPT) 4-way set-associative L1 data cache.
1274 * - Fixed cache line length of 64 bytes.
1275 * - Pseudo-LRU cache replacement policy.
1276 *
1277 * A7.1 About the L2 memory system
1278 * The L2 memory subsystem consist of:
1279 * - An 8-way set associative L2 cache with a
1280 * configurable size of 128KB, 256KB or 512KB. Cache
1281 * lines have a fixed length of 64 bytes.
1282 * - Strictly inclusive with L1 data cache. Weakly
1283 * inclusive with L1 instruction cache.
1284 */
1285 const uint32_t l2_size = 256 * 1024;
1286 const uint32_t l3_size = 1024 * 1024;
1287 *l1i = (struct cpuinfo_cache){
1288 .size = 64 * 1024,
1289 .associativity = 4,
1290 .line_size = 64,
1291 };
1292 *l1d = (struct cpuinfo_cache){
1293 .size = 64 * 1024,
1294 .associativity = 4,
1295 .line_size = 64,
1296 };
1297 *l2 = (struct cpuinfo_cache){
1298 .size = l2_size,
1299 .associativity = 8,
1300 .line_size = 64,
1301 .flags = CPUINFO_CACHE_INCLUSIVE,
1302 };
1303 *l3 = (struct cpuinfo_cache){
1304 .size = l3_size,
1305 .associativity = 16,
1306 .line_size = 64,
1307 };
1308 break;
1309 }
1310 case cpuinfo_uarch_neoverse_n1:
1311 case cpuinfo_uarch_neoverse_v1:
1312 case cpuinfo_uarch_neoverse_n2:
1313 case cpuinfo_uarch_neoverse_v2: {
1314 /*
1315 * The specifications here below are taken from the
1316 * Arm Core Technical Reference Manuals for
1317 * - Neoverse N1:
1318 * https://developer.arm.com/documentation/100616/0401/?lang=en
1319 * - Neoverse N2:
1320 * https://developer.arm.com/documentation/102099/0003/?lang=en
1321 * - Neoverse V1:
1322 * https://developer.arm.com/documentation/101427/0102/?lang=en
1323 * - Neoverse V2:
1324 * https://developer.arm.com/documentation/102375/0002/?lang=en
1325 *
1326 * All four Arm architectures have L1 memory system with
1327 * instruction and data caches, both of fixed size of
1328 * 64KB. The instruction side memory system is 4-way set
1329 * associative with a cache line length of 64 bytes. The
1330 * data cache is also 4-way set associative with a cache
1331 * line length of 64 bytes.
1332 *
1333 * The L2 memory system differs across the four
1334 * Architectures in the minimum length of the L2 cache.
1335 * Namely:
1336 * - Arm Neoverse N1/N2/V1 have a L2 cache of
1337 * configurable size of 256KB, 512KB, or 1024KB
1338 * - Arm Neoverse V2 has a L2 cache of configurable
1339 * size of 1MB or 2MB For all four architectures, the L2
1340 * cache is 8-way set associative For all other
1341 * information, please refer to the technical manuals
1342 * linked above
1343 */
1344 const uint32_t min_l2_size_KB =
1345 (uarch == cpuinfo_uarch_neoverse_v2 || midr_is_ampere_altra(midr)) ? 1024 : 256;
1346 const uint32_t min_l3_size_KB = 0;
1347
1348 *l1i = (struct cpuinfo_cache){
1349 .size = 64 * 1024,
1350 .associativity = 4,
1351 .line_size = 64,
1352 };
1353 *l1d = (struct cpuinfo_cache){
1354 .size = 64 * 1024,
1355 .associativity = 4,
1356 .line_size = 64,
1357 };
1358 *l2 = (struct cpuinfo_cache){
1359 .size = min_l2_size_KB * 1024,
1360 .associativity = 8,
1361 .line_size = 64,
1362 .flags = CPUINFO_CACHE_INCLUSIVE,
1363 };
1364 *l3 = (struct cpuinfo_cache){
1365 .size = min_l3_size_KB * 1024,
1366 .associativity = 16,
1367 .line_size = 64,
1368 };
1369 break;
1370 }
1371 #if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__)
1372 case cpuinfo_uarch_scorpion:
1373 /*
1374 * - "The CPU includes 32KB instruction and data caches
1375 * as well as a complete memory-management unit (MMU)
1376 * suitable for high-level operating systems. The CPU
1377 * also has 256KB of SRAM that can be allocated in 64KB
1378 * increments to level-two (L2) cache or tightly coupled
1379 * memory (TCM)." [1] We interpret it as L2 cache being
1380 * 4-way set-associative on single-core Scorpion.
1381 * - L1 Data Cache = 32 KB. 32 B/line. [2]
1382 * - L2 Cache = 256 KB. 128 B/line. [2]
1383 * - 256 KB (single-core) or 512 KB (dual-core) L2 cache
1384 * [3]
1385 * - Single or dual-core configuration [3]
1386 * - For L1 cache assume the same associativity as Krait
1387 *
1388 * [1]
1389 * https://www.qualcomm.com/media/documents/files/linley-report-on-dual-core-snapdragon.pdf
1390 * [2] http://www.7-cpu.com/cpu/Snapdragon.html
1391 * [3] https://en.wikipedia.org/wiki/Scorpion_(CPU)
1392 */
1393 *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 32};
1394 *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 32};
1395 *l2 = (struct cpuinfo_cache){
1396 .size = cluster_cores * 256 * 1024, .associativity = 4, .line_size = 128};
1397 break;
1398 case cpuinfo_uarch_krait:
1399 /*
1400 * - L0 Data cache = 4 KB. 64 B/line, direct mapped [1]
1401 * - L0 Instruction cache = 4 KB. [1]
1402 * - L1 Data cache = 16 KB. 64 B/line, 4-way [1]
1403 * - L1 Instruction cache = 16 KB, 4-way [1]
1404 * - L2 Cache = 1 MB, 128 B/line, 8-way. Each core has
1405 * fast access only to 512 KB of L2 cache. [1]
1406 * - L2 = 1MB (dual core) or 2MB (quad core), 8-way set
1407 * associative [2]
1408 *
1409 * [1] http://www.7-cpu.com/cpu/Krait.html
1410 * [2]
1411 * http://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture/2
1412 */
1413 *l1i = (struct cpuinfo_cache){
1414 .size = 16 * 1024, .associativity = 4, .line_size = 64 /* assume same as L1D */
1415 };
1416 *l1d = (struct cpuinfo_cache){.size = 16 * 1024, .associativity = 4, .line_size = 64};
1417 *l2 = (struct cpuinfo_cache){
1418 .size = cluster_cores * 512 * 1024, .associativity = 8, .line_size = 128};
1419 break;
1420 #endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__) */
1421 case cpuinfo_uarch_kryo:
1422 /*
1423 * +-----------------+-------+-----------+-----------+-----------+-----------+
1424 * | Processor model | Cores | L1D cache | L1I cache |
1425 * L2 cache | Reference |
1426 * +-----------------+-------+-----------+-----------+-----------+-----------+
1427 * | Snapdragon 820 | 2+2 | 24K | 32K |
1428 * 1M+512K | [1, 2] | | Snapdragon 821 | 2+2 | ?
1429 * | ? | 1M+512K | [1] |
1430 * +-----------------+-------+-----------+-----------+-----------+-----------+
1431 *
1432 * [1]
1433 * http://www.anandtech.com/show/9837/snapdragon-820-preview/2
1434 * [2]
1435 * https://www.inforcecomputing.com/public_docs/Inforce6601/Inforce_6601_Micro-SOM_FAQs_04-2016-1.pdf
1436 */
1437 *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64};
1438 *l1d = (struct cpuinfo_cache){.size = 24 * 1024, .associativity = 3, .line_size = 64};
1439 if (midr_is_kryo_silver(midr)) {
1440 /* Kryo "Silver" */
1441 *l2 = (struct cpuinfo_cache){.size = 512 * 1024, .associativity = 8, .line_size = 128};
1442 } else {
1443 /* Kryo "Gold" */
1444 *l2 = (struct cpuinfo_cache){.size = 1024 * 1024, .associativity = 8, .line_size = 128};
1445 }
1446 break;
1447 case cpuinfo_uarch_denver:
1448 case cpuinfo_uarch_denver2:
1449 /*
1450 * The Denver chip includes a 128KB, 4-way level 1
1451 * instruction cache, a 64KB, 4-way level 2 data cache,
1452 * and a 2MB, 16-way level 2 cache, all of which can
1453 * service both cores. [1]
1454 *
1455 * All the caches have 64-byte lines. [2]
1456 *
1457 * [1]
1458 * http://www.pcworld.com/article/2463900/nvidia-reveals-pc-like-performance-for-denver-tegra-k1.html
1459 * [2]
1460 * http://linleygroup.com/newsletters/newsletter_detail.php?num=5205&year=2014
1461 */
1462 *l1i = (struct cpuinfo_cache){.size = 128 * 1024, .associativity = 4, .line_size = 64};
1463 *l1d = (struct cpuinfo_cache){.size = 64 * 1024, .associativity = 4, .line_size = 64};
1464 *l2 = (struct cpuinfo_cache){.size = 2 * 1024 * 1024, .associativity = 16, .line_size = 64};
1465 break;
1466 case cpuinfo_uarch_exynos_m1:
1467 case cpuinfo_uarch_exynos_m2:
1468 /*
1469 * - "Moving past branch prediction we can see some
1470 * elements of how the cache is set up for the L1 I$,
1471 * namely 64 KB split into four sets with 128-byte line
1472 * sizes for 128 cache lines per set" [1]
1473 * - "For loads and stores, a 32 KB, 8-way set
1474 * associative cache with 64 byte line size is used" [1]
1475 * - "The L2 cache here is 2MB shared across all cores
1476 * split into 16 sets. This memory is also split into 4
1477 * banks and has a 22 cycle latency" [1]
1478 *
1479 * +--------------------+-------+-----------+-----------+-----------+-----------+
1480 * | Processor model | Cores | L1D cache | L1I cache
1481 * | L2 cache | Reference |
1482 * +--------------------+-------+-----------+-----------+-----------+-----------+
1483 * | Exynos 8 Octa 8890 | 4(+4) | 64K | 32K |
1484 * 2M | [1] | | Exynos 8 Octa 8895 | 4(+4) | 64K
1485 * | 32K | 2M | [2] |
1486 * +--------------------+-------+-----------+-----------+-----------+-----------+
1487 *
1488 * [1]
1489 * http://www.anandtech.com/show/10590/hot-chips-2016-exynos-m1-architecture-disclosed
1490 * [2]
1491 * https://www.extremetech.com/mobile/244949-samsungs-exynos-8895-features-custom-cpu-cores-first-10nm-chip-market
1492 */
1493 *l1i = (struct cpuinfo_cache){.size = 64 * 1024, .associativity = 4, .line_size = 128};
1494 *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 8, .line_size = 64};
1495 *l2 = (struct cpuinfo_cache){.size = 2 * 1024 * 1024, .associativity = 16, .line_size = 64};
1496 break;
1497 case cpuinfo_uarch_exynos_m3:
1498 /*
1499 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1500 * | Processor model | Cores | L1D cache | L1I cache
1501 * | L2 cache | L3 cache | Reference |
1502 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1503 * | Exynos 9810 | 4(+4) | 64K | ? |
1504 * 512K | 4M | [1] |
1505 * +--------------------+-------+-----------+-----------+-----------+----------+------------+
1506 *
1507 * [1]
1508 * https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results
1509 */
1510 *l1i = (struct cpuinfo_cache){
1511 .size = 64 * 1024 /* assume same as in Exynos
1512 M1/M2 cores */
1513 ,
1514 .associativity = 4 /* assume same as in Exynos
1515 M1/M2 cores */
1516 ,
1517 .line_size = 128 /* assume same as in Exynos
1518 M1/M2 cores */
1519 };
1520 *l1d = (struct cpuinfo_cache){
1521 .size = 64 * 1024,
1522 .associativity = 8 /* assume same as in Exynos
1523 M1/M2 cores */
1524 ,
1525 .line_size = 64 /* assume same as in Exynos
1526 M1/M2 cores */
1527 ,
1528 };
1529 *l2 = (struct cpuinfo_cache){
1530 .size = 512 * 1024,
1531 .associativity = 16 /* assume same as in Exynos
1532 M1/M2 cores */
1533 ,
1534 .line_size = 64 /* assume same as in Exynos
1535 M1/M2 cores */
1536 ,
1537 };
1538 *l3 = (struct cpuinfo_cache){
1539 .size = 4 * 1024 * 1024,
1540 .associativity = 16 /* assume DynamIQ cache */,
1541 .line_size = 64 /* assume DynamIQ cache */,
1542 };
1543 break;
1544 #if CPUINFO_ARCH_ARM64 && !defined(__ANDROID__)
1545 case cpuinfo_uarch_thunderx:
1546 /*
1547 * "78K-Icache and 32K-D cache per core, 16 MB shared L2
1548 * cache" [1]
1549 *
1550 * [1]
1551 * https://www.cavium.com/pdfFiles/ThunderX_CP_PB_Rev1.pdf
1552 */
1553 *l1i = (struct cpuinfo_cache){
1554 .size = 78 * 1024, .associativity = 4 /* assumption */, .line_size = 64 /* assumption */
1555 };
1556 *l1d = (struct cpuinfo_cache){
1557 .size = 32 * 1024, .associativity = 4 /* assumption */, .line_size = 64 /* assumption */
1558 };
1559 *l2 = (struct cpuinfo_cache){
1560 .size = 16 * 1024 * 1024,
1561 .associativity = 8 /* assumption */,
1562 .line_size = 64 /* assumption */
1563 };
1564 break;
1565 case cpuinfo_uarch_taishan_v110:
1566 /*
1567 * It features private 64 KiB L1 instruction and data
1568 * caches as well as 512 KiB of private L2. [1]
1569 *
1570 * +------------------+-------+-----------+-----------+-----------+----------+-----------+
1571 * | Processor model | Cores | L1D cache | L1I cache |
1572 * L2 cache | L3 cache | Reference |
1573 * +------------------+-------+-----------+-----------+-----------+----------+-----------+
1574 * | Kunpeng 920-3226 | 32 | 64K | 64K |
1575 * 512K | 32M | [2] |
1576 * +------------------+-------+-----------+-----------+-----------+----------+-----------+
1577 * | Kunpeng 920-4826 | 48 | 64K | 64K |
1578 * 512K | 48M | [3] |
1579 * +------------------+-------+-----------+-----------+-----------+----------+-----------+
1580 * | Kunpeng 920-6426 | 64 | 64K | 64K |
1581 * 512K | 64M | [4] |
1582 * +------------------+-------+-----------+-----------+-----------+----------+-----------+
1583 *
1584 * [1]
1585 * https://en.wikichip.org/wiki/hisilicon/microarchitectures/taishan_v110
1586 * [2]
1587 * https://en.wikichip.org/wiki/hisilicon/kunpeng/920-3226
1588 * [3]
1589 * https://en.wikichip.org/wiki/hisilicon/kunpeng/920-4826
1590 * [4]
1591 * https://en.wikichip.org/wiki/hisilicon/kunpeng/920-6426
1592 */
1593 *l1i = (struct cpuinfo_cache){
1594 .size = 64 * 1024,
1595 .associativity = 4 /* assumption */,
1596 .line_size = 128 /* assumption */,
1597 };
1598 *l1d = (struct cpuinfo_cache){
1599 .size = 64 * 1024,
1600 .associativity = 4 /* assumption */,
1601 .line_size = 128 /* assumption */,
1602 };
1603 *l2 = (struct cpuinfo_cache){
1604 .size = 512 * 1024,
1605 .associativity = 8 /* assumption */,
1606 .line_size = 128 /* assumption */,
1607 .flags = CPUINFO_CACHE_INCLUSIVE /* assumption */
1608 ,
1609 };
1610 *l3 = (struct cpuinfo_cache){
1611 .size = cluster_cores * 1024 * 1024,
1612 .associativity = 16 /* assumption */,
1613 .line_size = 128 /* assumption */,
1614 };
1615 break;
1616 #endif
1617 case cpuinfo_uarch_cortex_a12:
1618 case cpuinfo_uarch_cortex_a32:
1619 default:
1620 cpuinfo_log_warning("target uarch not recognized; using generic cache parameters");
1621 /* Follow OpenBLAS */
1622 if (arch_version >= 8) {
1623 *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64};
1624 *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64};
1625 *l2 = (struct cpuinfo_cache){
1626 .size = cluster_cores * 256 * 1024, .associativity = 8, .line_size = 64};
1627 } else {
1628 *l1i = (struct cpuinfo_cache){.size = 16 * 1024, .associativity = 4, .line_size = 32};
1629 *l1d = (struct cpuinfo_cache){.size = 16 * 1024, .associativity = 4, .line_size = 32};
1630 if (arch_version >= 7) {
1631 *l2 = (struct cpuinfo_cache){
1632 .size = cluster_cores * 128 * 1024,
1633 .associativity = 8,
1634 .line_size = 32};
1635 }
1636 }
1637 break;
1638 }
1639 l1i->sets = l1i->size / (l1i->associativity * l1i->line_size);
1640 l1i->partitions = 1;
1641 l1d->sets = l1d->size / (l1d->associativity * l1d->line_size);
1642 l1d->partitions = 1;
1643 if (l2->size != 0) {
1644 l2->sets = l2->size / (l2->associativity * l2->line_size);
1645 l2->partitions = 1;
1646 if (l3->size != 0) {
1647 l3->sets = l3->size / (l3->associativity * l3->line_size);
1648 l3->partitions = 1;
1649 }
1650 }
1651 }
1652
cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor * processor)1653 uint32_t cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor* processor) {
1654 /*
1655 * There is no precise way to detect cache size on ARM/ARM64, and cache
1656 * size reported by cpuinfo may underestimate the actual cache size.
1657 * Thus, we use microarchitecture-specific maximum.
1658 */
1659 switch (processor->core->uarch) {
1660 case cpuinfo_uarch_xscale:
1661 case cpuinfo_uarch_arm11:
1662 case cpuinfo_uarch_scorpion:
1663 case cpuinfo_uarch_krait:
1664 case cpuinfo_uarch_kryo:
1665 case cpuinfo_uarch_exynos_m1:
1666 case cpuinfo_uarch_exynos_m2:
1667 case cpuinfo_uarch_exynos_m3:
1668 /* cpuinfo-detected cache size always correct */
1669 return cpuinfo_compute_max_cache_size(processor);
1670 case cpuinfo_uarch_cortex_a5:
1671 /* Max observed (NXP Vybrid SoC) */
1672 return 512 * 1024;
1673 case cpuinfo_uarch_cortex_a7:
1674 /*
1675 * Cortex-A7 MPCore Technical Reference Manual:
1676 * 7.1. About the L2 Memory system
1677 * The L2 memory system consists of an:
1678 * - Optional tightly-coupled L2 cache that includes:
1679 * - Configurable L2 cache size of 128KB, 256KB,
1680 * 512KB, and 1MB.
1681 */
1682 return 1024 * 1024;
1683 case cpuinfo_uarch_cortex_a8:
1684 /*
1685 * Cortex-A8 Technical Reference Manual:
1686 * 8.1. About the L2 memory system
1687 * The key features of the L2 memory system include:
1688 * - configurable cache size of 0KB, 128KB, 256KB,
1689 * 512KB, and 1MB
1690 */
1691 return 1024 * 1024;
1692 case cpuinfo_uarch_cortex_a9:
1693 /* Max observed (e.g. Exynos 4212) */
1694 return 1024 * 1024;
1695 case cpuinfo_uarch_cortex_a12:
1696 case cpuinfo_uarch_cortex_a17:
1697 /*
1698 * ARM Cortex-A17 MPCore Processor Technical Reference
1699 * Manual: 7.1. About the L2 Memory system The key
1700 * features of the L2 memory system include:
1701 * - An integrated L2 cache:
1702 * - The cache size is implemented as either 256KB,
1703 * 512KB, 1MB, 2MB, 4MB or 8MB.
1704 */
1705 return 8 * 1024 * 1024;
1706 case cpuinfo_uarch_cortex_a15:
1707 /*
1708 * ARM Cortex-A15 MPCore Processor Technical Reference
1709 * Manual: 7.1. About the L2 memory system The features
1710 * of the L2 memory system include:
1711 * - Configurable L2 cache size of 512KB, 1MB, 2MB
1712 * and 4MB.
1713 */
1714 return 4 * 1024 * 1024;
1715 case cpuinfo_uarch_cortex_a35:
1716 /*
1717 * ARM Cortex‑A35 Processor Technical Reference Manual:
1718 * 7.1 About the L2 memory system
1719 * L2 cache
1720 * - Further features of the L2 cache are:
1721 * - Configurable size of 128KB, 256KB, 512KB, and
1722 * 1MB.
1723 */
1724 return 1024 * 1024;
1725 case cpuinfo_uarch_cortex_a53:
1726 /*
1727 * ARM Cortex-A53 MPCore Processor Technical Reference
1728 * Manual: 7.1. About the L2 memory system The L2 memory
1729 * system consists of an:
1730 * - Optional tightly-coupled L2 cache that includes:
1731 * - Configurable L2 cache size of 128KB, 256KB,
1732 * 512KB, 1MB and 2MB.
1733 */
1734 return 2 * 1024 * 1024;
1735 case cpuinfo_uarch_cortex_a57:
1736 /*
1737 * ARM Cortex-A57 MPCore Processor Technical Reference
1738 * Manual: 7.1 About the L2 memory system The features
1739 * of the L2 memory system include:
1740 * - Configurable L2 cache size of 512KB, 1MB, and
1741 * 2MB.
1742 */
1743 return 2 * 1024 * 1024;
1744 case cpuinfo_uarch_cortex_a72:
1745 /*
1746 * ARM Cortex-A72 MPCore Processor Technical Reference
1747 * Manual: 7.1 About the L2 memory system The features
1748 * of the L2 memory system include:
1749 * - Configurable L2 cache size of 512KB, 1MB, 2MB
1750 * and 4MB.
1751 */
1752 return 4 * 1024 * 1024;
1753 case cpuinfo_uarch_cortex_a73:
1754 /*
1755 * ARM Cortex‑A73 MPCore Processor Technical Reference
1756 * Manual 7.1 About the L2 memory system The L2 memory
1757 * system consists of:
1758 * - A tightly-integrated L2 cache with:
1759 * - A configurable size of 256KB, 512KB, 1MB,
1760 * 2MB, 4MB, or 8MB.
1761 */
1762 return 8 * 1024 * 1024;
1763 case cpuinfo_uarch_cortex_a55:
1764 case cpuinfo_uarch_neoverse_n1:
1765 case cpuinfo_uarch_neoverse_v1:
1766 case cpuinfo_uarch_neoverse_n2:
1767 case cpuinfo_uarch_neoverse_v2:
1768 case cpuinfo_uarch_cortex_a75:
1769 case cpuinfo_uarch_cortex_a76:
1770 case cpuinfo_uarch_exynos_m4:
1771 default:
1772 /*
1773 * ARM DynamIQ Shared Unit Technical Reference Manual
1774 * 1.3 Implementation options
1775 * L3_CACHE_SIZE
1776 * - 256KB
1777 * - 512KB
1778 * - 1024KB
1779 * - 1536KB
1780 * - 2048KB
1781 * - 3072KB
1782 * - 4096KB
1783 */
1784 return 4 * 1024 * 1024;
1785 }
1786 }
1787