1 #include <alloca.h>
2 #include <stdint.h>
3 #include <stdio.h>
4 #include <stdlib.h>
5 #include <string.h>
6
7 #include <errno.h>
8 #include <mach/machine.h>
9 #include <sys/sysctl.h>
10 #include <sys/types.h>
11
12 #include <cpuinfo.h>
13 #include <cpuinfo/internal-api.h>
14 #include <cpuinfo/log.h>
15 #include <mach/api.h>
16
17 /* Polyfill recent CPUFAMILY_ARM_* values for older SDKs */
18 #ifndef CPUFAMILY_ARM_VORTEX_TEMPEST
19 #define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07D34B9F
20 #endif
21 #ifndef CPUFAMILY_ARM_LIGHTNING_THUNDER
22 #define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504D2
23 #endif
24 #ifndef CPUFAMILY_ARM_FIRESTORM_ICESTORM
25 #define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1B588BB3
26 #endif
27 #ifndef CPUFAMILY_ARM_AVALANCHE_BLIZZARD
28 #define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D
29 #endif
30
31 struct cpuinfo_arm_isa cpuinfo_isa = {
32 .aes = true,
33 .sha1 = true,
34 .sha2 = true,
35 .pmull = true,
36 .crc32 = true,
37 };
38
get_sys_info(int type_specifier,const char * name)39 static uint32_t get_sys_info(int type_specifier, const char* name) {
40 size_t size = 0;
41 uint32_t result = 0;
42 int mib[2] = {CTL_HW, type_specifier};
43 if (sysctl(mib, 2, NULL, &size, NULL, 0) != 0) {
44 cpuinfo_log_info("sysctl(\"%s\") failed: %s", name, strerror(errno));
45 } else if (size == sizeof(uint32_t)) {
46 sysctl(mib, 2, &result, &size, NULL, 0);
47 cpuinfo_log_debug("%s: %" PRIu32 ", size = %lu", name, result, size);
48 } else {
49 cpuinfo_log_info("sysctl does not support non-integer lookup for (\"%s\")", name);
50 }
51 return result;
52 }
53
get_sys_info_by_name(const char * type_specifier)54 static uint32_t get_sys_info_by_name(const char* type_specifier) {
55 size_t size = 0;
56 uint32_t result = 0;
57 if (sysctlbyname(type_specifier, NULL, &size, NULL, 0) != 0) {
58 cpuinfo_log_info("sysctlbyname(\"%s\") failed: %s", type_specifier, strerror(errno));
59 } else if (size == sizeof(uint32_t)) {
60 sysctlbyname(type_specifier, &result, &size, NULL, 0);
61 cpuinfo_log_debug("%s: %" PRIu32 ", size = %lu", type_specifier, result, size);
62 } else {
63 cpuinfo_log_info("sysctl does not support non-integer lookup for (\"%s\")", type_specifier);
64 }
65 return result;
66 }
67
decode_uarch(uint32_t cpu_family,uint32_t core_index,uint32_t core_count)68 static enum cpuinfo_uarch decode_uarch(uint32_t cpu_family, uint32_t core_index, uint32_t core_count) {
69 switch (cpu_family) {
70 case CPUFAMILY_ARM_CYCLONE:
71 return cpuinfo_uarch_cyclone;
72 case CPUFAMILY_ARM_TYPHOON:
73 return cpuinfo_uarch_typhoon;
74 case CPUFAMILY_ARM_TWISTER:
75 return cpuinfo_uarch_twister;
76 case CPUFAMILY_ARM_HURRICANE:
77 return cpuinfo_uarch_hurricane;
78 case CPUFAMILY_ARM_MONSOON_MISTRAL:
79 /* 2x Monsoon + 4x Mistral cores */
80 return core_index < 2 ? cpuinfo_uarch_monsoon : cpuinfo_uarch_mistral;
81 case CPUFAMILY_ARM_VORTEX_TEMPEST:
82 /* Hexa-core: 2x Vortex + 4x Tempest; Octa-core: 4x
83 * Cortex + 4x Tempest */
84 return core_index + 4 < core_count ? cpuinfo_uarch_vortex : cpuinfo_uarch_tempest;
85 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
86 /* Hexa-core: 2x Lightning + 4x Thunder; Octa-core
87 * (presumed): 4x Lightning + 4x Thunder */
88 return core_index + 4 < core_count ? cpuinfo_uarch_lightning : cpuinfo_uarch_thunder;
89 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
90 /* Hexa-core: 2x Firestorm + 4x Icestorm; Octa-core: 4x
91 * Firestorm + 4x Icestorm */
92 return core_index + 4 < core_count ? cpuinfo_uarch_firestorm : cpuinfo_uarch_icestorm;
93 case CPUFAMILY_ARM_AVALANCHE_BLIZZARD:
94 /* Hexa-core: 2x Avalanche + 4x Blizzard */
95 return core_index + 4 < core_count ? cpuinfo_uarch_avalanche : cpuinfo_uarch_blizzard;
96 default:
97 /* Use hw.cpusubtype for detection */
98 break;
99 }
100
101 return cpuinfo_uarch_unknown;
102 }
103
decode_package_name(char * package_name)104 static void decode_package_name(char* package_name) {
105 size_t size;
106 if (sysctlbyname("hw.machine", NULL, &size, NULL, 0) != 0) {
107 cpuinfo_log_warning("sysctlbyname(\"hw.machine\") failed: %s", strerror(errno));
108 return;
109 }
110
111 char* machine_name = alloca(size);
112 if (sysctlbyname("hw.machine", machine_name, &size, NULL, 0) != 0) {
113 cpuinfo_log_warning("sysctlbyname(\"hw.machine\") failed: %s", strerror(errno));
114 return;
115 }
116 cpuinfo_log_debug("hw.machine: %s", machine_name);
117
118 char name[10];
119 uint32_t major = 0, minor = 0;
120 if (sscanf(machine_name, "%9[^,0123456789]%" SCNu32 ",%" SCNu32, name, &major, &minor) != 3) {
121 cpuinfo_log_warning("parsing \"hw.machine\" failed: %s", strerror(errno));
122 return;
123 }
124
125 uint32_t chip_model = 0;
126 char suffix = '\0';
127 if (strcmp(name, "iPhone") == 0) {
128 /*
129 * iPhone 4 and up are supported:
130 * - iPhone 4 [A4]: iPhone3,1, iPhone3,2, iPhone3,3
131 * - iPhone 4S [A5]: iPhone4,1
132 * - iPhone 5 [A6]: iPhone5,1, iPhone5,2
133 * - iPhone 5c [A6]: iPhone5,3, iPhone5,4
134 * - iPhone 5s [A7]: iPhone6,1, iPhone6,2
135 * - iPhone 6 [A8]: iPhone7,2
136 * - iPhone 6 Plus [A8]: iPhone7,1
137 * - iPhone 6s [A9]: iPhone8,1
138 * - iPhone 6s Plus [A9]: iPhone8,2
139 * - iPhone SE [A9]: iPhone8,4
140 * - iPhone 7 [A10]: iPhone9,1, iPhone9,3
141 * - iPhone 7 Plus [A10]: iPhone9,2, iPhone9,4
142 * - iPhone 8 [A11]: iPhone10,1, iPhone10,4
143 * - iPhone 8 Plus [A11]: iPhone10,2, iPhone10,5
144 * - iPhone X [A11]: iPhone10,3, iPhone10,6
145 * - iPhone XS [A12]: iPhone11,2,
146 * - iPhone XS Max [A12]: iPhone11,4, iPhone11,6
147 * - iPhone XR [A12]: iPhone11,8
148 */
149 chip_model = major + 1;
150 } else if (strcmp(name, "iPad") == 0) {
151 switch (major) {
152 /* iPad 2 and up are supported */
153 case 2:
154 /*
155 * iPad 2 [A5]: iPad2,1, iPad2,2, iPad2,3,
156 * iPad2,4 iPad mini [A5]: iPad2,5, iPad2,6,
157 * iPad2,7
158 */
159 chip_model = major + 3;
160 break;
161 case 3:
162 /*
163 * iPad 3rd Gen [A5X]: iPad3,1, iPad3,2, iPad3,3
164 * iPad 4th Gen [A6X]: iPad3,4, iPad3,5, iPad3,6
165 */
166 chip_model = (minor <= 3) ? 5 : 6;
167 suffix = 'X';
168 break;
169 case 4:
170 /*
171 * iPad Air [A7]: iPad4,1, iPad4,2,
172 * iPad4,3 iPad mini Retina [A7]: iPad4,4,
173 * iPad4,5, iPad4,6 iPad mini 3 [A7]:
174 * iPad4,7, iPad4,8, iPad4,9
175 */
176 chip_model = major + 3;
177 break;
178 case 5:
179 /*
180 * iPad mini 4 [A8]: iPad5,1, iPad5,2
181 * iPad Air 2 [A8X]: iPad5,3, iPad5,4
182 */
183 chip_model = major + 3;
184 suffix = (minor <= 2) ? '\0' : 'X';
185 break;
186 case 6:
187 /*
188 * iPad Pro 9.7" [A9X]: iPad6,3, iPad6,4
189 * iPad Pro [A9X]: iPad6,7, iPad6,8
190 * iPad 5th Gen [A9]: iPad6,11, iPad6,12
191 */
192 chip_model = major + 3;
193 suffix = minor <= 8 ? 'X' : '\0';
194 break;
195 case 7:
196 /*
197 * iPad Pro 12.9" [A10X]: iPad7,1, iPad7,2
198 * iPad Pro 10.5" [A10X]: iPad7,3, iPad7,4
199 * iPad 6th Gen [A10]: iPad7,5, iPad7,6
200 */
201 chip_model = major + 3;
202 suffix = minor <= 4 ? 'X' : '\0';
203 break;
204 default:
205 cpuinfo_log_info("unknown iPad: %s", machine_name);
206 break;
207 }
208 } else if (strcmp(name, "iPod") == 0) {
209 switch (major) {
210 case 5:
211 chip_model = 5;
212 break;
213 /* iPod touch (5th Gen) [A5]: iPod5,1 */
214 case 7:
215 /* iPod touch (6th Gen, 2015) [A8]: iPod7,1 */
216 chip_model = 8;
217 break;
218 default:
219 cpuinfo_log_info("unknown iPod: %s", machine_name);
220 break;
221 }
222 } else {
223 cpuinfo_log_info("unknown device: %s", machine_name);
224 }
225 if (chip_model != 0) {
226 snprintf(package_name, CPUINFO_PACKAGE_NAME_MAX, "Apple A%" PRIu32 "%c", chip_model, suffix);
227 }
228 }
229
cpuinfo_arm_mach_init(void)230 void cpuinfo_arm_mach_init(void) {
231 struct cpuinfo_processor* processors = NULL;
232 struct cpuinfo_core* cores = NULL;
233 struct cpuinfo_cluster* clusters = NULL;
234 struct cpuinfo_package* packages = NULL;
235 struct cpuinfo_uarch_info* uarchs = NULL;
236 struct cpuinfo_cache* l1i = NULL;
237 struct cpuinfo_cache* l1d = NULL;
238 struct cpuinfo_cache* l2 = NULL;
239 struct cpuinfo_cache* l3 = NULL;
240
241 struct cpuinfo_mach_topology mach_topology = cpuinfo_mach_detect_topology();
242 processors = calloc(mach_topology.threads, sizeof(struct cpuinfo_processor));
243 if (processors == NULL) {
244 cpuinfo_log_error(
245 "failed to allocate %zu bytes for descriptions of %" PRIu32 " logical processors",
246 mach_topology.threads * sizeof(struct cpuinfo_processor),
247 mach_topology.threads);
248 goto cleanup;
249 }
250 cores = calloc(mach_topology.cores, sizeof(struct cpuinfo_core));
251 if (cores == NULL) {
252 cpuinfo_log_error(
253 "failed to allocate %zu bytes for descriptions of %" PRIu32 " cores",
254 mach_topology.cores * sizeof(struct cpuinfo_core),
255 mach_topology.cores);
256 goto cleanup;
257 }
258 packages = calloc(mach_topology.packages, sizeof(struct cpuinfo_package));
259 if (packages == NULL) {
260 cpuinfo_log_error(
261 "failed to allocate %zu bytes for descriptions of %" PRIu32 " packages",
262 mach_topology.packages * sizeof(struct cpuinfo_package),
263 mach_topology.packages);
264 goto cleanup;
265 }
266
267 const uint32_t threads_per_core = mach_topology.threads / mach_topology.cores;
268 const uint32_t threads_per_package = mach_topology.threads / mach_topology.packages;
269 const uint32_t cores_per_package = mach_topology.cores / mach_topology.packages;
270
271 for (uint32_t i = 0; i < mach_topology.packages; i++) {
272 packages[i] = (struct cpuinfo_package){
273 .processor_start = i * threads_per_package,
274 .processor_count = threads_per_package,
275 .core_start = i * cores_per_package,
276 .core_count = cores_per_package,
277 };
278 decode_package_name(packages[i].name);
279 }
280
281 const uint32_t cpu_family = get_sys_info_by_name("hw.cpufamily");
282
283 /*
284 * iOS 15 and macOS 12 added sysctls for ARM features, use them where
285 * possible. Otherwise, fallback to hardcoded set of CPUs with known
286 * support.
287 */
288 const uint32_t has_feat_lse = get_sys_info_by_name("hw.optional.arm.FEAT_LSE");
289 if (has_feat_lse != 0) {
290 cpuinfo_isa.atomics = true;
291 } else {
292 // Mandatory in ARMv8.1-A, list only cores released before iOS
293 // 15 / macOS 12
294 switch (cpu_family) {
295 case CPUFAMILY_ARM_MONSOON_MISTRAL:
296 case CPUFAMILY_ARM_VORTEX_TEMPEST:
297 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
298 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
299 cpuinfo_isa.atomics = true;
300 }
301 }
302
303 const uint32_t has_feat_rdm = get_sys_info_by_name("hw.optional.arm.FEAT_RDM");
304 if (has_feat_rdm != 0) {
305 cpuinfo_isa.rdm = true;
306 } else {
307 // Optional in ARMv8.2-A (implemented in Apple cores),
308 // list only cores released before iOS 15 / macOS 12
309 switch (cpu_family) {
310 case CPUFAMILY_ARM_MONSOON_MISTRAL:
311 case CPUFAMILY_ARM_VORTEX_TEMPEST:
312 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
313 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
314 cpuinfo_isa.rdm = true;
315 }
316 }
317
318 const uint32_t has_feat_fp16 = get_sys_info_by_name("hw.optional.arm.FEAT_FP16");
319 if (has_feat_fp16 != 0) {
320 cpuinfo_isa.fp16arith = true;
321 } else {
322 // Optional in ARMv8.2-A (implemented in Apple cores),
323 // list only cores released before iOS 15 / macOS 12
324 switch (cpu_family) {
325 case CPUFAMILY_ARM_MONSOON_MISTRAL:
326 case CPUFAMILY_ARM_VORTEX_TEMPEST:
327 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
328 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
329 cpuinfo_isa.fp16arith = true;
330 }
331 }
332
333 const uint32_t has_feat_fhm = get_sys_info_by_name("hw.optional.arm.FEAT_FHM");
334 if (has_feat_fhm != 0) {
335 cpuinfo_isa.fhm = true;
336 } else {
337 // Prior to iOS 15, use 'hw.optional.armv8_2_fhm'
338 const uint32_t has_feat_fhm_legacy = get_sys_info_by_name("hw.optional.armv8_2_fhm");
339 if (has_feat_fhm_legacy != 0) {
340 cpuinfo_isa.fhm = true;
341 } else {
342 // Mandatory in ARMv8.4-A when FP16 arithmetics is
343 // implemented, list only cores released before iOS 15 /
344 // macOS 12
345 switch (cpu_family) {
346 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
347 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
348 cpuinfo_isa.fhm = true;
349 }
350 }
351 }
352
353 const uint32_t has_feat_bf16 = get_sys_info_by_name("hw.optional.arm.FEAT_BF16");
354 if (has_feat_bf16 != 0) {
355 cpuinfo_isa.bf16 = true;
356 }
357
358 const uint32_t has_feat_fcma = get_sys_info_by_name("hw.optional.arm.FEAT_FCMA");
359 if (has_feat_fcma != 0) {
360 cpuinfo_isa.fcma = true;
361 } else {
362 // Mandatory in ARMv8.3-A, list only cores released before iOS
363 // 15 / macOS 12
364 switch (cpu_family) {
365 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
366 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
367 cpuinfo_isa.fcma = true;
368 }
369 }
370
371 const uint32_t has_feat_jscvt = get_sys_info_by_name("hw.optional.arm.FEAT_JSCVT");
372 if (has_feat_jscvt != 0) {
373 cpuinfo_isa.jscvt = true;
374 } else {
375 // Mandatory in ARMv8.3-A, list only cores released before iOS
376 // 15 / macOS 12
377 switch (cpu_family) {
378 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
379 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
380 cpuinfo_isa.jscvt = true;
381 }
382 }
383
384 const uint32_t has_feat_dotprod = get_sys_info_by_name("hw.optional.arm.FEAT_DotProd");
385 if (has_feat_dotprod != 0) {
386 cpuinfo_isa.dot = true;
387 } else {
388 // Mandatory in ARMv8.4-A, list only cores released before iOS
389 // 15 / macOS 12
390 switch (cpu_family) {
391 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
392 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
393 cpuinfo_isa.dot = true;
394 }
395 }
396
397 const uint32_t has_feat_i8mm = get_sys_info_by_name("hw.optional.arm.FEAT_I8MM");
398 if (has_feat_i8mm != 0) {
399 cpuinfo_isa.i8mm = true;
400 }
401
402 const uint32_t has_feat_sme = get_sys_info_by_name("hw.optional.arm.FEAT_SME");
403 if (has_feat_sme != 0) {
404 cpuinfo_isa.sme = true;
405 }
406
407 const uint32_t has_feat_sme2 = get_sys_info_by_name("hw.optional.arm.FEAT_SME2");
408 if (has_feat_sme2 != 0) {
409 cpuinfo_isa.sme2 = true;
410 }
411
412 uint32_t num_clusters = 1;
413 for (uint32_t i = 0; i < mach_topology.cores; i++) {
414 cores[i] = (struct cpuinfo_core){
415 .processor_start = i * threads_per_core,
416 .processor_count = threads_per_core,
417 .core_id = i % cores_per_package,
418 .package = packages + i / cores_per_package,
419 .vendor = cpuinfo_vendor_apple,
420 .uarch = decode_uarch(cpu_family, i, mach_topology.cores),
421 };
422 if (i != 0 && cores[i].uarch != cores[i - 1].uarch) {
423 num_clusters++;
424 }
425 }
426 for (uint32_t i = 0; i < mach_topology.threads; i++) {
427 const uint32_t smt_id = i % threads_per_core;
428 const uint32_t core_id = i / threads_per_core;
429 const uint32_t package_id = i / threads_per_package;
430
431 processors[i].smt_id = smt_id;
432 processors[i].core = &cores[core_id];
433 processors[i].package = &packages[package_id];
434 }
435
436 clusters = calloc(num_clusters, sizeof(struct cpuinfo_cluster));
437 if (clusters == NULL) {
438 cpuinfo_log_error(
439 "failed to allocate %zu bytes for descriptions of %" PRIu32 " clusters",
440 num_clusters * sizeof(struct cpuinfo_cluster),
441 num_clusters);
442 goto cleanup;
443 }
444 uarchs = calloc(num_clusters, sizeof(struct cpuinfo_uarch_info));
445 if (uarchs == NULL) {
446 cpuinfo_log_error(
447 "failed to allocate %zu bytes for descriptions of %" PRIu32 " uarchs",
448 num_clusters * sizeof(enum cpuinfo_uarch),
449 num_clusters);
450 goto cleanup;
451 }
452 uint32_t cluster_idx = UINT32_MAX;
453 for (uint32_t i = 0; i < mach_topology.cores; i++) {
454 if (i == 0 || cores[i].uarch != cores[i - 1].uarch) {
455 cluster_idx++;
456 uarchs[cluster_idx] = (struct cpuinfo_uarch_info){
457 .uarch = cores[i].uarch,
458 .processor_count = 1,
459 .core_count = 1,
460 };
461 clusters[cluster_idx] = (struct cpuinfo_cluster){
462 .processor_start = i * threads_per_core,
463 .processor_count = 1,
464 .core_start = i,
465 .core_count = 1,
466 .cluster_id = cluster_idx,
467 .package = cores[i].package,
468 .vendor = cores[i].vendor,
469 .uarch = cores[i].uarch,
470 };
471 } else {
472 uarchs[cluster_idx].processor_count++;
473 uarchs[cluster_idx].core_count++;
474 clusters[cluster_idx].processor_count++;
475 clusters[cluster_idx].core_count++;
476 }
477 cores[i].cluster = &clusters[cluster_idx];
478 }
479
480 for (uint32_t i = 0; i < mach_topology.threads; i++) {
481 const uint32_t core_id = i / threads_per_core;
482 processors[i].cluster = cores[core_id].cluster;
483 }
484
485 for (uint32_t i = 0; i < mach_topology.packages; i++) {
486 packages[i].cluster_start = 0;
487 packages[i].cluster_count = num_clusters;
488 }
489
490 const uint32_t cacheline_size = get_sys_info(HW_CACHELINE, "HW_CACHELINE");
491 const uint32_t l1d_cache_size = get_sys_info(HW_L1DCACHESIZE, "HW_L1DCACHESIZE");
492 const uint32_t l1i_cache_size = get_sys_info(HW_L1ICACHESIZE, "HW_L1ICACHESIZE");
493 const uint32_t l2_cache_size = get_sys_info(HW_L2CACHESIZE, "HW_L2CACHESIZE");
494 const uint32_t l3_cache_size = get_sys_info(HW_L3CACHESIZE, "HW_L3CACHESIZE");
495 const uint32_t l1_cache_associativity = 4;
496 const uint32_t l2_cache_associativity = 8;
497 const uint32_t l3_cache_associativity = 16;
498 const uint32_t cache_partitions = 1;
499 const uint32_t cache_flags = 0;
500
501 uint32_t threads_per_l1 = 0, l1_count = 0;
502 if (l1i_cache_size != 0 || l1d_cache_size != 0) {
503 /* Assume L1 caches are private to each core */
504 threads_per_l1 = 1;
505 l1_count = mach_topology.threads / threads_per_l1;
506 cpuinfo_log_debug("detected %" PRIu32 " L1 caches", l1_count);
507 }
508
509 uint32_t threads_per_l2 = 0, l2_count = 0;
510 if (l2_cache_size != 0) {
511 /* Assume L2 cache is shared between all cores */
512 threads_per_l2 = mach_topology.cores;
513 l2_count = 1;
514 cpuinfo_log_debug("detected %" PRIu32 " L2 caches", l2_count);
515 }
516
517 uint32_t threads_per_l3 = 0, l3_count = 0;
518 if (l3_cache_size != 0) {
519 /* Assume L3 cache is shared between all cores */
520 threads_per_l3 = mach_topology.cores;
521 l3_count = 1;
522 cpuinfo_log_debug("detected %" PRIu32 " L3 caches", l3_count);
523 }
524
525 if (l1i_cache_size != 0) {
526 l1i = calloc(l1_count, sizeof(struct cpuinfo_cache));
527 if (l1i == NULL) {
528 cpuinfo_log_error(
529 "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1I caches",
530 l1_count * sizeof(struct cpuinfo_cache),
531 l1_count);
532 goto cleanup;
533 }
534 for (uint32_t c = 0; c < l1_count; c++) {
535 l1i[c] = (struct cpuinfo_cache){
536 .size = l1i_cache_size,
537 .associativity = l1_cache_associativity,
538 .sets = l1i_cache_size / (l1_cache_associativity * cacheline_size),
539 .partitions = cache_partitions,
540 .line_size = cacheline_size,
541 .flags = cache_flags,
542 .processor_start = c * threads_per_l1,
543 .processor_count = threads_per_l1,
544 };
545 }
546 for (uint32_t t = 0; t < mach_topology.threads; t++) {
547 processors[t].cache.l1i = &l1i[t / threads_per_l1];
548 }
549 }
550
551 if (l1d_cache_size != 0) {
552 l1d = calloc(l1_count, sizeof(struct cpuinfo_cache));
553 if (l1d == NULL) {
554 cpuinfo_log_error(
555 "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1D caches",
556 l1_count * sizeof(struct cpuinfo_cache),
557 l1_count);
558 goto cleanup;
559 }
560 for (uint32_t c = 0; c < l1_count; c++) {
561 l1d[c] = (struct cpuinfo_cache){
562 .size = l1d_cache_size,
563 .associativity = l1_cache_associativity,
564 .sets = l1d_cache_size / (l1_cache_associativity * cacheline_size),
565 .partitions = cache_partitions,
566 .line_size = cacheline_size,
567 .flags = cache_flags,
568 .processor_start = c * threads_per_l1,
569 .processor_count = threads_per_l1,
570 };
571 }
572 for (uint32_t t = 0; t < mach_topology.threads; t++) {
573 processors[t].cache.l1d = &l1d[t / threads_per_l1];
574 }
575 }
576
577 if (l2_count != 0) {
578 l2 = calloc(l2_count, sizeof(struct cpuinfo_cache));
579 if (l2 == NULL) {
580 cpuinfo_log_error(
581 "failed to allocate %zu bytes for descriptions of %" PRIu32 " L2 caches",
582 l2_count * sizeof(struct cpuinfo_cache),
583 l2_count);
584 goto cleanup;
585 }
586 for (uint32_t c = 0; c < l2_count; c++) {
587 l2[c] = (struct cpuinfo_cache){
588 .size = l2_cache_size,
589 .associativity = l2_cache_associativity,
590 .sets = l2_cache_size / (l2_cache_associativity * cacheline_size),
591 .partitions = cache_partitions,
592 .line_size = cacheline_size,
593 .flags = cache_flags,
594 .processor_start = c * threads_per_l2,
595 .processor_count = threads_per_l2,
596 };
597 }
598 for (uint32_t t = 0; t < mach_topology.threads; t++) {
599 processors[t].cache.l2 = &l2[0];
600 }
601 }
602
603 if (l3_count != 0) {
604 l3 = calloc(l3_count, sizeof(struct cpuinfo_cache));
605 if (l3 == NULL) {
606 cpuinfo_log_error(
607 "failed to allocate %zu bytes for descriptions of %" PRIu32 " L3 caches",
608 l3_count * sizeof(struct cpuinfo_cache),
609 l3_count);
610 goto cleanup;
611 }
612 for (uint32_t c = 0; c < l3_count; c++) {
613 l3[c] = (struct cpuinfo_cache){
614 .size = l3_cache_size,
615 .associativity = l3_cache_associativity,
616 .sets = l3_cache_size / (l3_cache_associativity * cacheline_size),
617 .partitions = cache_partitions,
618 .line_size = cacheline_size,
619 .flags = cache_flags,
620 .processor_start = c * threads_per_l3,
621 .processor_count = threads_per_l3,
622 };
623 }
624 for (uint32_t t = 0; t < mach_topology.threads; t++) {
625 processors[t].cache.l3 = &l3[0];
626 }
627 }
628
629 /* Commit changes */
630 cpuinfo_processors = processors;
631 cpuinfo_cores = cores;
632 cpuinfo_clusters = clusters;
633 cpuinfo_packages = packages;
634 cpuinfo_uarchs = uarchs;
635 cpuinfo_cache[cpuinfo_cache_level_1i] = l1i;
636 cpuinfo_cache[cpuinfo_cache_level_1d] = l1d;
637 cpuinfo_cache[cpuinfo_cache_level_2] = l2;
638 cpuinfo_cache[cpuinfo_cache_level_3] = l3;
639
640 cpuinfo_processors_count = mach_topology.threads;
641 cpuinfo_cores_count = mach_topology.cores;
642 cpuinfo_clusters_count = num_clusters;
643 cpuinfo_packages_count = mach_topology.packages;
644 cpuinfo_uarchs_count = num_clusters;
645 cpuinfo_cache_count[cpuinfo_cache_level_1i] = l1_count;
646 cpuinfo_cache_count[cpuinfo_cache_level_1d] = l1_count;
647 cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count;
648 cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count;
649 cpuinfo_max_cache_size = cpuinfo_compute_max_cache_size(&processors[0]);
650
651 __sync_synchronize();
652
653 cpuinfo_is_initialized = true;
654
655 processors = NULL;
656 cores = NULL;
657 clusters = NULL;
658 packages = NULL;
659 uarchs = NULL;
660 l1i = l1d = l2 = l3 = NULL;
661
662 cleanup:
663 free(processors);
664 free(cores);
665 free(clusters);
666 free(packages);
667 free(uarchs);
668 free(l1i);
669 free(l1d);
670 free(l2);
671 free(l3);
672 }
673