1 #include <gtest/gtest.h>
2
3 #include <cpuinfo-mock.h>
4 #include <cpuinfo.h>
5
TEST(PROCESSORS,count)6 TEST(PROCESSORS, count) {
7 ASSERT_EQ(8, cpuinfo_get_processors_count());
8 }
9
TEST(PROCESSORS,non_null)10 TEST(PROCESSORS, non_null) {
11 ASSERT_TRUE(cpuinfo_get_processors());
12 }
13
TEST(PROCESSORS,smt_id)14 TEST(PROCESSORS, smt_id) {
15 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
16 ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id);
17 }
18 }
19
TEST(PROCESSORS,core)20 TEST(PROCESSORS, core) {
21 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
22 ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core);
23 }
24 }
25
TEST(PROCESSORS,cluster)26 TEST(PROCESSORS, cluster) {
27 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
28 switch (i) {
29 case 0:
30 case 1:
31 case 2:
32 case 3:
33 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_processor(i)->cluster);
34 break;
35 case 4:
36 case 5:
37 case 6:
38 case 7:
39 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_processor(i)->cluster);
40 break;
41 }
42 }
43 }
44
TEST(PROCESSORS,package)45 TEST(PROCESSORS, package) {
46 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
47 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package);
48 }
49 }
50
TEST(PROCESSORS,linux_id)51 TEST(PROCESSORS, linux_id) {
52 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
53 switch (i) {
54 case 0:
55 case 1:
56 case 2:
57 case 3:
58 ASSERT_EQ(i + 4, cpuinfo_get_processor(i)->linux_id);
59 break;
60 case 4:
61 case 5:
62 case 6:
63 case 7:
64 ASSERT_EQ(i - 4, cpuinfo_get_processor(i)->linux_id);
65 break;
66 }
67 }
68 }
69
TEST(PROCESSORS,l1i)70 TEST(PROCESSORS, l1i) {
71 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
72 ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i);
73 }
74 }
75
TEST(PROCESSORS,l1d)76 TEST(PROCESSORS, l1d) {
77 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
78 ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d);
79 }
80 }
81
TEST(PROCESSORS,l2)82 TEST(PROCESSORS, l2) {
83 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
84 switch (i) {
85 case 0:
86 case 1:
87 case 2:
88 case 3:
89 ASSERT_EQ(cpuinfo_get_l2_cache(0), cpuinfo_get_processor(i)->cache.l2);
90 break;
91 case 4:
92 case 5:
93 case 6:
94 case 7:
95 ASSERT_EQ(cpuinfo_get_l2_cache(1), cpuinfo_get_processor(i)->cache.l2);
96 break;
97 }
98 }
99 }
100
TEST(PROCESSORS,l3)101 TEST(PROCESSORS, l3) {
102 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
103 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l3);
104 }
105 }
106
TEST(PROCESSORS,l4)107 TEST(PROCESSORS, l4) {
108 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
109 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4);
110 }
111 }
112
TEST(CORES,count)113 TEST(CORES, count) {
114 ASSERT_EQ(8, cpuinfo_get_cores_count());
115 }
116
TEST(CORES,non_null)117 TEST(CORES, non_null) {
118 ASSERT_TRUE(cpuinfo_get_cores());
119 }
120
TEST(CORES,processor_start)121 TEST(CORES, processor_start) {
122 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
123 ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start);
124 }
125 }
126
TEST(CORES,processor_count)127 TEST(CORES, processor_count) {
128 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
129 ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count);
130 }
131 }
132
TEST(CORES,core_id)133 TEST(CORES, core_id) {
134 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
135 ASSERT_EQ(i, cpuinfo_get_core(i)->core_id);
136 }
137 }
138
TEST(CORES,cluster)139 TEST(CORES, cluster) {
140 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
141 switch (i) {
142 case 0:
143 case 1:
144 case 2:
145 case 3:
146 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_core(i)->cluster);
147 break;
148 case 4:
149 case 5:
150 case 6:
151 case 7:
152 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_core(i)->cluster);
153 break;
154 }
155 }
156 }
157
TEST(CORES,package)158 TEST(CORES, package) {
159 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
160 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package);
161 }
162 }
163
TEST(CORES,vendor)164 TEST(CORES, vendor) {
165 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
166 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_core(i)->vendor);
167 }
168 }
169
TEST(CORES,uarch)170 TEST(CORES, uarch) {
171 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
172 switch (i) {
173 case 0:
174 case 1:
175 case 2:
176 case 3:
177 ASSERT_EQ(cpuinfo_uarch_cortex_a73, cpuinfo_get_core(i)->uarch);
178 break;
179 case 4:
180 case 5:
181 case 6:
182 case 7:
183 ASSERT_EQ(cpuinfo_uarch_cortex_a53, cpuinfo_get_core(i)->uarch);
184 break;
185 }
186 }
187 }
188
TEST(CORES,midr)189 TEST(CORES, midr) {
190 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
191 switch (i) {
192 case 0:
193 case 1:
194 case 2:
195 case 3:
196 ASSERT_EQ(UINT32_C(0x410FD092), cpuinfo_get_core(i)->midr);
197 break;
198 case 4:
199 case 5:
200 case 6:
201 case 7:
202 ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_core(i)->midr);
203 break;
204 }
205 }
206 }
207
TEST(CORES,DISABLED_frequency)208 TEST(CORES, DISABLED_frequency) {
209 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
210 switch (i) {
211 case 0:
212 case 1:
213 case 2:
214 case 3:
215 ASSERT_EQ(UINT64_C(2362000000), cpuinfo_get_core(i)->frequency);
216 break;
217 case 4:
218 case 5:
219 case 6:
220 case 7:
221 ASSERT_EQ(UINT64_C(1844000000), cpuinfo_get_core(i)->frequency);
222 break;
223 }
224 }
225 }
226
TEST(CLUSTERS,count)227 TEST(CLUSTERS, count) {
228 ASSERT_EQ(2, cpuinfo_get_clusters_count());
229 }
230
TEST(CLUSTERS,non_null)231 TEST(CLUSTERS, non_null) {
232 ASSERT_TRUE(cpuinfo_get_clusters());
233 }
234
TEST(CLUSTERS,processor_start)235 TEST(CLUSTERS, processor_start) {
236 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
237 switch (i) {
238 case 0:
239 ASSERT_EQ(0, cpuinfo_get_cluster(i)->processor_start);
240 break;
241 case 1:
242 ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_start);
243 break;
244 }
245 }
246 }
247
TEST(CLUSTERS,processor_count)248 TEST(CLUSTERS, processor_count) {
249 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
250 ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_count);
251 }
252 }
253
TEST(CLUSTERS,core_start)254 TEST(CLUSTERS, core_start) {
255 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
256 switch (i) {
257 case 0:
258 ASSERT_EQ(0, cpuinfo_get_cluster(i)->core_start);
259 break;
260 case 1:
261 ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_start);
262 break;
263 }
264 }
265 }
266
TEST(CLUSTERS,core_count)267 TEST(CLUSTERS, core_count) {
268 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
269 ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_count);
270 }
271 }
272
TEST(CLUSTERS,cluster_id)273 TEST(CLUSTERS, cluster_id) {
274 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
275 ASSERT_EQ(i, cpuinfo_get_cluster(i)->cluster_id);
276 }
277 }
278
TEST(CLUSTERS,package)279 TEST(CLUSTERS, package) {
280 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
281 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_cluster(i)->package);
282 }
283 }
284
TEST(CLUSTERS,vendor)285 TEST(CLUSTERS, vendor) {
286 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
287 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_cluster(i)->vendor);
288 }
289 }
290
TEST(CLUSTERS,uarch)291 TEST(CLUSTERS, uarch) {
292 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
293 switch (i) {
294 case 0:
295 ASSERT_EQ(cpuinfo_uarch_cortex_a73, cpuinfo_get_cluster(i)->uarch);
296 break;
297 case 1:
298 ASSERT_EQ(cpuinfo_uarch_cortex_a53, cpuinfo_get_cluster(i)->uarch);
299 break;
300 }
301 }
302 }
303
TEST(CLUSTERS,midr)304 TEST(CLUSTERS, midr) {
305 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
306 switch (i) {
307 case 0:
308 ASSERT_EQ(UINT32_C(0x410FD092), cpuinfo_get_cluster(i)->midr);
309 break;
310 case 1:
311 ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_cluster(i)->midr);
312 break;
313 }
314 }
315 }
316
TEST(CLUSTERS,DISABLED_frequency)317 TEST(CLUSTERS, DISABLED_frequency) {
318 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
319 switch (i) {
320 case 0:
321 ASSERT_EQ(UINT64_C(2362000000), cpuinfo_get_cluster(i)->frequency);
322 break;
323 case 1:
324 ASSERT_EQ(UINT64_C(1844000000), cpuinfo_get_cluster(i)->frequency);
325 break;
326 }
327 }
328 }
329
TEST(PACKAGES,count)330 TEST(PACKAGES, count) {
331 ASSERT_EQ(1, cpuinfo_get_packages_count());
332 }
333
TEST(PACKAGES,name)334 TEST(PACKAGES, name) {
335 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
336 ASSERT_EQ(
337 "HiSilicon Kirin 970",
338 std::string(
339 cpuinfo_get_package(i)->name,
340 strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX)));
341 }
342 }
343
TEST(PACKAGES,processor_start)344 TEST(PACKAGES, processor_start) {
345 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
346 ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start);
347 }
348 }
349
TEST(PACKAGES,processor_count)350 TEST(PACKAGES, processor_count) {
351 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
352 ASSERT_EQ(8, cpuinfo_get_package(i)->processor_count);
353 }
354 }
355
TEST(PACKAGES,core_start)356 TEST(PACKAGES, core_start) {
357 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
358 ASSERT_EQ(0, cpuinfo_get_package(i)->core_start);
359 }
360 }
361
TEST(PACKAGES,core_count)362 TEST(PACKAGES, core_count) {
363 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
364 ASSERT_EQ(8, cpuinfo_get_package(i)->core_count);
365 }
366 }
367
TEST(PACKAGES,cluster_start)368 TEST(PACKAGES, cluster_start) {
369 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
370 ASSERT_EQ(0, cpuinfo_get_package(i)->cluster_start);
371 }
372 }
373
TEST(PACKAGES,cluster_count)374 TEST(PACKAGES, cluster_count) {
375 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
376 ASSERT_EQ(2, cpuinfo_get_package(i)->cluster_count);
377 }
378 }
379
TEST(ISA,thumb)380 TEST(ISA, thumb) {
381 #if CPUINFO_ARCH_ARM
382 ASSERT_TRUE(cpuinfo_has_arm_thumb());
383 #elif CPUINFO_ARCH_ARM64
384 ASSERT_FALSE(cpuinfo_has_arm_thumb());
385 #endif
386 }
387
TEST(ISA,thumb2)388 TEST(ISA, thumb2) {
389 #if CPUINFO_ARCH_ARM
390 ASSERT_TRUE(cpuinfo_has_arm_thumb2());
391 #elif CPUINFO_ARCH_ARM64
392 ASSERT_FALSE(cpuinfo_has_arm_thumb2());
393 #endif
394 }
395
TEST(ISA,armv5e)396 TEST(ISA, armv5e) {
397 #if CPUINFO_ARCH_ARM
398 ASSERT_TRUE(cpuinfo_has_arm_v5e());
399 #elif CPUINFO_ARCH_ARM64
400 ASSERT_FALSE(cpuinfo_has_arm_v5e());
401 #endif
402 }
403
TEST(ISA,armv6)404 TEST(ISA, armv6) {
405 #if CPUINFO_ARCH_ARM
406 ASSERT_TRUE(cpuinfo_has_arm_v6());
407 #elif CPUINFO_ARCH_ARM64
408 ASSERT_FALSE(cpuinfo_has_arm_v6());
409 #endif
410 }
411
TEST(ISA,armv6k)412 TEST(ISA, armv6k) {
413 #if CPUINFO_ARCH_ARM
414 ASSERT_TRUE(cpuinfo_has_arm_v6k());
415 #elif CPUINFO_ARCH_ARM64
416 ASSERT_FALSE(cpuinfo_has_arm_v6k());
417 #endif
418 }
419
TEST(ISA,armv7)420 TEST(ISA, armv7) {
421 #if CPUINFO_ARCH_ARM
422 ASSERT_TRUE(cpuinfo_has_arm_v7());
423 #elif CPUINFO_ARCH_ARM64
424 ASSERT_FALSE(cpuinfo_has_arm_v7());
425 #endif
426 }
427
TEST(ISA,armv7mp)428 TEST(ISA, armv7mp) {
429 #if CPUINFO_ARCH_ARM
430 ASSERT_TRUE(cpuinfo_has_arm_v7mp());
431 #elif CPUINFO_ARCH_ARM64
432 ASSERT_FALSE(cpuinfo_has_arm_v7mp());
433 #endif
434 }
435
TEST(ISA,idiv)436 TEST(ISA, idiv) {
437 ASSERT_TRUE(cpuinfo_has_arm_idiv());
438 }
439
TEST(ISA,vfpv2)440 TEST(ISA, vfpv2) {
441 ASSERT_FALSE(cpuinfo_has_arm_vfpv2());
442 }
443
TEST(ISA,vfpv3)444 TEST(ISA, vfpv3) {
445 ASSERT_TRUE(cpuinfo_has_arm_vfpv3());
446 }
447
TEST(ISA,vfpv3_d32)448 TEST(ISA, vfpv3_d32) {
449 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32());
450 }
451
TEST(ISA,vfpv3_fp16)452 TEST(ISA, vfpv3_fp16) {
453 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16());
454 }
455
TEST(ISA,vfpv3_fp16_d32)456 TEST(ISA, vfpv3_fp16_d32) {
457 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32());
458 }
459
TEST(ISA,vfpv4)460 TEST(ISA, vfpv4) {
461 ASSERT_TRUE(cpuinfo_has_arm_vfpv4());
462 }
463
TEST(ISA,vfpv4_d32)464 TEST(ISA, vfpv4_d32) {
465 ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32());
466 }
467
TEST(ISA,wmmx)468 TEST(ISA, wmmx) {
469 ASSERT_FALSE(cpuinfo_has_arm_wmmx());
470 }
471
TEST(ISA,wmmx2)472 TEST(ISA, wmmx2) {
473 ASSERT_FALSE(cpuinfo_has_arm_wmmx2());
474 }
475
TEST(ISA,neon)476 TEST(ISA, neon) {
477 ASSERT_TRUE(cpuinfo_has_arm_neon());
478 }
479
TEST(ISA,neon_fp16)480 TEST(ISA, neon_fp16) {
481 ASSERT_TRUE(cpuinfo_has_arm_neon_fp16());
482 }
483
TEST(ISA,neon_fma)484 TEST(ISA, neon_fma) {
485 ASSERT_TRUE(cpuinfo_has_arm_neon_fma());
486 }
487
TEST(ISA,atomics)488 TEST(ISA, atomics) {
489 ASSERT_FALSE(cpuinfo_has_arm_atomics());
490 }
491
TEST(ISA,neon_rdm)492 TEST(ISA, neon_rdm) {
493 ASSERT_FALSE(cpuinfo_has_arm_neon_rdm());
494 }
495
TEST(ISA,fp16_arith)496 TEST(ISA, fp16_arith) {
497 ASSERT_FALSE(cpuinfo_has_arm_fp16_arith());
498 }
499
TEST(ISA,neon_fp16_arith)500 TEST(ISA, neon_fp16_arith) {
501 ASSERT_FALSE(cpuinfo_has_arm_neon_fp16_arith());
502 }
503
TEST(ISA,neon_dot)504 TEST(ISA, neon_dot) {
505 ASSERT_FALSE(cpuinfo_has_arm_neon_dot());
506 }
507
TEST(ISA,jscvt)508 TEST(ISA, jscvt) {
509 ASSERT_FALSE(cpuinfo_has_arm_jscvt());
510 }
511
TEST(ISA,fcma)512 TEST(ISA, fcma) {
513 ASSERT_FALSE(cpuinfo_has_arm_fcma());
514 }
515
TEST(ISA,aes)516 TEST(ISA, aes) {
517 ASSERT_TRUE(cpuinfo_has_arm_aes());
518 }
519
TEST(ISA,sha1)520 TEST(ISA, sha1) {
521 ASSERT_TRUE(cpuinfo_has_arm_sha1());
522 }
523
TEST(ISA,sha2)524 TEST(ISA, sha2) {
525 ASSERT_TRUE(cpuinfo_has_arm_sha2());
526 }
527
TEST(ISA,pmull)528 TEST(ISA, pmull) {
529 ASSERT_TRUE(cpuinfo_has_arm_pmull());
530 }
531
TEST(ISA,crc32)532 TEST(ISA, crc32) {
533 ASSERT_TRUE(cpuinfo_has_arm_crc32());
534 }
535
TEST(L1I,count)536 TEST(L1I, count) {
537 ASSERT_EQ(8, cpuinfo_get_l1i_caches_count());
538 }
539
TEST(L1I,non_null)540 TEST(L1I, non_null) {
541 ASSERT_TRUE(cpuinfo_get_l1i_caches());
542 }
543
TEST(L1I,size)544 TEST(L1I, size) {
545 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
546 switch (i) {
547 case 0:
548 case 1:
549 case 2:
550 case 3:
551 ASSERT_EQ(64 * 1024, cpuinfo_get_l1i_cache(i)->size);
552 break;
553 case 4:
554 case 5:
555 case 6:
556 case 7:
557 ASSERT_EQ(32 * 1024, cpuinfo_get_l1i_cache(i)->size);
558 break;
559 }
560 }
561 }
562
TEST(L1I,associativity)563 TEST(L1I, associativity) {
564 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
565 switch (i) {
566 case 0:
567 case 1:
568 case 2:
569 case 3:
570 ASSERT_EQ(4, cpuinfo_get_l1i_cache(i)->associativity);
571 break;
572 case 4:
573 case 5:
574 case 6:
575 case 7:
576 ASSERT_EQ(2, cpuinfo_get_l1i_cache(i)->associativity);
577 break;
578 }
579 }
580 }
581
TEST(L1I,sets)582 TEST(L1I, sets) {
583 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
584 ASSERT_EQ(
585 cpuinfo_get_l1i_cache(i)->size,
586 cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size *
587 cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity);
588 }
589 }
590
TEST(L1I,partitions)591 TEST(L1I, partitions) {
592 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
593 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions);
594 }
595 }
596
TEST(L1I,line_size)597 TEST(L1I, line_size) {
598 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
599 ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size);
600 }
601 }
602
TEST(L1I,flags)603 TEST(L1I, flags) {
604 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
605 ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags);
606 }
607 }
608
TEST(L1I,processors)609 TEST(L1I, processors) {
610 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
611 ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start);
612 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count);
613 }
614 }
615
TEST(L1D,count)616 TEST(L1D, count) {
617 ASSERT_EQ(8, cpuinfo_get_l1d_caches_count());
618 }
619
TEST(L1D,non_null)620 TEST(L1D, non_null) {
621 ASSERT_TRUE(cpuinfo_get_l1d_caches());
622 }
623
TEST(L1D,size)624 TEST(L1D, size) {
625 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
626 switch (i) {
627 case 0:
628 case 1:
629 case 2:
630 case 3:
631 ASSERT_EQ(64 * 1024, cpuinfo_get_l1d_cache(i)->size);
632 break;
633 case 4:
634 case 5:
635 case 6:
636 case 7:
637 ASSERT_EQ(32 * 1024, cpuinfo_get_l1d_cache(i)->size);
638 break;
639 }
640 }
641 }
642
TEST(L1D,associativity)643 TEST(L1D, associativity) {
644 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
645 switch (i) {
646 case 0:
647 case 1:
648 case 2:
649 case 3:
650 ASSERT_EQ(16, cpuinfo_get_l1d_cache(i)->associativity);
651 break;
652 case 4:
653 case 5:
654 case 6:
655 case 7:
656 ASSERT_EQ(4, cpuinfo_get_l1d_cache(i)->associativity);
657 break;
658 }
659 }
660 }
661
TEST(L1D,sets)662 TEST(L1D, sets) {
663 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
664 ASSERT_EQ(
665 cpuinfo_get_l1d_cache(i)->size,
666 cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size *
667 cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity);
668 }
669 }
670
TEST(L1D,partitions)671 TEST(L1D, partitions) {
672 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
673 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions);
674 }
675 }
676
TEST(L1D,line_size)677 TEST(L1D, line_size) {
678 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
679 ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size);
680 }
681 }
682
TEST(L1D,flags)683 TEST(L1D, flags) {
684 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
685 ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags);
686 }
687 }
688
TEST(L1D,processors)689 TEST(L1D, processors) {
690 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
691 ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start);
692 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count);
693 }
694 }
695
TEST(L2,count)696 TEST(L2, count) {
697 ASSERT_EQ(2, cpuinfo_get_l2_caches_count());
698 }
699
TEST(L2,non_null)700 TEST(L2, non_null) {
701 ASSERT_TRUE(cpuinfo_get_l2_caches());
702 }
703
TEST(L2,size)704 TEST(L2, size) {
705 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
706 switch (i) {
707 case 0:
708 ASSERT_EQ(2 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size);
709 break;
710 case 1:
711 ASSERT_EQ(1024 * 1024, cpuinfo_get_l2_cache(i)->size);
712 break;
713 }
714 }
715 }
716
TEST(L2,associativity)717 TEST(L2, associativity) {
718 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
719 ASSERT_EQ(16, cpuinfo_get_l2_cache(i)->associativity);
720 }
721 }
722
TEST(L2,sets)723 TEST(L2, sets) {
724 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
725 ASSERT_EQ(
726 cpuinfo_get_l2_cache(i)->size,
727 cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size *
728 cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity);
729 }
730 }
731
TEST(L2,partitions)732 TEST(L2, partitions) {
733 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
734 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions);
735 }
736 }
737
TEST(L2,line_size)738 TEST(L2, line_size) {
739 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
740 ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size);
741 }
742 }
743
TEST(L2,flags)744 TEST(L2, flags) {
745 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
746 switch (i) {
747 case 0:
748 ASSERT_EQ(CPUINFO_CACHE_INCLUSIVE, cpuinfo_get_l2_cache(i)->flags);
749 break;
750 case 1:
751 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags);
752 break;
753 }
754 }
755 }
756
TEST(L2,processors)757 TEST(L2, processors) {
758 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
759 switch (i) {
760 case 0:
761 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->processor_start);
762 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count);
763 break;
764 case 1:
765 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_start);
766 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count);
767 break;
768 }
769 }
770 }
771
TEST(L3,none)772 TEST(L3, none) {
773 ASSERT_EQ(0, cpuinfo_get_l3_caches_count());
774 ASSERT_FALSE(cpuinfo_get_l3_caches());
775 }
776
TEST(L4,none)777 TEST(L4, none) {
778 ASSERT_EQ(0, cpuinfo_get_l4_caches_count());
779 ASSERT_FALSE(cpuinfo_get_l4_caches());
780 }
781
782 #include <huawei-mate-10.h>
783
main(int argc,char * argv[])784 int main(int argc, char* argv[]) {
785 #if CPUINFO_ARCH_ARM
786 cpuinfo_set_hwcap(UINT32_C(0x0037B0D6));
787 cpuinfo_set_hwcap2(UINT32_C(0x0000001F));
788 #elif CPUINFO_ARCH_ARM64
789 cpuinfo_set_hwcap(UINT32_C(0x000000FF));
790 #endif
791 cpuinfo_mock_filesystem(filesystem);
792 #ifdef __ANDROID__
793 cpuinfo_mock_android_properties(properties);
794 #endif
795 cpuinfo_initialize();
796 ::testing::InitGoogleTest(&argc, argv);
797 return RUN_ALL_TESTS();
798 }
799