1 #include <gtest/gtest.h>
2
3 #include <cpuinfo-mock.h>
4 #include <cpuinfo.h>
5
TEST(PROCESSORS,count)6 TEST(PROCESSORS, count) {
7 ASSERT_EQ(6, cpuinfo_get_processors_count());
8 }
9
TEST(PROCESSORS,non_null)10 TEST(PROCESSORS, non_null) {
11 ASSERT_TRUE(cpuinfo_get_processors());
12 }
13
TEST(PROCESSORS,smt_id)14 TEST(PROCESSORS, smt_id) {
15 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
16 ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id);
17 }
18 }
19
TEST(PROCESSORS,core)20 TEST(PROCESSORS, core) {
21 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
22 ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core);
23 }
24 }
25
TEST(PROCESSORS,cluster)26 TEST(PROCESSORS, cluster) {
27 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
28 switch (i) {
29 case 0:
30 case 1:
31 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_processor(i)->cluster);
32 break;
33 case 2:
34 case 3:
35 case 4:
36 case 5:
37 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_processor(i)->cluster);
38 break;
39 }
40 }
41 }
42
TEST(PROCESSORS,package)43 TEST(PROCESSORS, package) {
44 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
45 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package);
46 }
47 }
48
TEST(PROCESSORS,linux_id)49 TEST(PROCESSORS, linux_id) {
50 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
51 switch (i) {
52 case 0:
53 case 1:
54 ASSERT_EQ(i + 4, cpuinfo_get_processor(i)->linux_id);
55 break;
56 case 2:
57 case 3:
58 case 4:
59 case 5:
60 ASSERT_EQ(i - 2, cpuinfo_get_processor(i)->linux_id);
61 break;
62 }
63 }
64 }
65
TEST(PROCESSORS,l1i)66 TEST(PROCESSORS, l1i) {
67 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
68 ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i);
69 }
70 }
71
TEST(PROCESSORS,l1d)72 TEST(PROCESSORS, l1d) {
73 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
74 ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d);
75 }
76 }
77
TEST(PROCESSORS,l2)78 TEST(PROCESSORS, l2) {
79 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
80 switch (i) {
81 case 0:
82 case 1:
83 ASSERT_EQ(cpuinfo_get_l2_cache(0), cpuinfo_get_processor(i)->cache.l2);
84 break;
85 case 2:
86 case 3:
87 case 4:
88 case 5:
89 ASSERT_EQ(cpuinfo_get_l2_cache(1), cpuinfo_get_processor(i)->cache.l2);
90 break;
91 }
92 }
93 }
94
TEST(PROCESSORS,l3)95 TEST(PROCESSORS, l3) {
96 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
97 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l3);
98 }
99 }
100
TEST(PROCESSORS,l4)101 TEST(PROCESSORS, l4) {
102 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
103 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4);
104 }
105 }
106
TEST(CORES,count)107 TEST(CORES, count) {
108 ASSERT_EQ(6, cpuinfo_get_cores_count());
109 }
110
TEST(CORES,non_null)111 TEST(CORES, non_null) {
112 ASSERT_TRUE(cpuinfo_get_cores());
113 }
114
TEST(CORES,processor_start)115 TEST(CORES, processor_start) {
116 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
117 ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start);
118 }
119 }
120
TEST(CORES,processor_count)121 TEST(CORES, processor_count) {
122 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
123 ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count);
124 }
125 }
126
TEST(CORES,core_id)127 TEST(CORES, core_id) {
128 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
129 ASSERT_EQ(i, cpuinfo_get_core(i)->core_id);
130 }
131 }
132
TEST(CORES,cluster)133 TEST(CORES, cluster) {
134 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
135 switch (i) {
136 case 0:
137 case 1:
138 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_core(i)->cluster);
139 break;
140 case 2:
141 case 3:
142 case 4:
143 case 5:
144 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_core(i)->cluster);
145 break;
146 }
147 }
148 }
149
TEST(CORES,package)150 TEST(CORES, package) {
151 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
152 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package);
153 }
154 }
155
TEST(CORES,vendor)156 TEST(CORES, vendor) {
157 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
158 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_core(i)->vendor);
159 }
160 }
161
TEST(CORES,uarch)162 TEST(CORES, uarch) {
163 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
164 switch (i) {
165 case 0:
166 case 1:
167 ASSERT_EQ(cpuinfo_uarch_cortex_a72, cpuinfo_get_core(i)->uarch);
168 break;
169 case 2:
170 case 3:
171 case 4:
172 case 5:
173 ASSERT_EQ(cpuinfo_uarch_cortex_a53, cpuinfo_get_core(i)->uarch);
174 break;
175 }
176 }
177 }
178
TEST(CORES,midr)179 TEST(CORES, midr) {
180 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
181 switch (i) {
182 case 0:
183 case 1:
184 ASSERT_EQ(UINT32_C(0x410FD080), cpuinfo_get_core(i)->midr);
185 break;
186 case 2:
187 case 3:
188 case 4:
189 case 5:
190 ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_core(i)->midr);
191 break;
192 }
193 }
194 }
195
TEST(CORES,DISABLED_frequency)196 TEST(CORES, DISABLED_frequency) {
197 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
198 switch (i) {
199 case 0:
200 case 1:
201 ASSERT_EQ(UINT64_C(1804800000), cpuinfo_get_core(i)->frequency);
202 break;
203 case 2:
204 case 3:
205 case 4:
206 case 5:
207 ASSERT_EQ(UINT64_C(1401600000), cpuinfo_get_core(i)->frequency);
208 break;
209 }
210 }
211 }
212
TEST(CLUSTERS,count)213 TEST(CLUSTERS, count) {
214 ASSERT_EQ(2, cpuinfo_get_clusters_count());
215 }
216
TEST(CLUSTERS,non_null)217 TEST(CLUSTERS, non_null) {
218 ASSERT_TRUE(cpuinfo_get_clusters());
219 }
220
TEST(CLUSTERS,processor_start)221 TEST(CLUSTERS, processor_start) {
222 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
223 switch (i) {
224 case 0:
225 ASSERT_EQ(0, cpuinfo_get_cluster(i)->processor_start);
226 break;
227 case 1:
228 ASSERT_EQ(2, cpuinfo_get_cluster(i)->processor_start);
229 break;
230 }
231 }
232 }
233
TEST(CLUSTERS,processor_count)234 TEST(CLUSTERS, processor_count) {
235 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
236 switch (i) {
237 case 0:
238 ASSERT_EQ(2, cpuinfo_get_cluster(i)->processor_count);
239 break;
240 case 1:
241 ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_count);
242 break;
243 }
244 }
245 }
246
TEST(CLUSTERS,core_start)247 TEST(CLUSTERS, core_start) {
248 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
249 switch (i) {
250 case 0:
251 ASSERT_EQ(0, cpuinfo_get_cluster(i)->core_start);
252 break;
253 case 1:
254 ASSERT_EQ(2, cpuinfo_get_cluster(i)->core_start);
255 break;
256 }
257 }
258 }
259
TEST(CLUSTERS,core_count)260 TEST(CLUSTERS, core_count) {
261 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
262 switch (i) {
263 case 0:
264 ASSERT_EQ(2, cpuinfo_get_cluster(i)->core_count);
265 break;
266 case 1:
267 ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_count);
268 break;
269 }
270 }
271 }
272
TEST(CLUSTERS,cluster_id)273 TEST(CLUSTERS, cluster_id) {
274 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
275 ASSERT_EQ(i, cpuinfo_get_cluster(i)->cluster_id);
276 }
277 }
278
TEST(CLUSTERS,package)279 TEST(CLUSTERS, package) {
280 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
281 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_cluster(i)->package);
282 }
283 }
284
TEST(CLUSTERS,vendor)285 TEST(CLUSTERS, vendor) {
286 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
287 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_cluster(i)->vendor);
288 }
289 }
290
TEST(CLUSTERS,uarch)291 TEST(CLUSTERS, uarch) {
292 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
293 switch (i) {
294 case 0:
295 ASSERT_EQ(cpuinfo_uarch_cortex_a72, cpuinfo_get_cluster(i)->uarch);
296 break;
297 case 1:
298 ASSERT_EQ(cpuinfo_uarch_cortex_a53, cpuinfo_get_cluster(i)->uarch);
299 break;
300 }
301 }
302 }
303
TEST(CLUSTERS,midr)304 TEST(CLUSTERS, midr) {
305 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
306 switch (i) {
307 case 0:
308 ASSERT_EQ(UINT32_C(0x410FD080), cpuinfo_get_cluster(i)->midr);
309 break;
310 case 1:
311 ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_cluster(i)->midr);
312 break;
313 }
314 }
315 }
316
TEST(CLUSTERS,DISABLED_frequency)317 TEST(CLUSTERS, DISABLED_frequency) {
318 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
319 switch (i) {
320 case 0:
321 ASSERT_EQ(UINT64_C(1804800000), cpuinfo_get_cluster(i)->frequency);
322 break;
323 case 1:
324 ASSERT_EQ(UINT64_C(1401600000), cpuinfo_get_cluster(i)->frequency);
325 break;
326 }
327 }
328 }
329
TEST(PACKAGES,count)330 TEST(PACKAGES, count) {
331 ASSERT_EQ(1, cpuinfo_get_packages_count());
332 }
333
TEST(PACKAGES,name)334 TEST(PACKAGES, name) {
335 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
336 ASSERT_EQ(
337 "Qualcomm MSM8956",
338 std::string(
339 cpuinfo_get_package(i)->name,
340 strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX)));
341 }
342 }
343
TEST(PACKAGES,processor_start)344 TEST(PACKAGES, processor_start) {
345 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
346 ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start);
347 }
348 }
349
TEST(PACKAGES,processor_count)350 TEST(PACKAGES, processor_count) {
351 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
352 ASSERT_EQ(6, cpuinfo_get_package(i)->processor_count);
353 }
354 }
355
TEST(PACKAGES,core_start)356 TEST(PACKAGES, core_start) {
357 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
358 ASSERT_EQ(0, cpuinfo_get_package(i)->core_start);
359 }
360 }
361
TEST(PACKAGES,core_count)362 TEST(PACKAGES, core_count) {
363 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
364 ASSERT_EQ(6, cpuinfo_get_package(i)->core_count);
365 }
366 }
367
TEST(PACKAGES,cluster_start)368 TEST(PACKAGES, cluster_start) {
369 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
370 ASSERT_EQ(0, cpuinfo_get_package(i)->cluster_start);
371 }
372 }
373
TEST(PACKAGES,cluster_count)374 TEST(PACKAGES, cluster_count) {
375 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
376 ASSERT_EQ(2, cpuinfo_get_package(i)->cluster_count);
377 }
378 }
379
TEST(ISA,thumb)380 TEST(ISA, thumb) {
381 #if CPUINFO_ARCH_ARM
382 ASSERT_TRUE(cpuinfo_has_arm_thumb());
383 #elif CPUINFO_ARCH_ARM64
384 ASSERT_FALSE(cpuinfo_has_arm_thumb());
385 #endif
386 }
387
TEST(ISA,thumb2)388 TEST(ISA, thumb2) {
389 #if CPUINFO_ARCH_ARM
390 ASSERT_TRUE(cpuinfo_has_arm_thumb2());
391 #elif CPUINFO_ARCH_ARM64
392 ASSERT_FALSE(cpuinfo_has_arm_thumb2());
393 #endif
394 }
395
TEST(ISA,armv5e)396 TEST(ISA, armv5e) {
397 #if CPUINFO_ARCH_ARM
398 ASSERT_TRUE(cpuinfo_has_arm_v5e());
399 #elif CPUINFO_ARCH_ARM64
400 ASSERT_FALSE(cpuinfo_has_arm_v5e());
401 #endif
402 }
403
TEST(ISA,armv6)404 TEST(ISA, armv6) {
405 #if CPUINFO_ARCH_ARM
406 ASSERT_TRUE(cpuinfo_has_arm_v6());
407 #elif CPUINFO_ARCH_ARM64
408 ASSERT_FALSE(cpuinfo_has_arm_v6());
409 #endif
410 }
411
TEST(ISA,armv6k)412 TEST(ISA, armv6k) {
413 #if CPUINFO_ARCH_ARM
414 ASSERT_TRUE(cpuinfo_has_arm_v6k());
415 #elif CPUINFO_ARCH_ARM64
416 ASSERT_FALSE(cpuinfo_has_arm_v6k());
417 #endif
418 }
419
TEST(ISA,armv7)420 TEST(ISA, armv7) {
421 #if CPUINFO_ARCH_ARM
422 ASSERT_TRUE(cpuinfo_has_arm_v7());
423 #elif CPUINFO_ARCH_ARM64
424 ASSERT_FALSE(cpuinfo_has_arm_v7());
425 #endif
426 }
427
TEST(ISA,armv7mp)428 TEST(ISA, armv7mp) {
429 #if CPUINFO_ARCH_ARM
430 ASSERT_TRUE(cpuinfo_has_arm_v7mp());
431 #elif CPUINFO_ARCH_ARM64
432 ASSERT_FALSE(cpuinfo_has_arm_v7mp());
433 #endif
434 }
435
TEST(ISA,idiv)436 TEST(ISA, idiv) {
437 ASSERT_TRUE(cpuinfo_has_arm_idiv());
438 }
439
TEST(ISA,vfpv2)440 TEST(ISA, vfpv2) {
441 ASSERT_FALSE(cpuinfo_has_arm_vfpv2());
442 }
443
TEST(ISA,vfpv3)444 TEST(ISA, vfpv3) {
445 ASSERT_TRUE(cpuinfo_has_arm_vfpv3());
446 }
447
TEST(ISA,vfpv3_d32)448 TEST(ISA, vfpv3_d32) {
449 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32());
450 }
451
TEST(ISA,vfpv3_fp16)452 TEST(ISA, vfpv3_fp16) {
453 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16());
454 }
455
TEST(ISA,vfpv3_fp16_d32)456 TEST(ISA, vfpv3_fp16_d32) {
457 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32());
458 }
459
TEST(ISA,vfpv4)460 TEST(ISA, vfpv4) {
461 ASSERT_TRUE(cpuinfo_has_arm_vfpv4());
462 }
463
TEST(ISA,vfpv4_d32)464 TEST(ISA, vfpv4_d32) {
465 ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32());
466 }
467
TEST(ISA,wmmx)468 TEST(ISA, wmmx) {
469 ASSERT_FALSE(cpuinfo_has_arm_wmmx());
470 }
471
TEST(ISA,wmmx2)472 TEST(ISA, wmmx2) {
473 ASSERT_FALSE(cpuinfo_has_arm_wmmx2());
474 }
475
TEST(ISA,neon)476 TEST(ISA, neon) {
477 ASSERT_TRUE(cpuinfo_has_arm_neon());
478 }
479
TEST(ISA,neon_fp16)480 TEST(ISA, neon_fp16) {
481 ASSERT_TRUE(cpuinfo_has_arm_neon_fp16());
482 }
483
TEST(ISA,neon_fma)484 TEST(ISA, neon_fma) {
485 ASSERT_TRUE(cpuinfo_has_arm_neon_fma());
486 }
487
TEST(ISA,atomics)488 TEST(ISA, atomics) {
489 ASSERT_FALSE(cpuinfo_has_arm_atomics());
490 }
491
TEST(ISA,neon_rdm)492 TEST(ISA, neon_rdm) {
493 ASSERT_FALSE(cpuinfo_has_arm_neon_rdm());
494 }
495
TEST(ISA,fp16_arith)496 TEST(ISA, fp16_arith) {
497 ASSERT_FALSE(cpuinfo_has_arm_fp16_arith());
498 }
499
TEST(ISA,neon_fp16_arith)500 TEST(ISA, neon_fp16_arith) {
501 ASSERT_FALSE(cpuinfo_has_arm_neon_fp16_arith());
502 }
503
TEST(ISA,neon_dot)504 TEST(ISA, neon_dot) {
505 ASSERT_FALSE(cpuinfo_has_arm_neon_dot());
506 }
507
TEST(ISA,jscvt)508 TEST(ISA, jscvt) {
509 ASSERT_FALSE(cpuinfo_has_arm_jscvt());
510 }
511
TEST(ISA,fcma)512 TEST(ISA, fcma) {
513 ASSERT_FALSE(cpuinfo_has_arm_fcma());
514 }
515
TEST(ISA,aes)516 TEST(ISA, aes) {
517 ASSERT_TRUE(cpuinfo_has_arm_aes());
518 }
519
TEST(ISA,sha1)520 TEST(ISA, sha1) {
521 ASSERT_TRUE(cpuinfo_has_arm_sha1());
522 }
523
TEST(ISA,sha2)524 TEST(ISA, sha2) {
525 ASSERT_TRUE(cpuinfo_has_arm_sha2());
526 }
527
TEST(ISA,pmull)528 TEST(ISA, pmull) {
529 ASSERT_TRUE(cpuinfo_has_arm_pmull());
530 }
531
TEST(ISA,crc32)532 TEST(ISA, crc32) {
533 ASSERT_TRUE(cpuinfo_has_arm_crc32());
534 }
535
TEST(L1I,count)536 TEST(L1I, count) {
537 ASSERT_EQ(6, cpuinfo_get_l1i_caches_count());
538 }
539
TEST(L1I,non_null)540 TEST(L1I, non_null) {
541 ASSERT_TRUE(cpuinfo_get_l1i_caches());
542 }
543
TEST(L1I,size)544 TEST(L1I, size) {
545 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
546 switch (i) {
547 case 0:
548 case 1:
549 ASSERT_EQ(48 * 1024, cpuinfo_get_l1i_cache(i)->size);
550 break;
551 case 2:
552 case 3:
553 case 4:
554 case 5:
555 ASSERT_EQ(32 * 1024, cpuinfo_get_l1i_cache(i)->size);
556 break;
557 }
558 }
559 }
560
TEST(L1I,associativity)561 TEST(L1I, associativity) {
562 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
563 switch (i) {
564 case 0:
565 case 1:
566 ASSERT_EQ(3, cpuinfo_get_l1i_cache(i)->associativity);
567 break;
568 case 2:
569 case 3:
570 case 4:
571 case 5:
572 ASSERT_EQ(2, cpuinfo_get_l1i_cache(i)->associativity);
573 break;
574 }
575 }
576 }
577
TEST(L1I,sets)578 TEST(L1I, sets) {
579 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
580 ASSERT_EQ(
581 cpuinfo_get_l1i_cache(i)->size,
582 cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size *
583 cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity);
584 }
585 }
586
TEST(L1I,partitions)587 TEST(L1I, partitions) {
588 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
589 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions);
590 }
591 }
592
TEST(L1I,line_size)593 TEST(L1I, line_size) {
594 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
595 ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size);
596 }
597 }
598
TEST(L1I,flags)599 TEST(L1I, flags) {
600 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
601 ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags);
602 }
603 }
604
TEST(L1I,processors)605 TEST(L1I, processors) {
606 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
607 ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start);
608 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count);
609 }
610 }
611
TEST(L1D,count)612 TEST(L1D, count) {
613 ASSERT_EQ(6, cpuinfo_get_l1d_caches_count());
614 }
615
TEST(L1D,non_null)616 TEST(L1D, non_null) {
617 ASSERT_TRUE(cpuinfo_get_l1d_caches());
618 }
619
TEST(L1D,size)620 TEST(L1D, size) {
621 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
622 ASSERT_EQ(32 * 1024, cpuinfo_get_l1d_cache(i)->size);
623 }
624 }
625
TEST(L1D,associativity)626 TEST(L1D, associativity) {
627 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
628 switch (i) {
629 case 0:
630 case 1:
631 ASSERT_EQ(2, cpuinfo_get_l1d_cache(i)->associativity);
632 break;
633 case 2:
634 case 3:
635 case 4:
636 case 5:
637 ASSERT_EQ(4, cpuinfo_get_l1d_cache(i)->associativity);
638 break;
639 }
640 }
641 }
642
TEST(L1D,sets)643 TEST(L1D, sets) {
644 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
645 ASSERT_EQ(
646 cpuinfo_get_l1d_cache(i)->size,
647 cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size *
648 cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity);
649 }
650 }
651
TEST(L1D,partitions)652 TEST(L1D, partitions) {
653 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
654 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions);
655 }
656 }
657
TEST(L1D,line_size)658 TEST(L1D, line_size) {
659 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
660 ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size);
661 }
662 }
663
TEST(L1D,flags)664 TEST(L1D, flags) {
665 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
666 ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags);
667 }
668 }
669
TEST(L1D,processors)670 TEST(L1D, processors) {
671 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
672 ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start);
673 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count);
674 }
675 }
676
TEST(L2,count)677 TEST(L2, count) {
678 ASSERT_EQ(2, cpuinfo_get_l2_caches_count());
679 }
680
TEST(L2,non_null)681 TEST(L2, non_null) {
682 ASSERT_TRUE(cpuinfo_get_l2_caches());
683 }
684
TEST(L2,size)685 TEST(L2, size) {
686 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
687 switch (i) {
688 case 0:
689 ASSERT_EQ(1 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size);
690 break;
691 case 1:
692 ASSERT_EQ(512 * 1024, cpuinfo_get_l2_cache(i)->size);
693 break;
694 }
695 }
696 }
697
TEST(L2,associativity)698 TEST(L2, associativity) {
699 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
700 ASSERT_EQ(16, cpuinfo_get_l2_cache(i)->associativity);
701 }
702 }
703
TEST(L2,sets)704 TEST(L2, sets) {
705 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
706 ASSERT_EQ(
707 cpuinfo_get_l2_cache(i)->size,
708 cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size *
709 cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity);
710 }
711 }
712
TEST(L2,partitions)713 TEST(L2, partitions) {
714 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
715 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions);
716 }
717 }
718
TEST(L2,line_size)719 TEST(L2, line_size) {
720 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
721 ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size);
722 }
723 }
724
TEST(L2,flags)725 TEST(L2, flags) {
726 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
727 switch (i) {
728 case 0:
729 ASSERT_EQ(CPUINFO_CACHE_INCLUSIVE, cpuinfo_get_l2_cache(i)->flags);
730 break;
731 case 1:
732 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags);
733 break;
734 }
735 }
736 }
737
TEST(L2,processors)738 TEST(L2, processors) {
739 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
740 switch (i) {
741 case 0:
742 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->processor_start);
743 ASSERT_EQ(2, cpuinfo_get_l2_cache(i)->processor_count);
744 break;
745 case 1:
746 ASSERT_EQ(2, cpuinfo_get_l2_cache(i)->processor_start);
747 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count);
748 break;
749 }
750 }
751 }
752
TEST(L3,none)753 TEST(L3, none) {
754 ASSERT_EQ(0, cpuinfo_get_l3_caches_count());
755 ASSERT_FALSE(cpuinfo_get_l3_caches());
756 }
757
TEST(L4,none)758 TEST(L4, none) {
759 ASSERT_EQ(0, cpuinfo_get_l4_caches_count());
760 ASSERT_FALSE(cpuinfo_get_l4_caches());
761 }
762
763 #include <xiaomi-redmi-note-3.h>
764
main(int argc,char * argv[])765 int main(int argc, char* argv[]) {
766 #if CPUINFO_ARCH_ARM
767 cpuinfo_set_hwcap(UINT32_C(0x0027B0D6));
768 cpuinfo_set_hwcap2(UINT32_C(0x0000001F));
769 #elif CPUINFO_ARCH_ARM64
770 cpuinfo_set_hwcap(UINT32_C(0x000000FF));
771 #endif
772 cpuinfo_mock_filesystem(filesystem);
773 #ifdef __ANDROID__
774 cpuinfo_mock_android_properties(properties);
775 #endif
776 cpuinfo_initialize();
777 ::testing::InitGoogleTest(&argc, argv);
778 return RUN_ALL_TESTS();
779 }
780