1 // Copyright 2012 The Chromium Authors
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 #include "base/cpu.h"
6
7 #include <stdint.h>
8 #include <string.h>
9
10 #include <string>
11 #include <string_view>
12 #include <utility>
13
14 #include "base/containers/span.h"
15 #include "base/containers/span_writer.h"
16 #include "base/memory/protected_memory.h"
17 #include "build/build_config.h"
18
19 #if defined(ARCH_CPU_ARM_FAMILY) && \
20 (BUILDFLAG(IS_ANDROID) || BUILDFLAG(IS_LINUX) || BUILDFLAG(IS_CHROMEOS))
21 #include <asm/hwcap.h>
22 #include <sys/auxv.h>
23
24 #include "base/files/file_util.h"
25 #include "base/numerics/checked_math.h"
26 #include "base/ranges/algorithm.h"
27 #include "base/strings/string_number_conversions.h"
28 #include "base/strings/string_split.h"
29 #include "base/strings/string_util.h"
30
31 // Temporary definitions until a new hwcap.h is pulled in everywhere.
32 // https://crbug.com/1265965
33 #ifndef HWCAP2_MTE
34 #define HWCAP2_MTE (1 << 18)
35 #define HWCAP2_BTI (1 << 17)
36 #endif
37 #endif
38
39 #if defined(ARCH_CPU_X86_FAMILY)
40 #if defined(COMPILER_MSVC)
41 #include <intrin.h>
42 #include <immintrin.h> // For _xgetbv()
43 #endif
44 #endif
45
46 namespace base {
47
48 #if defined(ARCH_CPU_X86_FAMILY)
49 namespace internal {
50
ComputeX86FamilyAndModel(const std::string & vendor,int signature)51 X86ModelInfo ComputeX86FamilyAndModel(const std::string& vendor,
52 int signature) {
53 X86ModelInfo results;
54 results.family = (signature >> 8) & 0xf;
55 results.model = (signature >> 4) & 0xf;
56 results.ext_family = 0;
57 results.ext_model = 0;
58
59 // The "Intel 64 and IA-32 Architectures Developer's Manual: Vol. 2A"
60 // specifies the Extended Model is defined only when the Base Family is
61 // 06h or 0Fh.
62 // The "AMD CPUID Specification" specifies that the Extended Model is
63 // defined only when Base Family is 0Fh.
64 // Both manuals define the display model as
65 // {ExtendedModel[3:0],BaseModel[3:0]} in that case.
66 if (results.family == 0xf ||
67 (results.family == 0x6 && vendor == "GenuineIntel")) {
68 results.ext_model = (signature >> 16) & 0xf;
69 results.model += results.ext_model << 4;
70 }
71 // Both the "Intel 64 and IA-32 Architectures Developer's Manual: Vol. 2A"
72 // and the "AMD CPUID Specification" specify that the Extended Family is
73 // defined only when the Base Family is 0Fh.
74 // Both manuals define the display family as {0000b,BaseFamily[3:0]} +
75 // ExtendedFamily[7:0] in that case.
76 if (results.family == 0xf) {
77 results.ext_family = (signature >> 20) & 0xff;
78 results.family += results.ext_family;
79 }
80
81 return results;
82 }
83
84 } // namespace internal
85 #endif // defined(ARCH_CPU_X86_FAMILY)
86
CPU()87 CPU::CPU() {
88 Initialize();
89 }
90
91 CPU::CPU(CPU&&) = default;
92
93 namespace {
94
95 #if defined(ARCH_CPU_X86_FAMILY)
96 #if !defined(COMPILER_MSVC)
97
98 #if defined(__pic__) && defined(__i386__)
99
100 // Requests extended feature information via |ecx|.
__cpuidex(int cpu_info[4],int eax,int ecx)101 void __cpuidex(int cpu_info[4], int eax, int ecx) {
102 // SAFETY: `cpu_info` has length 4 and therefore all accesses below are valid.
103 UNSAFE_BUFFERS(
104 __asm__ volatile("mov %%ebx, %%edi\n"
105 "cpuid\n"
106 "xchg %%edi, %%ebx\n"
107 : "=a"(cpu_info[0]), "=D"(cpu_info[1]),
108 "=c"(cpu_info[2]), "=d"(cpu_info[3])
109 : "a"(eax), "c"(ecx)));
110 }
111
__cpuid(int cpu_info[4],int info_type)112 void __cpuid(int cpu_info[4], int info_type) {
113 __cpuidex(cpu_info, info_type, /*ecx=*/0);
114 }
115
116 #else
117
118 // Requests extended feature information via |ecx|.
119 void __cpuidex(int cpu_info[4], int eax, int ecx) {
120 // SAFETY: `cpu_info` has length 4 and therefore all accesses below are valid.
121 UNSAFE_BUFFERS(__asm__ volatile("cpuid\n"
122 : "=a"(cpu_info[0]), "=b"(cpu_info[1]),
123 "=c"(cpu_info[2]), "=d"(cpu_info[3])
124 : "a"(eax), "c"(ecx)));
125 }
126
127 void __cpuid(int cpu_info[4], int info_type) {
128 __cpuidex(cpu_info, info_type, /*ecx=*/0);
129 }
130
131 #endif
132 #endif // !defined(COMPILER_MSVC)
133
134 // xgetbv returns the value of an Intel Extended Control Register (XCR).
135 // Currently only XCR0 is defined by Intel so |xcr| should always be zero.
xgetbv(uint32_t xcr)136 uint64_t xgetbv(uint32_t xcr) {
137 #if defined(COMPILER_MSVC)
138 return _xgetbv(xcr);
139 #else
140 uint32_t eax, edx;
141
142 __asm__ volatile (
143 "xgetbv" : "=a"(eax), "=d"(edx) : "c"(xcr));
144 return (static_cast<uint64_t>(edx) << 32) | eax;
145 #endif // defined(COMPILER_MSVC)
146 }
147
148 #endif // ARCH_CPU_X86_FAMILY
149
150 DEFINE_PROTECTED_DATA base::ProtectedMemory<CPU> g_cpu_instance;
151
152 } // namespace
153
Initialize()154 void CPU::Initialize() {
155 #if defined(ARCH_CPU_X86_FAMILY)
156 int cpu_info[4] = {-1};
157
158 // __cpuid with an InfoType argument of 0 returns the number of
159 // valid Ids in CPUInfo[0] and the CPU identification string in
160 // the other three array elements. The CPU identification string is
161 // not in linear order. The code below arranges the information
162 // in a human readable form. The human readable order is CPUInfo[1] |
163 // CPUInfo[3] | CPUInfo[2]. CPUInfo[2] and CPUInfo[3] are swapped
164 // before copying these three array elements to |cpu_vendor_|.
165 __cpuid(cpu_info, 0);
166 int num_ids = cpu_info[0];
167 std::swap(cpu_info[2], cpu_info[3]);
168 {
169 SpanWriter writer{span(cpu_vendor_)};
170 writer.Write(as_chars(span(cpu_info)).last<kVendorNameSize>());
171 writer.Write('\0');
172 }
173
174 // Interpret CPU feature information.
175 if (num_ids > 0) {
176 int cpu_info7[4] = {0};
177 int cpu_einfo7[4] = {0};
178 __cpuid(cpu_info, 1);
179 if (num_ids >= 7) {
180 __cpuid(cpu_info7, 7);
181 if (cpu_info7[0] >= 1) {
182 __cpuidex(cpu_einfo7, 7, 1);
183 }
184 }
185 signature_ = cpu_info[0];
186 stepping_ = cpu_info[0] & 0xf;
187 type_ = (cpu_info[0] >> 12) & 0x3;
188 internal::X86ModelInfo results =
189 internal::ComputeX86FamilyAndModel(cpu_vendor_, signature_);
190 family_ = results.family;
191 model_ = results.model;
192 ext_family_ = results.ext_family;
193 ext_model_ = results.ext_model;
194 has_mmx_ = (cpu_info[3] & 0x00800000) != 0;
195 has_sse_ = (cpu_info[3] & 0x02000000) != 0;
196 has_sse2_ = (cpu_info[3] & 0x04000000) != 0;
197 has_sse3_ = (cpu_info[2] & 0x00000001) != 0;
198 has_ssse3_ = (cpu_info[2] & 0x00000200) != 0;
199 has_sse41_ = (cpu_info[2] & 0x00080000) != 0;
200 has_sse42_ = (cpu_info[2] & 0x00100000) != 0;
201 has_popcnt_ = (cpu_info[2] & 0x00800000) != 0;
202
203 // "Hypervisor Present Bit: Bit 31 of ECX of CPUID leaf 0x1."
204 // See https://lwn.net/Articles/301888/
205 // This is checking for any hypervisor. Hypervisors may choose not to
206 // announce themselves. Hypervisors trap CPUID and sometimes return
207 // different results to underlying hardware.
208 is_running_in_vm_ = (static_cast<uint32_t>(cpu_info[2]) & 0x80000000) != 0;
209
210 // AVX instructions will generate an illegal instruction exception unless
211 // a) they are supported by the CPU,
212 // b) XSAVE is supported by the CPU and
213 // c) XSAVE is enabled by the kernel.
214 // See http://software.intel.com/en-us/blogs/2011/04/14/is-avx-enabled
215 //
216 // In addition, we have observed some crashes with the xgetbv instruction
217 // even after following Intel's example code. (See crbug.com/375968.)
218 // Because of that, we also test the XSAVE bit because its description in
219 // the CPUID documentation suggests that it signals xgetbv support.
220 has_avx_ =
221 (cpu_info[2] & 0x10000000) != 0 &&
222 (cpu_info[2] & 0x04000000) != 0 /* XSAVE */ &&
223 (cpu_info[2] & 0x08000000) != 0 /* OSXSAVE */ &&
224 (xgetbv(0) & 6) == 6 /* XSAVE enabled by kernel */;
225 has_aesni_ = (cpu_info[2] & 0x02000000) != 0;
226 has_fma3_ = (cpu_info[2] & 0x00001000) != 0;
227 if (has_avx_) {
228 has_avx2_ = (cpu_info7[1] & 0x00000020) != 0;
229 has_avx_vnni_ = (cpu_einfo7[0] & 0x00000010) != 0;
230 // Check AVX-512 state, bits 5-7.
231 if ((xgetbv(0) & 0xe0) == 0xe0) {
232 has_avx512_f_ = (cpu_info7[1] & 0x00010000) != 0;
233 has_avx512_bw_ = (cpu_info7[1] & 0x40000000) != 0;
234 has_avx512_vnni_ = (cpu_info7[2] & 0x00000800) != 0;
235 }
236 }
237
238 has_pku_ = (cpu_info7[2] & 0x00000010) != 0;
239 }
240
241 // Get the brand string of the cpu.
242 __cpuid(cpu_info, static_cast<int>(0x80000000));
243 const uint32_t max_parameter = static_cast<uint32_t>(cpu_info[0]);
244
245 static constexpr uint32_t kParameterStart = 0x80000002;
246 static constexpr uint32_t kParameterEnd = 0x80000004;
247 static constexpr uint32_t kParameterSize =
248 kParameterEnd - kParameterStart + 1;
249 static_assert(kParameterSize * sizeof(cpu_info) == kBrandNameSize,
250 "cpu_brand_ has wrong size");
251
252 if (max_parameter >= kParameterEnd) {
253 SpanWriter writer{span(cpu_brand_)};
254 for (uint32_t parameter = kParameterStart; parameter <= kParameterEnd;
255 ++parameter) {
256 __cpuid(cpu_info, static_cast<int>(parameter));
257 writer.Write(as_chars(span(cpu_info)));
258 }
259 writer.Write('\0');
260 }
261
262 static constexpr uint32_t kParameterContainingNonStopTimeStampCounter =
263 0x80000007;
264 if (max_parameter >= kParameterContainingNonStopTimeStampCounter) {
265 __cpuid(cpu_info,
266 static_cast<int>(kParameterContainingNonStopTimeStampCounter));
267 has_non_stop_time_stamp_counter_ = (cpu_info[3] & (1 << 8)) != 0;
268 }
269
270 if (!has_non_stop_time_stamp_counter_ && is_running_in_vm_) {
271 int cpu_info_hv[4] = {};
272 __cpuid(cpu_info_hv, 0x40000000);
273 if (cpu_info_hv[1] == 0x7263694D && // Micr
274 cpu_info_hv[2] == 0x666F736F && // osof
275 cpu_info_hv[3] == 0x76482074) { // t Hv
276 // If CPUID says we have a variant TSC and a hypervisor has identified
277 // itself and the hypervisor says it is Microsoft Hyper-V, then treat
278 // TSC as invariant.
279 //
280 // Microsoft Hyper-V hypervisor reports variant TSC as there are some
281 // scenarios (eg. VM live migration) where the TSC is variant, but for
282 // our purposes we can treat it as invariant.
283 has_non_stop_time_stamp_counter_ = true;
284 }
285 }
286 #elif defined(ARCH_CPU_ARM_FAMILY)
287 #if defined(ARCH_CPU_ARM64) && \
288 (BUILDFLAG(IS_ANDROID) || BUILDFLAG(IS_LINUX) || BUILDFLAG(IS_CHROMEOS))
289 // Check for Armv8.5-A BTI/MTE support, exposed via HWCAP2
290 unsigned long hwcap2 = getauxval(AT_HWCAP2);
291 has_mte_ = hwcap2 & HWCAP2_MTE;
292 has_bti_ = hwcap2 & HWCAP2_BTI;
293 #elif BUILDFLAG(IS_WIN)
294 // Windows makes high-resolution thread timing information available in
295 // user-space.
296 has_non_stop_time_stamp_counter_ = true;
297 #endif
298 #endif
299 }
300
301 #if defined(ARCH_CPU_X86_FAMILY)
GetIntelMicroArchitecture() const302 CPU::IntelMicroArchitecture CPU::GetIntelMicroArchitecture() const {
303 if (has_avx512_vnni()) return AVX512_VNNI;
304 if (has_avx512_bw()) return AVX512BW;
305 if (has_avx512_f()) return AVX512F;
306 if (has_avx_vnni()) return AVX_VNNI;
307 if (has_avx2()) return AVX2;
308 if (has_fma3()) return FMA3;
309 if (has_avx()) return AVX;
310 if (has_sse42()) return SSE42;
311 if (has_sse41()) return SSE41;
312 if (has_ssse3()) return SSSE3;
313 if (has_sse3()) return SSE3;
314 if (has_sse2()) return SSE2;
315 if (has_sse()) return SSE;
316 return PENTIUM;
317 }
318 #endif
319
GetInstanceNoAllocation()320 const CPU& CPU::GetInstanceNoAllocation() {
321 static ProtectedMemoryInitializer cpu_initializer(g_cpu_instance, CPU());
322
323 return *g_cpu_instance;
324 }
325
326 } // namespace base
327