1 // Copyright 2019 The Chromium Authors
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 #ifdef UNSAFE_BUFFERS_BUILD
6 // TODO(crbug.com/40284755): Remove this and spanify to fix the errors.
7 #pragma allow_unsafe_buffers
8 #endif
9
10 #include "base/profiler/thread_delegate_posix.h"
11
12 #include <inttypes.h>
13 #include <pthread.h>
14 #include <stdio.h>
15
16 #include <optional>
17
18 #include "base/memory/ptr_util.h"
19 #include "base/process/process_handle.h"
20 #include "build/build_config.h"
21
22 #if !(BUILDFLAG(IS_LINUX) || BUILDFLAG(IS_CHROMEOS))
23 #include "base/profiler/stack_base_address_posix.h"
24 #endif
25
26 namespace base {
27 // static
Create(SamplingProfilerThreadToken thread_token)28 std::unique_ptr<ThreadDelegatePosix> ThreadDelegatePosix::Create(
29 SamplingProfilerThreadToken thread_token) {
30 std::optional<uintptr_t> base_address;
31 #if BUILDFLAG(IS_LINUX) || BUILDFLAG(IS_CHROMEOS)
32 base_address = thread_token.stack_base_address;
33 #else
34 base_address =
35 GetThreadStackBaseAddress(thread_token.id, thread_token.pthread_id);
36 #endif
37 if (!base_address)
38 return nullptr;
39 return base::WrapUnique(
40 new ThreadDelegatePosix(thread_token.id, *base_address));
41 }
42
43 ThreadDelegatePosix::~ThreadDelegatePosix() = default;
44
GetThreadId() const45 PlatformThreadId ThreadDelegatePosix::GetThreadId() const {
46 return thread_id_;
47 }
48
GetStackBaseAddress() const49 uintptr_t ThreadDelegatePosix::GetStackBaseAddress() const {
50 return thread_stack_base_address_;
51 }
52
GetRegistersToRewrite(RegisterContext * thread_context)53 std::vector<uintptr_t*> ThreadDelegatePosix::GetRegistersToRewrite(
54 RegisterContext* thread_context) {
55 #if defined(ARCH_CPU_ARM_FAMILY) && defined(ARCH_CPU_32_BITS)
56 return {
57 reinterpret_cast<uintptr_t*>(&thread_context->arm_r0),
58 reinterpret_cast<uintptr_t*>(&thread_context->arm_r1),
59 reinterpret_cast<uintptr_t*>(&thread_context->arm_r2),
60 reinterpret_cast<uintptr_t*>(&thread_context->arm_r3),
61 reinterpret_cast<uintptr_t*>(&thread_context->arm_r4),
62 reinterpret_cast<uintptr_t*>(&thread_context->arm_r5),
63 reinterpret_cast<uintptr_t*>(&thread_context->arm_r6),
64 reinterpret_cast<uintptr_t*>(&thread_context->arm_r7),
65 reinterpret_cast<uintptr_t*>(&thread_context->arm_r8),
66 reinterpret_cast<uintptr_t*>(&thread_context->arm_r9),
67 reinterpret_cast<uintptr_t*>(&thread_context->arm_r10),
68 reinterpret_cast<uintptr_t*>(&thread_context->arm_fp),
69 reinterpret_cast<uintptr_t*>(&thread_context->arm_ip),
70 reinterpret_cast<uintptr_t*>(&thread_context->arm_sp),
71 // arm_lr and arm_pc do not require rewriting because they contain
72 // addresses of executable code, not addresses in the stack.
73 };
74 #elif defined(ARCH_CPU_ARM_FAMILY) && \
75 defined(ARCH_CPU_64_BITS) // #if defined(ARCH_CPU_ARM_FAMILY) &&
76 // defined(ARCH_CPU_32_BITS)
77 std::vector<uintptr_t*> registers;
78 registers.reserve(12);
79 // Return the set of callee-save registers per the ARM 64-bit Procedure Call
80 // Standard section 5.1.1, plus the stack pointer.
81 registers.push_back(reinterpret_cast<uintptr_t*>(&thread_context->sp));
82 for (size_t i = 19; i <= 29; ++i)
83 registers.push_back(reinterpret_cast<uintptr_t*>(&thread_context->regs[i]));
84 return registers;
85 #elif defined(ARCH_CPU_X86_FAMILY) && defined(ARCH_CPU_32_BITS)
86 return {
87 // Return the set of callee-save registers per the i386 System V ABI
88 // section 2.2.3, plus the stack pointer.
89 reinterpret_cast<uintptr_t*>(&thread_context->gregs[REG_EBX]),
90 reinterpret_cast<uintptr_t*>(&thread_context->gregs[REG_EBP]),
91 reinterpret_cast<uintptr_t*>(&thread_context->gregs[REG_ESI]),
92 reinterpret_cast<uintptr_t*>(&thread_context->gregs[REG_EDI]),
93 reinterpret_cast<uintptr_t*>(&thread_context->gregs[REG_ESP]),
94 };
95 #elif defined(ARCH_CPU_X86_FAMILY) && defined(ARCH_CPU_64_BITS)
96 return {
97 // Return the set of callee-save registers per the x86-64 System V ABI
98 // section 3.2.1, plus the stack pointer.
99 reinterpret_cast<uintptr_t*>(&thread_context->gregs[REG_RBP]),
100 reinterpret_cast<uintptr_t*>(&thread_context->gregs[REG_RBX]),
101 reinterpret_cast<uintptr_t*>(&thread_context->gregs[REG_R12]),
102 reinterpret_cast<uintptr_t*>(&thread_context->gregs[REG_R13]),
103 reinterpret_cast<uintptr_t*>(&thread_context->gregs[REG_R14]),
104 reinterpret_cast<uintptr_t*>(&thread_context->gregs[REG_R15]),
105 reinterpret_cast<uintptr_t*>(&thread_context->gregs[REG_RSP]),
106 };
107 #else // #if defined(ARCH_CPU_ARM_FAMILY) && defined(ARCH_CPU_32_BITS)
108 // Unimplemented for other architectures.
109 return {};
110 #endif
111 }
112
ThreadDelegatePosix(PlatformThreadId id,uintptr_t base_address)113 ThreadDelegatePosix::ThreadDelegatePosix(PlatformThreadId id,
114 uintptr_t base_address)
115 : thread_id_(id), thread_stack_base_address_(base_address) {}
116
117 } // namespace base
118