1 #ifndef CMIS_H__ 2 #define CMIS_H__ 3 4 /* Identifier and revision compliance (Page 0) */ 5 #define CMIS_ID_OFFSET 0x00 6 #define CMIS_REV_COMPLIANCE_OFFSET 0x01 7 #define CMIS_MEMORY_MODEL_OFFSET 0x02 8 #define CMIS_MEMORY_MODEL_MASK 0x80 9 10 /* Global Status Information (Page 0) */ 11 #define CMIS_MODULE_STATE_OFFSET 0x03 12 #define CMIS_MODULE_STATE_MASK 0x0E 13 #define CMIS_MODULE_STATE_MODULE_LOW_PWR 0x01 14 #define CMIS_MODULE_STATE_MODULE_PWR_UP 0x02 15 #define CMIS_MODULE_STATE_MODULE_READY 0x03 16 #define CMIS_MODULE_STATE_MODULE_PWR_DN 0x04 17 #define CMIS_MODULE_STATE_MODULE_FAULT 0x05 18 19 /* Module Flags (Page 0) */ 20 #define CMIS_VCC_AW_OFFSET 0x09 21 #define CMIS_VCC_LWARN_STATUS 0x80 22 #define CMIS_VCC_HWARN_STATUS 0x40 23 #define CMIS_VCC_LALARM_STATUS 0x20 24 #define CMIS_VCC_HALARM_STATUS 0x10 25 #define CMIS_TEMP_AW_OFFSET 0x09 26 #define CMIS_TEMP_LWARN_STATUS 0x08 27 #define CMIS_TEMP_HWARN_STATUS 0x04 28 #define CMIS_TEMP_LALARM_STATUS 0x02 29 #define CMIS_TEMP_HALARM_STATUS 0x01 30 31 #define CMIS_MODULE_TYPE_OFFSET 0x55 32 #define CMIS_MT_MMF 0x01 33 #define CMIS_MT_SMF 0x02 34 35 /* Module-Level Monitors (Page 0) */ 36 #define CMIS_CURR_TEMP_OFFSET 0x0E 37 #define CMIS_CURR_VCC_OFFSET 0x10 38 39 /* Module Global Controls (Page 0) */ 40 #define CMIS_MODULE_CONTROL_OFFSET 0x1A 41 #define CMIS_LOW_PWR_ALLOW_REQUEST_HW_MASK 0x40 42 #define CMIS_LOW_PWR_REQUEST_SW_MASK 0x10 43 44 /* Module Active Firmware Version (Page 0) */ 45 #define CMIS_MODULE_ACTIVE_FW_MAJOR_OFFSET 0x27 46 #define CMIS_MODULE_ACTIVE_FW_MINOR_OFFSET 0x28 47 48 /* Module Fault Information (Page 0) */ 49 #define CMIS_MODULE_FAULT_OFFSET 0x29 50 #define CMIS_MODULE_FAULT_NO_FAULT 0x00 51 #define CMIS_MODULE_FAULT_TEC_RUNAWAY 0x01 52 #define CMIS_MODULE_FAULT_DATA_MEM_CORRUPTED 0x02 53 #define CMIS_MODULE_FAULT_PROG_MEM_CORRUPTED 0x03 54 55 #define CMIS_CTOR_OFFSET 0xCB 56 57 /* Vendor related information (Page 0) */ 58 #define CMIS_VENDOR_NAME_START_OFFSET 0x81 59 #define CMIS_VENDOR_NAME_END_OFFSET 0x90 60 61 #define CMIS_VENDOR_OUI_OFFSET 0x91 62 63 #define CMIS_VENDOR_PN_START_OFFSET 0x94 64 #define CMIS_VENDOR_PN_END_OFFSET 0xA3 65 66 #define CMIS_VENDOR_REV_START_OFFSET 0xA4 67 #define CMIS_VENDOR_REV_END_OFFSET 0xA5 68 69 #define CMIS_VENDOR_SN_START_OFFSET 0xA6 70 #define CMIS_VENDOR_SN_END_OFFSET 0xB5 71 72 #define CMIS_DATE_YEAR_OFFSET 0xB6 73 #define CMIS_DATE_VENDOR_LOT_OFFSET 0xBC 74 75 /* CLEI Code (Page 0) */ 76 #define CMIS_CLEI_START_OFFSET 0xBE 77 #define CMIS_CLEI_END_OFFSET 0xC7 78 #define CMIS_CLEI_BLANK " " 79 #define CMIS_CLEI_LEN 0x0A 80 81 /* Cable assembly length */ 82 #define CMIS_CBL_ASM_LEN_OFFSET 0xCA 83 #define CMIS_6300M_MAX_LEN 0xFF 84 85 /* Cable length with multiplier */ 86 #define CMIS_MULTIPLIER_00 0x00 87 #define CMIS_MULTIPLIER_01 0x40 88 #define CMIS_MULTIPLIER_10 0x80 89 #define CMIS_MULTIPLIER_11 0xC0 90 #define CMIS_LEN_MUL_MASK 0xC0 91 #define CMIS_LEN_VAL_MASK 0x3F 92 93 /* Module power characteristics */ 94 #define CMIS_PWR_CLASS_OFFSET 0xC8 95 #define CMIS_PWR_MAX_POWER_OFFSET 0xC9 96 #define CMIS_PWR_CLASS_MASK 0xE0 97 #define CMIS_PWR_CLASS_1 0x00 98 #define CMIS_PWR_CLASS_2 0x01 99 #define CMIS_PWR_CLASS_3 0x02 100 #define CMIS_PWR_CLASS_4 0x03 101 #define CMIS_PWR_CLASS_5 0x04 102 #define CMIS_PWR_CLASS_6 0x05 103 #define CMIS_PWR_CLASS_7 0x06 104 #define CMIS_PWR_CLASS_8 0x07 105 106 /* Copper cable attenuation */ 107 #define CMIS_COPPER_ATT_5GHZ 0xCC 108 #define CMIS_COPPER_ATT_7GHZ 0xCD 109 #define CMIS_COPPER_ATT_12P9GHZ 0xCE 110 #define CMIS_COPPER_ATT_25P8GHZ 0xCF 111 112 /* Cable assembly lane */ 113 #define CMIS_CABLE_ASM_NEAR_END_OFFSET 0xD2 114 #define CMIS_CABLE_ASM_FAR_END_OFFSET 0xD3 115 116 /* Media interface technology */ 117 #define CMIS_MEDIA_INTF_TECH_OFFSET 0xD4 118 #define CMIS_850_VCSEL 0x00 119 #define CMIS_1310_VCSEL 0x01 120 #define CMIS_1550_VCSEL 0x02 121 #define CMIS_1310_FP 0x03 122 #define CMIS_1310_DFB 0x04 123 #define CMIS_1550_DFB 0x05 124 #define CMIS_1310_EML 0x06 125 #define CMIS_1550_EML 0x07 126 #define CMIS_OTHERS 0x08 127 #define CMIS_1490_DFB 0x09 128 #define CMIS_COPPER_UNEQUAL 0x0A 129 #define CMIS_COPPER_PASS_EQUAL 0x0B 130 #define CMIS_COPPER_NF_EQUAL 0x0C 131 #define CMIS_COPPER_F_EQUAL 0x0D 132 #define CMIS_COPPER_N_EQUAL 0x0E 133 #define CMIS_COPPER_LINEAR_EQUAL 0x0F 134 135 /*----------------------------------------------------------------------- 136 * Upper Memory Page 0x01: contains advertising fields that define properties 137 * that are unique to active modules and cable assemblies. 138 * GlobalOffset = 2 * 0x80 + LocalOffset 139 */ 140 141 /* Module Inactive Firmware Version (Page 1) */ 142 #define CMIS_MODULE_INACTIVE_FW_MAJOR_OFFSET 0x80 143 #define CMIS_MODULE_INACTIVE_FW_MINOR_OFFSET 0x81 144 145 /* Supported Link Length (Page 1) */ 146 #define CMIS_SMF_LEN_OFFSET 0x84 147 #define CMIS_OM5_LEN_OFFSET 0x85 148 #define CMIS_OM4_LEN_OFFSET 0x86 149 #define CMIS_OM3_LEN_OFFSET 0x87 150 #define CMIS_OM2_LEN_OFFSET 0x88 151 152 /* Wavelength (Page 1) */ 153 #define CMIS_NOM_WAVELENGTH_MSB 0x8A 154 #define CMIS_NOM_WAVELENGTH_LSB 0x8B 155 #define CMIS_WAVELENGTH_TOL_MSB 0x8C 156 #define CMIS_WAVELENGTH_TOL_LSB 0x8D 157 158 /* Supported Pages Advertising (Page 1) */ 159 #define CMIS_PAGES_ADVER_OFFSET 0x8E 160 #define CMIS_BANKS_SUPPORTED_MASK 0x03 161 #define CMIS_BANK_0_SUPPORTED 0x00 162 #define CMIS_BANK_0_1_SUPPORTED 0x01 163 #define CMIS_BANK_0_3_SUPPORTED 0x02 164 165 /* Module Characteristics Advertising (Page 1) */ 166 #define CMIS_DIAG_TYPE_OFFSET 0x97 167 #define CMIS_RX_PWR_TYPE_MASK 0x10 168 169 /* Supported Flags Advertisement (Page 1) */ 170 #define CMIS_DIAG_FLAGS_TX_OFFSET 0x9d 171 #define CMIS_DIAG_FL_TX_ADAPTIVE_EQ_FAIL (1 << 3) 172 #define CMIS_DIAG_FL_TX_LOL (1 << 2) 173 #define CMIS_DIAG_FL_TX_LOS (1 << 1) 174 #define CMIS_DIAG_FL_TX_FAIL (1 << 0) 175 176 #define CMIS_DIAG_FLAGS_RX_OFFSET 0x9e 177 #define CMIS_DIAG_FL_RX_LOL (1 << 2) 178 #define CMIS_DIAG_FL_RX_LOS (1 << 1) 179 180 /* Supported Monitors Advertisement (Page 1) */ 181 #define CMIS_DIAG_CHAN_ADVER_OFFSET 0xA0 182 #define CMIS_TX_BIAS_MON_MASK 0x01 183 #define CMIS_TX_PWR_MON_MASK 0x02 184 #define CMIS_RX_PWR_MON_MASK 0x04 185 #define CMIS_TX_BIAS_MUL_MASK 0x18 186 #define CMIS_TX_BIAS_MUL_1 0x00 187 #define CMIS_TX_BIAS_MUL_2 0x08 188 #define CMIS_TX_BIAS_MUL_4 0x10 189 190 /* Signal integrity controls */ 191 #define CMIS_SIG_INTEG_TX_OFFSET 0xA1 192 #define CMIS_SIG_INTEG_RX_OFFSET 0xA2 193 194 /* CDB Messaging Support Advertisement */ 195 #define CMIS_CDB_ADVER_OFFSET 0xA3 196 #define CMIS_CDB_ADVER_INSTANCES_MASK 0xC0 197 #define CMIS_CDB_ADVER_MODE_MASK 0x20 198 #define CMIS_CDB_ADVER_EPL_MASK 0x0F 199 200 #define CMIS_CDB_ADVER_RW_LEN_OFFSET 0xA4 201 202 #define CMIS_CDB_ADVER_TRIGGER_OFFSET 0xA5 203 #define CMIS_CDB_ADVER_TRIGGER_MASK 0x80 204 205 /*----------------------------------------------------------------------- 206 * Upper Memory Page 0x02: Optional Page that informs about module-defined 207 * thresholds for module-level and lane-specific threshold crossing monitors. 208 */ 209 210 /* Module-Level Monitor Thresholds (Page 2) */ 211 #define CMIS_TEMP_HALRM_OFFSET 0x80 212 #define CMIS_TEMP_LALRM_OFFSET 0x82 213 #define CMIS_TEMP_HWARN_OFFSET 0x84 214 #define CMIS_TEMP_LWARN_OFFSET 0x86 215 #define CMIS_VCC_HALRM_OFFSET 0x88 216 #define CMIS_VCC_LALRM_OFFSET 0x8A 217 #define CMIS_VCC_HWARN_OFFSET 0x8C 218 #define CMIS_VCC_LWARN_OFFSET 0x8E 219 220 /* Lane-Related Monitor Thresholds (Page 2) */ 221 #define CMIS_TX_PWR_HALRM_OFFSET 0xB0 222 #define CMIS_TX_PWR_LALRM_OFFSET 0xB2 223 #define CMIS_TX_PWR_HWARN_OFFSET 0xB4 224 #define CMIS_TX_PWR_LWARN_OFFSET 0xB6 225 #define CMIS_TX_BIAS_HALRM_OFFSET 0xB8 226 #define CMIS_TX_BIAS_LALRM_OFFSET 0xBA 227 #define CMIS_TX_BIAS_HWARN_OFFSET 0xBC 228 #define CMIS_TX_BIAS_LWARN_OFFSET 0xBE 229 #define CMIS_RX_PWR_HALRM_OFFSET 0xC0 230 #define CMIS_RX_PWR_LALRM_OFFSET 0xC2 231 #define CMIS_RX_PWR_HWARN_OFFSET 0xC4 232 #define CMIS_RX_PWR_LWARN_OFFSET 0xC6 233 234 /*----------------------------------------------------------------------- 235 * Upper Memory Page 0x11: Optional Page that contains lane dynamic status 236 * bytes. 237 */ 238 239 /* Media Lane-Specific Flags (Page 0x11) */ 240 #define CMIS_TX_FAIL_OFFSET 0x87 241 #define CMIS_TX_LOS_OFFSET 0x88 242 #define CMIS_TX_LOL_OFFSET 0x89 243 #define CMIS_TX_EQ_FAIL_OFFSET 0x8a 244 #define CMIS_TX_PWR_AW_HALARM_OFFSET 0x8B 245 #define CMIS_TX_PWR_AW_LALARM_OFFSET 0x8C 246 #define CMIS_TX_PWR_AW_HWARN_OFFSET 0x8D 247 #define CMIS_TX_PWR_AW_LWARN_OFFSET 0x8E 248 #define CMIS_TX_BIAS_AW_HALARM_OFFSET 0x8F 249 #define CMIS_TX_BIAS_AW_LALARM_OFFSET 0x90 250 #define CMIS_TX_BIAS_AW_HWARN_OFFSET 0x91 251 #define CMIS_TX_BIAS_AW_LWARN_OFFSET 0x92 252 #define CMIS_RX_LOS_OFFSET 0x93 253 #define CMIS_RX_LOL_OFFSET 0x94 254 #define CMIS_RX_PWR_AW_HALARM_OFFSET 0x95 255 #define CMIS_RX_PWR_AW_LALARM_OFFSET 0x96 256 #define CMIS_RX_PWR_AW_HWARN_OFFSET 0x97 257 #define CMIS_RX_PWR_AW_LWARN_OFFSET 0x98 258 259 /* Media Lane-Specific Monitors (Page 0x11) */ 260 #define CMIS_TX_PWR_OFFSET 0x9A 261 #define CMIS_TX_BIAS_OFFSET 0xAA 262 #define CMIS_RX_PWR_OFFSET 0xBA 263 264 #define YESNO(x) (((x) != 0) ? "Yes" : "No") 265 #define ONOFF(x) (((x) != 0) ? "On" : "Off") 266 267 void cmis_show_all_ioctl(const __u8 *id); 268 269 int cmis_show_all_nl(struct cmd_context *ctx); 270 271 #endif /* CMIS_H__ */ 272