1========== 2Bus Pirate 3========== 4 5The `Bus Pirate <http://dangerousprototypes.com/docs/Bus_Pirate>`_ is an open source design 6for a multi-purpose chip-level serial protocol transceiver and debugger. 7flashrom supports the Bus Pirate for `SPI programming <http://dangerousprototypes.com/docs/SPI>`_. 8It also has `SPI sniffing <http://dangerousprototypes.com/docs/Bus_Pirate_binary_SPI_sniffer_utility>`_ 9functionality, which may come in useful for analysing chip or programmer behaviour. 10 11They are available for around US$30 from various sources. 12 13Connections 14=========== 15 16The table below shows how a typical SPI flash chip (sitting in the center of the table) 17needs to be connected (NB: not all flash chips feature all of the pins below, but in general 18you should always connect all input pins of ICs to some defined potential (usually GND or VCC), 19ideally with a pull-up/down resistor in between). Most SPI flash chips require a 3.3V supply voltage, 20but there exist some models that use e.g. 1.8V. Make sure the device in question is compatible 21before connecting any wires. 22 23*NB: Some rather rare SPI flash chips (e.g. Atmel AT45DB series) have a completely different layout, please beware.* 24 25+----------------------+------------+------+---------------------------------+------+------------+-----------------------------+ 26| Description | Bus Pirate | Dir. | Flash chip | Dir. | Bus Pirate | Description | 27+======================+============+======+===+===========+=============+===+======+============+=============================+ 28| (not) Chip Select | CS | → | 1 | /CS | VCC | 8 | ← | +3.3v | Supply | 29+----------------------+------------+------+---+-----------+-------------+---+------+------------+-----------------------------+ 30| Master In, Slave Out | MISO | ← | 2 | DO (IO1) | /HOLD (IO3) | 7 | ← | +3.3v | (not) hold (see datasheets) | 31+----------------------+------------+------+---+-----------+-------------+---+------+------------+-----------------------------+ 32| (not) Write Protect | +3.3v | → | 3 | /WP (IO2) | CLK | 6 | ← | CLK | The SPI clock | 33+----------------------+------------+------+---+-----------+-------------+---+------+------------+-----------------------------+ 34| Ground | GND | → | 4 | GND | DI (IO0) | 5 | ← | MOSI | Master Out, Slave In | 35+----------------------+------------+------+---+-----------+-------------+---+------+------------+-----------------------------+ 36 37Usage 38========= 39 40:: 41 42 $ flashrom -p buspirate_spi:dev=/dev/device,spispeed=frequency 43 44Example:: 45 46 $ flashrom -p buspirate_spi:dev=/dev/ttyUSB0,spispeed=1M 47 48Troubleshooting 49=============== 50 51In case of problems probing the chip with flashrom - especially when connecting chips 52still soldered in a system - please take a look at the doc :doc:`/user_docs/in_system`. In-system programming is often possible 53**only as long as no other devices on the SPI bus are trying to access the device**. 54 55Speedup 56========= 57 58A beta firmware build exists, to speed up the buspirate. 59`See this post on dangerousprototypes.com <http://dangerousprototypes.com/forum/viewtopic.php?f=40&t=3864&start=15#p41505>`_ 60 61See also: http://dangerousprototypes.com/docs/Bus_Pirate#Firmware_upgrades 62 63Images 64========== 65 66Bus Pirate v3, front. 67 68.. image:: Buspirate_v3_front.jpg 69 70Bus Pirate v3, back. 71 72.. image:: Buspirate_v3_back.jpg 73 74Recovering a bricked Lycom PE-115 88SE8123 PCIe to SATA adapter using flashrom and a Bus Pirate - power to the 75PE-115 is supplied by a PC. The test probes of the bus pirate are attached directly to the SOIC Atmel AT26F004 SPI flash chip. 76The other test clip is connected to GND on another device for convenience (easier than getting yet another clip onto a SOIC device). 77 78.. image:: Lycom-pe115-flashrom-buspirate-2.jpg 79
