1 /* 2 * Copyright (c) 2016-2018, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_mi_g11_X.h 24 //! \brief Defines functions for constructing HW commands on Gen11-based platforms 25 //! 26 27 #ifndef __MHW_MI_G11_X_H__ 28 #define __MHW_MI_G11_X_H__ 29 30 #include "mhw_mi_generic.h" 31 #include "mhw_mi_hwcmd_g11_X.h" 32 33 struct MhwMiInterfaceG11 : public MhwMiInterfaceGeneric<mhw_mi_g11_X> 34 { MhwMiInterfaceG11MhwMiInterfaceG1135 MhwMiInterfaceG11( 36 MhwCpInterface *cpInterface, 37 PMOS_INTERFACE osInterface) : 38 MhwMiInterfaceGeneric(cpInterface, osInterface) 39 { 40 MHW_FUNCTION_ENTER; 41 InitMmioRegisters(); 42 } 43 ~MhwMiInterfaceG11MhwMiInterfaceG1144 ~MhwMiInterfaceG11() { MHW_FUNCTION_ENTER; }; 45 46 MOS_STATUS AddMiConditionalBatchBufferEndCmd( 47 PMOS_COMMAND_BUFFER cmdBuffer, 48 PMHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS params); 49 50 MOS_STATUS AddMiBatchBufferStartCmd( 51 PMOS_COMMAND_BUFFER cmdBuffer, 52 PMHW_BATCH_BUFFER batchBuffer); 53 54 MOS_STATUS AddMiStoreRegisterMemCmd( 55 PMOS_COMMAND_BUFFER cmdBuffer, 56 PMHW_MI_STORE_REGISTER_MEM_PARAMS params); 57 58 MOS_STATUS AddMiLoadRegisterMemCmd( 59 PMOS_COMMAND_BUFFER cmdBuffer, 60 PMHW_MI_STORE_REGISTER_MEM_PARAMS params); 61 62 MOS_STATUS AddMiLoadRegisterImmCmd( 63 PMOS_COMMAND_BUFFER cmdBuffer, 64 PMHW_MI_LOAD_REGISTER_IMM_PARAMS params); 65 66 MOS_STATUS AddMiLoadRegisterRegCmd( 67 PMOS_COMMAND_BUFFER cmdBuffer, 68 PMHW_MI_LOAD_REGISTER_REG_PARAMS params); 69 70 MOS_STATUS AddMiSemaphoreWaitCmd( 71 PMOS_COMMAND_BUFFER cmdBuffer, 72 PMHW_MI_SEMAPHORE_WAIT_PARAMS params); 73 74 MOS_STATUS SetWatchdogTimerThreshold( 75 uint32_t frameWidth, 76 uint32_t frameHeight, 77 bool isEncoder = true); 78 79 MOS_STATUS SetWatchdogTimerRegisterOffset( 80 MOS_GPU_CONTEXT gpuContext); 81 82 MOS_STATUS AddWatchdogTimerStartCmd( 83 PMOS_COMMAND_BUFFER cmdBuffer); 84 85 MOS_STATUS AddWatchdogTimerStopCmd( 86 PMOS_COMMAND_BUFFER cmdBuffer); 87 88 MOS_STATUS AddMediaStateFlush( 89 PMOS_COMMAND_BUFFER cmdBuffer, 90 PMHW_BATCH_BUFFER batchBuffer, 91 PMHW_MEDIA_STATE_FLUSH_PARAM params = nullptr); 92 93 MOS_STATUS SkipMiBatchBufferEndBb( 94 PMHW_BATCH_BUFFER batchBuffer); 95 96 MOS_STATUS AddMiFlushDwCmd( 97 PMOS_COMMAND_BUFFER cmdBuffer, 98 PMHW_MI_FLUSH_DW_PARAMS params); 99 100 void InitMmioRegisters(); 101 102 private: 103 // MMIO Range 0x1C0000 - 0x200000 is used for Media VDBox or VEBox 104 // Each media engine has a range from 0 to 0x3FFF for relative access 105 // 106 static const uint32_t m_mmioMaxRelativeOffset = 0x3FFF; //!< Max reg relative offset in an engine 107 static const uint32_t m_mmioMediaLowOffset = 0x1C0000; //!< Low bound of VDBox and VEBox MMIO offset 108 static const uint32_t m_mmioMediaHighOffset = 0x200000; //!< High bound of VDBox and VEBox MMIO offset 109 110 //! 111 //! \brief Check and convert meida registers to relative offset 112 //! \details Check if an abusolute register offset is VDbox or VEBox register and convert it to relative if so 113 //! \param [in/out] reg 114 //! Register to be checked and converted 115 //! \return bool 116 //! Return true if it is VDBox or VEBox register 117 //! IsRelativeMMIOMhwMiInterfaceG11118 bool IsRelativeMMIO(uint32_t ®) 119 { 120 MOS_GPU_CONTEXT gpuContext = m_osInterface->pfnGetGpuContext(m_osInterface); 121 122 if ((MOS_VCS_ENGINE_USED(gpuContext) || MOS_VECS_ENGINE_USED(gpuContext)) && 123 (reg >= m_mmioMediaLowOffset && reg < m_mmioMediaHighOffset)) 124 { 125 reg &= m_mmioMaxRelativeOffset; 126 return true; 127 } 128 return false; 129 } 130 }; 131 132 #endif 133