1 /* 2 * Copyright © 2021 Advanced Micro Devices, Inc. 3 * 4 * SPDX-License-Identifier: MIT 5 */ 6 7 #ifndef AC_DRM_FOURCC_H 8 #define AC_DRM_FOURCC_H 9 10 #ifdef _WIN32 11 #include <stdint.h> 12 typedef uint64_t __u64; 13 #define DRM_FORMAT_MOD_VENDOR_NONE 0 14 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 15 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 16 #define fourcc_mod_code(vendor, val) \ 17 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 18 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 19 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 20 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) 21 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) 22 #define AMD_FMT_MOD_TILE_VER_GFX9 1 23 #define AMD_FMT_MOD_TILE_VER_GFX10 2 24 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 25 #define AMD_FMT_MOD_TILE_VER_GFX11 4 26 #define AMD_FMT_MOD_TILE_VER_GFX12 5 27 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9 28 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 29 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 30 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 31 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 32 #define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31 33 #define AMD_FMT_MOD_TILE_GFX12_256B_2D 1 34 #define AMD_FMT_MOD_TILE_GFX12_4K_2D 2 35 #define AMD_FMT_MOD_TILE_GFX12_64K_2D 3 36 #define AMD_FMT_MOD_TILE_GFX12_256K_2D 4 37 #define AMD_FMT_MOD_DCC_BLOCK_64B 0 38 #define AMD_FMT_MOD_DCC_BLOCK_128B 1 39 #define AMD_FMT_MOD_DCC_BLOCK_256B 2 40 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 41 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF 42 #define AMD_FMT_MOD_TILE_SHIFT 8 43 #define AMD_FMT_MOD_TILE_MASK 0x1F 44 #define AMD_FMT_MOD_DCC_SHIFT 13 45 #define AMD_FMT_MOD_DCC_MASK 0x1 46 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 47 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 48 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 49 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 50 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 51 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 52 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 53 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 54 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 55 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 56 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 57 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 58 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 59 #define AMD_FMT_MOD_PACKERS_SHIFT 27 /* aliases with BANK_XOR_BITS */ 60 #define AMD_FMT_MOD_RB_SHIFT 30 61 #define AMD_FMT_MOD_RB_MASK 0x7 62 #define AMD_FMT_MOD_PIPE_SHIFT 33 63 #define AMD_FMT_MOD_SET(field, value) \ 64 ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) 65 #define AMD_FMT_MOD_GET(field, value) \ 66 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) 67 #else 68 #include "drm-uapi/drm_fourcc.h" 69 #endif 70 71 #endif /* AC_DRM_FOURCC_H */ 72