1 /*
2 * Copyright © 2021 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 */
7
8 #ifndef AC_SURFACE_TEST_COMMON_H
9 #define AC_SURFACE_TEST_COMMON_H
10
11 #include "ac_gpu_info.h"
12 #include "amdgfxregs.h"
13 #include "addrlib/src/amdgpu_asic_addr.h"
14
15 #ifdef _WIN32
16 #define AMDGPU_FAMILY_VI 130
17 #define AMDGPU_FAMILY_AI 141
18 #define AMDGPU_FAMILY_RV 142
19 #define AMDGPU_FAMILY_NV 143
20 #else
21 #include "drm-uapi/amdgpu_drm.h"
22 #endif
23
24 typedef void (*gpu_init_func)(struct radeon_info *info);
25
init_polaris12(struct radeon_info * info)26 static void init_polaris12(struct radeon_info *info)
27 {
28 info->family = CHIP_POLARIS12;
29 info->gfx_level = GFX8;
30 info->family_id = AMDGPU_FAMILY_VI;
31 info->chip_external_rev = 0x64;
32 info->use_display_dcc_unaligned = false;
33 info->use_display_dcc_with_retile_blit = false;
34 info->has_graphics = true;
35 info->tcc_cache_line_size = 64;
36 info->max_render_backends = 4;
37
38 uint32_t si_tile_mode_array[] = {
39 0x00800150, 0x00800950, 0x00801150, 0x00801950, 0x00802950,
40 0x00802948, 0x00802954, 0x00802954, 0x00000144, 0x02000148,
41 0x02000150, 0x06000154, 0x06000154, 0x02400148, 0x02400150,
42 0x02400170, 0x06400154, 0x06400154, 0x0040014c, 0x0100014c,
43 0x0100015c, 0x01000174, 0x01000164, 0x01000164, 0x0040015c,
44 0x01000160, 0x01000178, 0x02c00148, 0x02c00150, 0x06c00154,
45 0x06c00154, 0x00000000
46 };
47 memcpy(info->si_tile_mode_array, si_tile_mode_array, sizeof(si_tile_mode_array));
48 info->gb_addr_config = 0x22011002;
49 }
50
init_vega10(struct radeon_info * info)51 static void init_vega10(struct radeon_info *info)
52 {
53 info->family = CHIP_VEGA10;
54 info->gfx_level = GFX9;
55 info->family_id = AMDGPU_FAMILY_AI;
56 info->chip_external_rev = 0x01;
57 info->use_display_dcc_unaligned = false;
58 info->use_display_dcc_with_retile_blit = false;
59 info->has_graphics = true;
60 info->tcc_cache_line_size = 64;
61 info->max_render_backends = 16;
62
63 info->gb_addr_config = 0x2a114042;
64 }
65
init_vega20(struct radeon_info * info)66 static void init_vega20(struct radeon_info *info)
67 {
68 info->family = CHIP_VEGA20;
69 info->gfx_level = GFX9;
70 info->family_id = AMDGPU_FAMILY_AI;
71 info->chip_external_rev = 0x30;
72 info->use_display_dcc_unaligned = false;
73 info->use_display_dcc_with_retile_blit = false;
74 info->has_graphics = true;
75 info->tcc_cache_line_size = 64;
76 info->max_render_backends = 16;
77
78 info->gb_addr_config = 0x2a114042;
79 }
80
81
init_raven(struct radeon_info * info)82 static void init_raven(struct radeon_info *info)
83 {
84 info->family = CHIP_RAVEN;
85 info->gfx_level = GFX9;
86 info->family_id = AMDGPU_FAMILY_RV;
87 info->chip_external_rev = 0x01;
88 info->use_display_dcc_unaligned = false;
89 info->use_display_dcc_with_retile_blit = true;
90 info->has_graphics = true;
91 info->tcc_cache_line_size = 64;
92 info->max_render_backends = 2;
93
94 info->gb_addr_config = 0x24000042;
95 }
96
init_raven2(struct radeon_info * info)97 static void init_raven2(struct radeon_info *info)
98 {
99 info->family = CHIP_RAVEN2;
100 info->gfx_level = GFX9;
101 info->family_id = AMDGPU_FAMILY_RV;
102 info->chip_external_rev = 0x82;
103 info->use_display_dcc_unaligned = true;
104 info->use_display_dcc_with_retile_blit = false;
105 info->has_graphics = true;
106 info->tcc_cache_line_size = 64;
107 info->max_render_backends = 1;
108
109 info->gb_addr_config = 0x26013041;
110 }
111
init_navi10(struct radeon_info * info)112 static void init_navi10(struct radeon_info *info)
113 {
114 info->family = CHIP_NAVI10;
115 info->gfx_level = GFX10;
116 info->family_id = AMDGPU_FAMILY_NV;
117 info->chip_external_rev = 3;
118 info->use_display_dcc_unaligned = false;
119 info->use_display_dcc_with_retile_blit = false;
120 info->has_graphics = true;
121 info->tcc_cache_line_size = 128;
122
123 info->gb_addr_config = 0x00100044;
124 }
125
init_navi14(struct radeon_info * info)126 static void init_navi14(struct radeon_info *info)
127 {
128 info->family = CHIP_NAVI14;
129 info->gfx_level = GFX10;
130 info->family_id = AMDGPU_FAMILY_NV;
131 info->chip_external_rev = 0x15;
132 info->use_display_dcc_unaligned = false;
133 info->use_display_dcc_with_retile_blit = false;
134 info->has_graphics = true;
135 info->tcc_cache_line_size = 128;
136
137 info->gb_addr_config = 0x00000043;
138 }
139
init_gfx103(struct radeon_info * info)140 static void init_gfx103(struct radeon_info *info)
141 {
142 info->family = CHIP_NAVI21; /* This doesn't affect tests. */
143 info->gfx_level = GFX10_3;
144 info->family_id = AMDGPU_FAMILY_NV;
145 info->chip_external_rev = 0x28;
146 info->use_display_dcc_unaligned = false;
147 info->use_display_dcc_with_retile_blit = true;
148 info->has_graphics = true;
149 info->tcc_cache_line_size = 128;
150 info->has_rbplus = true;
151 info->rbplus_allowed = true;
152
153 info->gb_addr_config = 0x00000040; /* Other fields are set by test cases. */
154 }
155
init_gfx11(struct radeon_info * info)156 static void init_gfx11(struct radeon_info *info)
157 {
158 info->family = CHIP_NAVI31;
159 info->gfx_level = GFX11;
160 info->family_id = FAMILY_NV3;
161 info->chip_external_rev = 0x01;
162 info->use_display_dcc_unaligned = false;
163 info->use_display_dcc_with_retile_blit = true;
164 info->has_graphics = true;
165 info->tcc_cache_line_size = 128;
166 info->has_rbplus = true;
167 info->rbplus_allowed = true;
168
169 info->gb_addr_config = 0x00000040; /* Other fields are set by test cases. */
170 }
171
init_gfx12(struct radeon_info * info)172 static void init_gfx12(struct radeon_info *info)
173 {
174 info->family = CHIP_GFX1200;
175 info->gfx_level = GFX12;
176 info->family_id = FAMILY_GFX12;
177 info->chip_external_rev = 0x01;
178 info->has_graphics = true;
179 info->tcc_cache_line_size = 256;
180 info->has_rbplus = true;
181 info->rbplus_allowed = true;
182
183 info->gb_addr_config = 0; /* Other fields are set by test cases. */
184 }
185
186 struct ac_fake_hw {
187 const char *name;
188 gpu_init_func init;
189 int banks_or_pkrs;
190 int pipes;
191 int se;
192 int rb_per_se;
193 };
194
195 static struct ac_fake_hw ac_fake_hw_db[] = {
196 {"polaris12", init_polaris12},
197 {"vega10", init_vega10, 4, 2, 2, 2},
198 {"vega10_diff_bank", init_vega10, 3, 2, 2, 2},
199 {"vega10_diff_rb", init_vega10, 4, 2, 2, 0},
200 {"vega10_diff_pipe", init_vega10, 4, 0, 2, 2},
201 {"vega10_diff_se", init_vega10, 4, 2, 1, 2},
202 {"vega20", init_vega20, 4, 2, 2, 2},
203 {"raven", init_raven, 0, 2, 0, 1},
204 {"raven2", init_raven2, 3, 1, 0, 1},
205 /* Just test a bunch of different numbers. (packers, pipes) */
206 {"navi10", init_navi10, 0, 4},
207 {"navi10_diff_pipe", init_navi10, 0, 3},
208 {"navi10_diff_pkr", init_navi10, 1, 4},
209 {"navi14", init_navi14, 1, 3},
210 {"gfx103_16pipe", init_gfx103, 4, 4},
211 {"gfx103_16pipe_8pkr", init_gfx103, 3, 4},
212 {"gfx103_8pipe", init_gfx103, 3, 3},
213 {"gfx103_4pipe", init_gfx103, 2, 2},
214 {"gfx103_4pipe_2pkr", init_gfx103, 1, 2},
215 {"gfx103_4pipe_1pkr", init_gfx103, 0, 2},
216 {"gfx103_2pipe_1pkr", init_gfx103, 0, 1},
217 {"gfx11_32pipe", init_gfx11, 5, 5},
218 {"gfx11_16pipe", init_gfx11, 4, 4},
219 {"gfx11_8pipe", init_gfx11, 3, 3},
220 {"gfx11_4pipe", init_gfx11, 2, 2},
221 {"gfx11_4pipe_2pkr", init_gfx11, 1, 2},
222 {"gfx11_4pipe_1pkr", init_gfx11, 0, 2},
223 {"gfx11_2pipe_1pkr", init_gfx11, 0, 1},
224 {"gfx12_16pipe", init_gfx12, 4, 4},
225 };
226
get_radeon_info(struct radeon_info * info,struct ac_fake_hw * hw)227 static void get_radeon_info(struct radeon_info *info, struct ac_fake_hw *hw)
228 {
229 if (info->drm_major != 3) {
230 info->drm_major = 3;
231 info->drm_minor = 30;
232 }
233
234 hw->init(info);
235
236 switch(info->gfx_level) {
237 case GFX9:
238 info->gb_addr_config = (info->gb_addr_config &
239 C_0098F8_NUM_PIPES &
240 C_0098F8_NUM_BANKS &
241 C_0098F8_NUM_SHADER_ENGINES_GFX9 &
242 C_0098F8_NUM_RB_PER_SE) |
243 S_0098F8_NUM_PIPES(hw->pipes) |
244 S_0098F8_NUM_BANKS(hw->banks_or_pkrs) |
245 S_0098F8_NUM_SHADER_ENGINES_GFX9(hw->se) |
246 S_0098F8_NUM_RB_PER_SE(hw->rb_per_se);
247 break;
248 case GFX10:
249 case GFX10_3:
250 case GFX11:
251 case GFX12:
252 info->gb_addr_config = (info->gb_addr_config &
253 C_0098F8_NUM_PIPES &
254 C_0098F8_NUM_PKRS) |
255 S_0098F8_NUM_PIPES(hw->pipes) |
256 S_0098F8_NUM_PKRS(hw->banks_or_pkrs);
257 /* 1 packer implies 1 RB except gfx10 where the field is ignored. */
258 info->max_render_backends = info->gfx_level == GFX10 || hw->banks_or_pkrs ? 2 : 1;
259 break;
260 default:
261 break;
262 }
263 }
264
265 #endif
266