1 /* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com> 3 * Copyright 2010 Marek Olšák <maraeo@gmail.com> 4 * 5 * SPDX-License-Identifier: MIT 6 */ 7 8 #ifndef AMD_FAMILY_H 9 #define AMD_FAMILY_H 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 struct radeon_info; 16 17 enum radeon_family 18 { 19 CHIP_UNKNOWN = 0, 20 /* R3xx-based cores. (GFX2) */ 21 CHIP_R300, 22 CHIP_R350, 23 CHIP_RV350, 24 CHIP_RV370, 25 CHIP_RV380, 26 CHIP_RS400, 27 CHIP_RC410, 28 CHIP_RS480, 29 /* R4xx-based cores. (GFX2) */ 30 CHIP_R420, 31 CHIP_R423, 32 CHIP_R430, 33 CHIP_R480, 34 CHIP_R481, 35 CHIP_RV410, 36 CHIP_RS600, 37 CHIP_RS690, 38 CHIP_RS740, 39 /* R5xx-based cores. (GFX2) */ 40 CHIP_RV515, 41 CHIP_R520, 42 CHIP_RV530, 43 CHIP_R580, 44 CHIP_RV560, 45 CHIP_RV570, 46 /* GFX3 (R6xx) */ 47 CHIP_R600, 48 CHIP_RV610, 49 CHIP_RV630, 50 CHIP_RV670, 51 CHIP_RV620, 52 CHIP_RV635, 53 CHIP_RS780, 54 CHIP_RS880, 55 /* GFX3 (R7xx) */ 56 CHIP_RV770, 57 CHIP_RV730, 58 CHIP_RV710, 59 CHIP_RV740, 60 /* GFX4 (Evergreen) */ 61 CHIP_CEDAR, 62 CHIP_REDWOOD, 63 CHIP_JUNIPER, 64 CHIP_CYPRESS, 65 CHIP_HEMLOCK, 66 CHIP_PALM, 67 CHIP_SUMO, 68 CHIP_SUMO2, 69 CHIP_BARTS, 70 CHIP_TURKS, 71 CHIP_CAICOS, 72 /* GFX5 (Northern Islands) */ 73 CHIP_CAYMAN, 74 CHIP_ARUBA, 75 /* GFX6 (Southern Islands) */ 76 CHIP_TAHITI, 77 CHIP_PITCAIRN, 78 CHIP_VERDE, 79 CHIP_OLAND, 80 CHIP_HAINAN, 81 /* GFX7 (Sea Islands) */ 82 CHIP_BONAIRE, 83 CHIP_KAVERI, 84 CHIP_KABINI, 85 CHIP_HAWAII, /* Radeon 290, 390 */ 86 /* GFX8 (Volcanic Islands & Polaris) */ 87 CHIP_TONGA, /* Radeon 285, 380 */ 88 CHIP_ICELAND, 89 CHIP_CARRIZO, 90 CHIP_FIJI, /* Radeon Fury */ 91 CHIP_STONEY, 92 CHIP_POLARIS10, /* Radeon 470, 480, 570, 580, 590 */ 93 CHIP_POLARIS11, /* Radeon 460, 560 */ 94 CHIP_POLARIS12, /* Radeon 540, 550 */ 95 CHIP_VEGAM, 96 /* GFX9 (Vega) */ 97 CHIP_VEGA10, /* Vega 56, 64 */ 98 CHIP_VEGA12, 99 CHIP_VEGA20, /* Radeon VII, MI50 */ 100 CHIP_RAVEN, /* Ryzen 2000, 3000 */ 101 CHIP_RAVEN2, /* Ryzen 2200U, 3200U */ 102 CHIP_RENOIR, /* Ryzen 4000, 5000 */ 103 CHIP_MI100, 104 CHIP_MI200, 105 CHIP_GFX940, 106 /* GFX10.1 (RDNA 1) */ 107 CHIP_NAVI10, /* Radeon 5600, 5700 */ 108 CHIP_NAVI12, /* Radeon Pro 5600M */ 109 CHIP_NAVI14, /* Radeon 5300, 5500 */ 110 /* GFX10.3 (RDNA 2) */ 111 CHIP_NAVI21, /* Radeon 6800, 6900 (formerly "Sienna Cichlid") */ 112 CHIP_NAVI22, /* Radeon 6700 (formerly "Navy Flounder") */ 113 CHIP_VANGOGH, /* Steam Deck */ 114 CHIP_NAVI23, /* Radeon 6600 (formerly "Dimgrey Cavefish") */ 115 CHIP_NAVI24, /* Radeon 6400, 6500 (formerly "Beige Goby") */ 116 CHIP_REMBRANDT, /* Ryzen 6000 (formerly "Yellow Carp") */ 117 CHIP_RAPHAEL_MENDOCINO, /* Ryzen 7000(X), Ryzen 7045, Ryzen 7020 */ 118 /* GFX11 (RDNA 3) */ 119 CHIP_NAVI31, /* Radeon 7900 */ 120 CHIP_NAVI32, /* Radeon 7800, 7700 */ 121 CHIP_NAVI33, /* Radeon 7600, 7700S (mobile) */ 122 CHIP_PHOENIX, /* Ryzen Z1 Extreme, Ryzen 7040, Ryzen 8040 */ 123 CHIP_PHOENIX2, /* Ryzen Z1, Ryzen 8040 */ 124 /* GFX11.5 (RDNA 3.5) */ 125 CHIP_GFX1150, 126 CHIP_GFX1151, 127 CHIP_GFX1152, 128 CHIP_GFX1153, 129 /* GFX12 (RDNA 4) */ 130 CHIP_GFX1200, 131 CHIP_GFX1201, 132 CHIP_LAST, 133 }; 134 135 enum amd_gfx_level 136 { 137 CLASS_UNKNOWN = 0, 138 R300, 139 R400, 140 R500, 141 R600, 142 R700, 143 EVERGREEN, 144 CAYMAN, 145 GFX6, 146 GFX7, 147 GFX8, 148 GFX9, 149 GFX10, 150 GFX10_3, 151 GFX11, 152 GFX11_5, 153 GFX12, 154 155 NUM_GFX_VERSIONS, 156 }; 157 158 enum amd_ip_type 159 { 160 AMD_IP_GFX = 0, 161 AMD_IP_COMPUTE, 162 AMD_IP_SDMA, 163 AMD_IP_UVD, 164 AMD_IP_VCE, 165 AMD_IP_UVD_ENC, 166 AMD_IP_VCN_DEC, 167 AMD_IP_VCN_ENC, 168 AMD_IP_VCN_UNIFIED = AMD_IP_VCN_ENC, 169 AMD_IP_VCN_JPEG, 170 AMD_IP_VPE, 171 AMD_NUM_IP_TYPES, 172 }; 173 174 enum amd_vram_type { 175 AMD_VRAM_TYPE_UNKNOWN = 0, 176 AMD_VRAM_TYPE_GDDR1, 177 AMD_VRAM_TYPE_DDR2, 178 AMD_VRAM_TYPE_GDDR3, 179 AMD_VRAM_TYPE_GDDR4, 180 AMD_VRAM_TYPE_GDDR5, 181 AMD_VRAM_TYPE_HBM, 182 AMD_VRAM_TYPE_DDR3, 183 AMD_VRAM_TYPE_DDR4, 184 AMD_VRAM_TYPE_GDDR6, 185 AMD_VRAM_TYPE_DDR5, 186 AMD_VRAM_TYPE_LPDDR4, 187 AMD_VRAM_TYPE_LPDDR5, 188 }; 189 190 enum vcn_version{ 191 VCN_UNKNOWN, 192 VCN_1_0_0, 193 VCN_1_0_1, 194 195 VCN_2_0_0, 196 VCN_2_0_2, 197 VCN_2_0_3, 198 VCN_2_2_0, 199 VCN_2_5_0, 200 VCN_2_6_0, 201 202 VCN_3_0_0, 203 VCN_3_0_2, 204 VCN_3_0_16, 205 VCN_3_0_33, 206 VCN_3_1_1, 207 VCN_3_1_2, 208 209 VCN_4_0_0, 210 VCN_4_0_2, 211 VCN_4_0_3, 212 VCN_4_0_4, 213 VCN_4_0_5, 214 VCN_4_0_6, 215 216 VCN_5_0_0, 217 VCN_5_0_1, 218 }; 219 220 #define SDMA_VERSION_VALUE(major, minor) (((major) << 8) | (minor)) 221 222 enum sdma_version { 223 SDMA_UNKNOWN = 0, 224 /* GFX6 */ 225 SDMA_1_0 = SDMA_VERSION_VALUE(1, 0), 226 227 /* GFX7 */ 228 SDMA_2_0 = SDMA_VERSION_VALUE(2, 0), 229 230 /* GFX8 */ 231 SDMA_2_4 = SDMA_VERSION_VALUE(2, 4), 232 SDMA_3_0 = SDMA_VERSION_VALUE(3, 0), 233 SDMA_3_1 = SDMA_VERSION_VALUE(3, 1), 234 235 /* GFX9 */ 236 SDMA_4_0 = SDMA_VERSION_VALUE(4, 0), 237 SDMA_4_1 = SDMA_VERSION_VALUE(4, 1), 238 SDMA_4_2 = SDMA_VERSION_VALUE(4, 2), 239 SDMA_4_4 = SDMA_VERSION_VALUE(4, 4), 240 241 /* GFX10 */ 242 SDMA_5_0 = SDMA_VERSION_VALUE(5, 0), 243 244 /* GFX10.3 */ 245 SDMA_5_2 = SDMA_VERSION_VALUE(5, 2), 246 247 /* GFX11 */ 248 SDMA_6_0 = SDMA_VERSION_VALUE(6, 0), 249 250 /* GFX11.5 */ 251 SDMA_6_1 = SDMA_VERSION_VALUE(6, 1), 252 253 /* GFX12 */ 254 SDMA_7_0 = SDMA_VERSION_VALUE(7, 0), 255 }; 256 257 const char *ac_get_family_name(enum radeon_family family); 258 enum amd_gfx_level ac_get_gfx_level(enum radeon_family family); 259 const char *ac_get_llvm_processor_name(enum radeon_family family); 260 const char *ac_get_ip_type_string(const struct radeon_info *info, enum amd_ip_type ip_type); 261 262 #ifdef __cplusplus 263 } 264 #endif 265 266 #endif 267