1 /* 2 * Copyright © 2024 Valve Corporation 3 * 4 * SPDX-License-Identifier: MIT 5 */ 6 7 8 #ifndef AC_NIR_HELPERS_H 9 #define AC_NIR_HELPERS_H 10 11 #include "ac_hw_stage.h" 12 #include "ac_shader_args.h" 13 #include "ac_shader_util.h" 14 #include "nir.h" 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #define AC_NIR_STORE_IO(b, store_val, const_offset, write_mask, hi_16bit, func, ...) \ 21 do { \ 22 if ((store_val)->bit_size >= 32) { \ 23 const unsigned store_write_mask = (write_mask); \ 24 const unsigned store_const_offset = (const_offset); \ 25 func((b), (store_val), __VA_ARGS__); \ 26 } else { \ 27 u_foreach_bit(c, (write_mask)) { \ 28 const unsigned store_write_mask = 1; \ 29 const unsigned store_const_offset = (const_offset) + c * 4 + ((hi_16bit) ? 2 : 0); \ 30 nir_def *store_component = nir_channel(b, (store_val), c); \ 31 func((b), store_component, __VA_ARGS__); \ 32 } \ 33 } \ 34 } while (0) 35 36 #define AC_NIR_LOAD_IO(load, b, num_components, bit_size, hi_16bit, func, ...) \ 37 do { \ 38 const unsigned load_bit_size = MAX2(32, (bit_size)); \ 39 (load) = func((b), (num_components), load_bit_size, __VA_ARGS__); \ 40 if ((bit_size) < load_bit_size) { \ 41 if ((hi_16bit)) { \ 42 (load) = nir_unpack_32_2x16_split_y(b, load); \ 43 } else { \ 44 (load) = nir_unpack_32_2x16_split_x(b, load); \ 45 } \ 46 } \ 47 } while (0) 48 49 typedef struct 50 { 51 /* GS output stream index, 2 bit per component */ 52 uint8_t stream; 53 /* Bitmask of components used: 4 bits per slot, 1 bit per component. */ 54 uint8_t components_mask : 4; 55 /* Bitmask of components that are used as varying, 1 bit per component. */ 56 uint8_t as_varying_mask : 4; 57 /* Bitmask of components that are used as sysval, 1 bit per component. */ 58 uint8_t as_sysval_mask : 4; 59 } ac_nir_prerast_per_output_info; 60 61 typedef struct 62 { 63 nir_def *outputs[VARYING_SLOT_MAX][4]; 64 nir_def *outputs_16bit_lo[16][4]; 65 nir_def *outputs_16bit_hi[16][4]; 66 67 nir_alu_type types[VARYING_SLOT_MAX][4]; 68 nir_alu_type types_16bit_lo[16][4]; 69 nir_alu_type types_16bit_hi[16][4]; 70 71 ac_nir_prerast_per_output_info infos[VARYING_SLOT_MAX]; 72 ac_nir_prerast_per_output_info infos_16bit_lo[16]; 73 ac_nir_prerast_per_output_info infos_16bit_hi[16]; 74 } ac_nir_prerast_out; 75 76 /* Maps I/O semantics to the actual location used by the lowering pass. */ 77 typedef unsigned (*ac_nir_map_io_driver_location)(unsigned semantic); 78 79 /* Forward declaration of nir_builder so we don't have to include nir_builder.h here */ 80 struct nir_builder; 81 typedef struct nir_builder nir_builder; 82 83 struct nir_xfb_info; 84 typedef struct nir_xfb_info nir_xfb_info; 85 86 /* Executed by ac_nir_cull when the current primitive is accepted. */ 87 typedef void (*ac_nir_cull_accepted)(nir_builder *b, void *state); 88 89 nir_def * 90 ac_nir_unpack_value(nir_builder *b, nir_def *value, unsigned rshift, unsigned bitwidth); 91 92 void 93 ac_nir_store_var_components(nir_builder *b, nir_variable *var, nir_def *value, 94 unsigned component, unsigned writemask); 95 96 void 97 ac_nir_gather_prerast_store_output_info(nir_builder *b, 98 nir_intrinsic_instr *intrin, 99 ac_nir_prerast_out *out); 100 101 void 102 ac_nir_export_primitive(nir_builder *b, nir_def *prim, nir_def *row); 103 104 void 105 ac_nir_export_position(nir_builder *b, 106 enum amd_gfx_level gfx_level, 107 uint32_t clip_cull_mask, 108 bool no_param_export, 109 bool force_vrs, 110 bool done, 111 uint64_t outputs_written, 112 ac_nir_prerast_out *out, 113 nir_def *row); 114 115 void 116 ac_nir_export_parameters(nir_builder *b, 117 const uint8_t *param_offsets, 118 uint64_t outputs_written, 119 uint16_t outputs_written_16bit, 120 ac_nir_prerast_out *out); 121 122 void 123 ac_nir_store_parameters_to_attr_ring(nir_builder *b, 124 const uint8_t *param_offsets, 125 const uint64_t outputs_written, 126 const uint16_t outputs_written_16bit, 127 ac_nir_prerast_out *out, 128 nir_def *export_tid, nir_def *num_export_threads); 129 130 nir_def * 131 ac_nir_calc_io_off(nir_builder *b, 132 nir_intrinsic_instr *intrin, 133 nir_def *base_stride, 134 unsigned component_stride, 135 unsigned mapped_location); 136 137 unsigned 138 ac_nir_map_io_location(unsigned location, 139 uint64_t mask, 140 ac_nir_map_io_driver_location map_io); 141 142 nir_def * 143 ac_nir_cull_primitive(nir_builder *b, 144 nir_def *initially_accepted, 145 nir_def *pos[3][4], 146 unsigned num_vertices, 147 ac_nir_cull_accepted accept_func, 148 void *state); 149 150 void 151 ac_nir_sleep(nir_builder *b, unsigned num_cycles); 152 153 nir_def * 154 ac_average_samples(nir_builder *b, nir_def **samples, unsigned num_samples); 155 156 void 157 ac_optimization_barrier_vgpr_array(const struct radeon_info *info, nir_builder *b, 158 nir_def **array, unsigned num_elements, 159 unsigned num_components); 160 161 nir_def * 162 ac_get_global_ids(nir_builder *b, unsigned num_components, unsigned bit_size); 163 164 void 165 ac_nir_emit_legacy_streamout(nir_builder *b, unsigned stream, nir_xfb_info *info, ac_nir_prerast_out *out); 166 167 bool 168 ac_nir_gs_shader_query(nir_builder *b, 169 bool has_gen_prim_query, 170 bool has_gs_invocations_query, 171 bool has_gs_primitives_query, 172 unsigned num_vertices_per_primitive, 173 unsigned wave_size, 174 nir_def *vertex_count[4], 175 nir_def *primitive_count[4]); 176 177 nir_def * 178 ac_nir_pack_ngg_prim_exp_arg(nir_builder *b, unsigned num_vertices_per_primitives, 179 nir_def *vertex_indices[3], nir_def *is_null_prim, 180 enum amd_gfx_level gfx_level); 181 182 #ifdef __cplusplus 183 } 184 #endif 185 186 #endif /* AC_NIR_HELPERS_H */ 187