1 /* 2 * Copyright 2024 Advanced Micro Devices, Inc. 3 * 4 * SPDX-License-Identifier: MIT 5 */ 6 #ifndef AMDGPU_VIRTIO_H 7 #define AMDGPU_VIRTIO_H 8 9 struct amdvgpu_bo; 10 struct amdvgpu_device; 11 struct amdvgpu_context; 12 typedef struct amdvgpu_device* amdvgpu_device_handle; 13 typedef struct amdvgpu_bo* amdvgpu_bo_handle; 14 15 struct amdvgpu_bo_import_result { 16 amdvgpu_bo_handle buf_handle; 17 uint64_t alloc_size; 18 }; 19 20 int amdvgpu_device_initialize(int fd, uint32_t *drm_major, uint32_t *drm_minor, 21 amdvgpu_device_handle* dev); 22 int amdvgpu_device_deinitialize(amdvgpu_device_handle dev); 23 int amdvgpu_bo_va_op_raw(amdvgpu_device_handle dev, 24 uint32_t res_id, 25 uint64_t offset, 26 uint64_t size, 27 uint64_t addr, 28 uint64_t flags, 29 uint32_t ops); 30 int amdvgpu_bo_import(amdvgpu_device_handle dev, 31 enum amdgpu_bo_handle_type type, 32 uint32_t handle, 33 struct amdvgpu_bo_import_result *result); 34 int amdvgpu_bo_export(amdvgpu_device_handle dev, amdvgpu_bo_handle bo, 35 enum amdgpu_bo_handle_type type, 36 uint32_t *shared_handle); 37 int amdvgpu_bo_cpu_map(amdvgpu_device_handle dev, amdvgpu_bo_handle bo_handle, void **cpu); 38 int amdvgpu_bo_cpu_unmap(amdvgpu_device_handle dev, amdvgpu_bo_handle bo); 39 int amdvgpu_bo_alloc(amdvgpu_device_handle dev, 40 struct amdgpu_bo_alloc_request *request, 41 amdvgpu_bo_handle *bo); 42 int amdvgpu_bo_free(amdvgpu_device_handle dev, struct amdvgpu_bo *bo); 43 int amdvgpu_bo_wait_for_idle(amdvgpu_device_handle dev, 44 amdvgpu_bo_handle bo, 45 uint64_t abs_timeout_ns); 46 int 47 amdvgpu_bo_set_metadata(amdvgpu_device_handle dev, uint32_t res_id, 48 struct amdgpu_bo_metadata *info); 49 int amdvgpu_query_info(amdvgpu_device_handle dev, struct drm_amdgpu_info *info); 50 int amdvgpu_bo_query_info(amdvgpu_device_handle dev, uint32_t res_id, struct amdgpu_bo_info *info); 51 int amdvgpu_cs_ctx_create2(amdvgpu_device_handle dev, int32_t priority, uint32_t *ctx_virtio); 52 int amdvgpu_cs_ctx_free(amdvgpu_device_handle dev, uint32_t ctx); 53 int amdvgpu_cs_ctx_stable_pstate(amdvgpu_device_handle dev, 54 uint32_t ctx, 55 uint32_t op, 56 uint32_t flags, 57 uint32_t *out_flags); 58 int amdvgpu_cs_query_reset_state2(amdvgpu_device_handle dev, 59 uint32_t ctx, 60 uint64_t *flags); 61 int 62 amdvgpu_va_range_alloc(amdvgpu_device_handle dev, 63 enum amdgpu_gpu_va_range va_range_type, 64 uint64_t size, 65 uint64_t va_base_alignment, 66 uint64_t va_base_required, 67 uint64_t *va_base_allocated, 68 amdgpu_va_handle *va_range_handle, 69 uint64_t flags); 70 int amdvgpu_cs_query_fence_status(amdvgpu_device_handle dev, 71 uint32_t ctx, 72 uint32_t ip_type, 73 uint32_t ip_instance, uint32_t ring, 74 uint64_t fence_seq_no, 75 uint64_t timeout_ns, uint64_t flags, 76 uint32_t *expired); 77 int 78 amdvgpu_device_get_fd(amdvgpu_device_handle dev); 79 const char * 80 amdvgpu_get_marketing_name(amdvgpu_device_handle dev); 81 int 82 amdvgpu_cs_submit_raw2(amdvgpu_device_handle dev, uint32_t ctx_id, 83 uint32_t bo_list_handle, 84 int num_chunks, struct drm_amdgpu_cs_chunk *chunks, 85 uint64_t *seqno); 86 int amdvgpu_vm_reserve_vmid(amdvgpu_device_handle dev, int reserve); 87 int 88 amdvgpu_query_sw_info(amdvgpu_device_handle dev, enum amdgpu_sw_info info, void *value); 89 90 #endif 91