1 /* 2 * Copyright © 2016 Red Hat. 3 * Copyright © 2016 Bas Nieuwenhuizen 4 * 5 * based in part on anv driver which is: 6 * Copyright © 2015 Intel Corporation 7 * 8 * SPDX-License-Identifier: MIT 9 */ 10 11 #ifndef RADV_CONSTANTS_H 12 #define RADV_CONSTANTS_H 13 14 #define ATI_VENDOR_ID 0x1002 15 #ifdef HAVE_AMDGPU_VIRTIO 16 #define VIRTGPU_PCI_VENDOR_ID 0x1af4 17 #endif 18 19 #define MAX_VBS 32 20 #define MAX_VERTEX_ATTRIBS 32 21 #define MAX_RTS 8 22 #define MAX_VIEWPORTS 16 23 #define MAX_SCISSORS 16 24 #define MAX_DISCARD_RECTANGLES 4 25 #define MAX_SAMPLE_LOCATIONS 32 26 #define MAX_PUSH_CONSTANTS_SIZE 256 27 #define MAX_PUSH_DESCRIPTORS 32 28 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16 29 #define MAX_DYNAMIC_STORAGE_BUFFERS 8 30 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS) 31 #define MAX_SAMPLES_LOG2 4 32 #define NUM_META_FS_KEYS 12 33 #define MAX_VIEWS 8 34 #define MAX_SO_STREAMS 4 35 #define MAX_SO_BUFFERS 4 36 #define MAX_SO_OUTPUTS 128 37 #define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024) 38 #define MAX_INLINE_UNIFORM_BLOCK_COUNT 64 39 #define MAX_BIND_POINTS 3 /* compute + graphics + raytracing */ 40 41 #define NUM_DEPTH_CLEAR_PIPELINES 2 42 #define NUM_DEPTH_DECOMPRESS_PIPELINES 3 43 #define MAX_FRAMEBUFFER_WIDTH (1u << 14) 44 #define MAX_FRAMEBUFFER_HEIGHT (1u << 14) 45 46 /* 47 * This is the point we switch from using CP to compute shader 48 * for certain buffer operations. 49 */ 50 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096 51 52 #define RADV_BUFFER_UPDATE_THRESHOLD 1024 53 54 /* descriptor index into scratch ring offsets */ 55 #define RING_SCRATCH 0 56 #define RING_ESGS_VS 1 57 #define RING_ESGS_GS 2 58 #define RING_GSVS_VS 3 59 #define RING_GSVS_GS 4 60 #define RING_HS_TESS_FACTOR 5 61 #define RING_HS_TESS_OFFCHIP 6 62 #define RING_TS_DRAW 7 63 #define RING_TS_PAYLOAD 8 64 #define RING_MS_SCRATCH 9 65 #define RING_PS_ATTR 10 66 #define RING_PS_SAMPLE_POSITIONS 11 67 68 #define SI_GS_PER_ES 128 69 70 /* max number of descriptor sets */ 71 #define MAX_SETS 32 72 73 /* Make sure everything is addressable by a signed 32-bit int, and 74 * our largest descriptors are 96 bytes. 75 */ 76 #define RADV_MAX_PER_SET_DESCRIPTORS ((1ull << 31) / 96) 77 78 /* Our buffer size fields allow only 2**32 - 1. We round that down to a multiple 79 * of 4 bytes so we can align buffer sizes up. 80 */ 81 #define RADV_MAX_MEMORY_ALLOCATION_SIZE 0xFFFFFFFCull 82 83 /* Number of entries in the mesh shader scratch ring. 84 * This depends on VGT_GS_MAX_WAVE_ID which is set by the kernel 85 * and is impossible to query. We leave it on its maximum value 86 * because real applications are unlikely to use it. 87 * 88 * The maximum ID on GFX10.3 is 2047 (0x7ff), so we need 2048 entries. 89 */ 90 #define RADV_MESH_SCRATCH_NUM_ENTRIES 2048 91 92 /* Size of each entry in the mesh shader scratch ring. 93 * We must ensure that the absolute maximum mesh shader output fits here. 94 * 95 * Mesh shaders can create up to 256 vertices/primitives per workgroup, 96 * and up to the following amount of outputs: 97 * - 32 parameters 98 * - 4 positions (clip/cull distance, etc.) 99 * - 4 per-primitive built-in outputs (layer, view index, prim id, VRS rate) 100 * - primitive indices which are always kept in LDS 101 * That is a total of 32+4+4=40 output slots x 16 bytes per slot x 256 = 160K bytes. 102 */ 103 #define RADV_MESH_SCRATCH_ENTRY_BYTES (160 * 1024) 104 105 /* Number of invocations in each subgroup. */ 106 #define RADV_SUBGROUP_SIZE 64 107 108 /* The spec requires this to be 32. */ 109 #define RADV_RT_HANDLE_SIZE 32 110 111 #define RADV_MAX_HIT_ATTRIB_SIZE 32 112 #define RADV_MAX_HIT_ATTRIB_DWORDS (RADV_MAX_HIT_ATTRIB_SIZE / 4) 113 114 #define RADV_SHADER_ALLOC_ALIGNMENT 256 115 #define RADV_SHADER_ALLOC_MIN_ARENA_SIZE (256 * 1024) 116 /* 256 KiB << 5 = 8 MiB */ 117 #define RADV_SHADER_ALLOC_MAX_ARENA_SIZE_SHIFT 5u 118 #define RADV_SHADER_ALLOC_MIN_SIZE_CLASS 8 119 #define RADV_SHADER_ALLOC_MAX_SIZE_CLASS 15 120 #define RADV_SHADER_ALLOC_NUM_FREE_LISTS (RADV_SHADER_ALLOC_MAX_SIZE_CLASS - RADV_SHADER_ALLOC_MIN_SIZE_CLASS + 1) 121 122 #define PERF_CTR_MAX_PASSES 512 123 #define PERF_CTR_BO_PASS_OFFSET 16 124 #define PERF_CTR_BO_LOCK_OFFSET 0 125 #define PERF_CTR_BO_FENCE_OFFSET 8 126 127 /* The maximum number of in-flight uploads (radv_shader_dma_submission) when asynchronous shader 128 * upload is used. 129 */ 130 #define RADV_SHADER_UPLOAD_CS_COUNT 32 131 132 /* Shader GDS counters: 133 * offset 0| 4| 8|12 - reserved for NGG streamout counters 134 * offset 16 - number of primitives generated by geometry shader invocations 135 * offset 20 - number of geometry shader invocations 136 * offset 24|28|32|36 - generated primitive counter for stream 0|1|2|3 137 * offset 40|44|48|52 - written primitive counter for stream 0|1|2|3 138 * 139 * Mesh shader GDS counters: 140 * offset 56 - number of mesh shader invocations 141 * offset 60 - number of mesh shader generated primitives 142 * 143 * Task shader GDS counter: 144 * offset 64 - number of task shader invocations 145 */ 146 #define RADV_SHADER_QUERY_GS_PRIM_EMIT_OFFSET 16 147 #define RADV_SHADER_QUERY_GS_INVOCATION_OFFSET 20 148 #define RADV_SHADER_QUERY_PRIM_GEN_OFFSET(stream) (24 + stream * 4) 149 #define RADV_SHADER_QUERY_PRIM_XFB_OFFSET(stream) (40 + stream * 4) 150 #define RADV_SHADER_QUERY_MS_INVOCATION_OFFSET 56 151 #define RADV_SHADER_QUERY_MS_PRIM_GEN_OFFSET 60 152 #define RADV_SHADER_QUERY_TS_INVOCATION_OFFSET 64 153 154 /* Number of samples for line smooth lowering (hw requirement). */ 155 #define RADV_NUM_SMOOTH_AA_SAMPLES 4 156 157 /* Size of the temporary buffer allocated for transfer queue copy command workarounds. 158 * The size is chosen so that it can fit two lines of (1 << 14) blocks at 16 bpp. 159 */ 160 #define RADV_SDMA_TRANSFER_TEMP_BYTES (2 * (1 << 14) * 16) 161 162 #define RADV_VERT_ATTRIB_MAX MAX2(VERT_ATTRIB_MAX, VERT_ATTRIB_GENERIC0 + MAX_VERTEX_ATTRIBS) 163 164 #endif /* RADV_CONSTANTS_H */ 165