1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * SPDX-License-Identifier: MIT
9 */
10
11 #ifndef RADV_PHYSICAL_DEVICE_H
12 #define RADV_PHYSICAL_DEVICE_H
13
14 #include "ac_gpu_info.h"
15 #include "ac_perfcounter.h"
16
17 #include "radv_instance.h"
18 #include "radv_queue.h"
19 #include "radv_radeon_winsys.h"
20 #include "ac_vcn_enc.h"
21 #include "wsi_common.h"
22
23 #include "nir.h"
24
25 #include "vk_physical_device.h"
26
27 #ifndef _WIN32
28 #include <amdgpu.h>
29 #include <xf86drm.h>
30 #endif
31
32 struct radv_binning_settings {
33 unsigned context_states_per_bin; /* allowed range: [1, 6] */
34 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
35 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
36 };
37
38 struct radv_physical_device_cache_key {
39 enum radeon_family family;
40 uint32_t ptr_size;
41
42 uint32_t conformant_trunc_coord : 1;
43 uint32_t clear_lds : 1;
44 uint32_t cs_wave32 : 1;
45 uint32_t disable_aniso_single_level : 1;
46 uint32_t disable_shrink_image_store : 1;
47 uint32_t disable_sinking_load_input_fs : 1;
48 uint32_t emulate_rt : 1;
49 uint32_t ge_wave32 : 1;
50 uint32_t invariant_geom : 1;
51 uint32_t no_fmask : 1;
52 uint32_t no_ngg_gs : 1;
53 uint32_t no_rt : 1;
54 uint32_t ps_wave32 : 1;
55 uint32_t rt_wave64 : 1;
56 uint32_t split_fma : 1;
57 uint32_t ssbo_non_uniform : 1;
58 uint32_t tex_non_uniform : 1;
59 uint32_t lower_terminate_to_discard : 1;
60 uint32_t use_llvm : 1;
61 uint32_t use_ngg : 1;
62 uint32_t use_ngg_culling : 1;
63 };
64
65 enum radv_video_enc_hw_ver {
66 RADV_VIDEO_ENC_HW_1_2,
67 RADV_VIDEO_ENC_HW_2,
68 RADV_VIDEO_ENC_HW_3,
69 RADV_VIDEO_ENC_HW_4,
70 };
71
72 struct radv_physical_device {
73 struct vk_physical_device vk;
74
75 struct radeon_winsys *ws;
76 struct radeon_info info;
77 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
78 char marketing_name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
79 uint8_t driver_uuid[VK_UUID_SIZE];
80 uint8_t device_uuid[VK_UUID_SIZE];
81 uint8_t cache_uuid[VK_UUID_SIZE];
82
83 struct ac_addrlib *addrlib;
84
85 int local_fd;
86 int master_fd;
87 struct wsi_device wsi_device;
88
89 /* Whether DCC should be enabled for MSAA textures. */
90 bool dcc_msaa_allowed;
91
92 /* Whether to enable FMASK compression for MSAA textures (GFX6-GFX10.3) */
93 bool use_fmask;
94
95 /* Whether to enable NGG. */
96 bool use_ngg;
97
98 /* Whether to enable NGG culling. */
99 bool use_ngg_culling;
100
101 /* Whether to enable NGG streamout. */
102 bool use_ngg_streamout;
103
104 /* Whether to emulate the number of primitives generated by GS. */
105 bool emulate_ngg_gs_query_pipeline_stat;
106
107 /* Whether to use GS_FAST_LAUNCH(2) for mesh shaders. */
108 bool mesh_fast_launch_2;
109
110 /* Whether to emulate mesh/task shader queries. */
111 bool emulate_mesh_shader_queries;
112
113 /* Number of threads per wave. */
114 uint8_t ps_wave_size;
115 uint8_t cs_wave_size;
116 uint8_t ge_wave_size;
117 uint8_t rt_wave_size;
118
119 /* Maximum compute shared memory size. */
120 uint32_t max_shared_size;
121
122 /* Whether to use the LLVM compiler backend */
123 bool use_llvm;
124
125 /* Whether to emulate ETC2 image support on HW without support. */
126 bool emulate_etc2;
127
128 /* Whether to emulate ASTC image support on HW without support. */
129 bool emulate_astc;
130
131 VkPhysicalDeviceMemoryProperties memory_properties;
132 enum radeon_bo_domain memory_domains[VK_MAX_MEMORY_TYPES];
133 enum radeon_bo_flag memory_flags[VK_MAX_MEMORY_TYPES];
134 unsigned heaps;
135
136 /* Bitmask of memory types that use the 32-bit address space. */
137 uint32_t memory_types_32bit;
138
139 #ifndef _WIN32
140 int available_nodes;
141 drmPciBusInfo bus_info;
142
143 dev_t primary_devid;
144 dev_t render_devid;
145 #endif
146
147 nir_shader_compiler_options nir_options[MESA_VULKAN_SHADER_STAGES];
148
149 enum radv_queue_family vk_queue_to_radv[RADV_MAX_QUEUE_FAMILIES];
150 uint32_t num_queues;
151
152 uint32_t gs_table_depth;
153
154 struct ac_hs_info hs;
155 struct ac_task_info task_info;
156
157 struct radv_binning_settings binning_settings;
158
159 /* Performance counters. */
160 struct ac_perfcounters ac_perfcounters;
161
162 uint32_t num_perfcounters;
163 struct radv_perfcounter_desc *perfcounters;
164
165 struct {
166 unsigned data0;
167 unsigned data1;
168 unsigned data2;
169 unsigned cmd;
170 unsigned cntl;
171 } vid_dec_reg;
172 enum amd_ip_type vid_decode_ip;
173 uint32_t vid_addr_gfx_mode;
174 uint32_t stream_handle_base;
175 uint32_t stream_handle_counter;
176 uint32_t av1_version;
177 rvcn_enc_cmd_t vcn_enc_cmds;
178 enum radv_video_enc_hw_ver enc_hw_ver;
179 uint32_t encoder_interface_version;
180 bool video_encode_enabled;
181 bool video_decode_enabled;
182 struct radv_physical_device_cache_key cache_key;
183
184 uint32_t tess_distribution_mode;
185 };
186
187 VK_DEFINE_HANDLE_CASTS(radv_physical_device, vk.base, VkPhysicalDevice, VK_OBJECT_TYPE_PHYSICAL_DEVICE)
188
189 static inline struct radv_instance *
radv_physical_device_instance(const struct radv_physical_device * pdev)190 radv_physical_device_instance(const struct radv_physical_device *pdev)
191 {
192 return (struct radv_instance *)pdev->vk.instance;
193 }
194
195 static inline bool
radv_sparse_queue_enabled(const struct radv_physical_device * pdev)196 radv_sparse_queue_enabled(const struct radv_physical_device *pdev)
197 {
198 const struct radv_instance *instance = radv_physical_device_instance(pdev);
199
200 /* Dedicated sparse queue requires VK_QUEUE_SUBMIT_MODE_THREADED, which is incompatible with
201 * VK_DEVICE_TIMELINE_MODE_EMULATED. */
202 return pdev->info.has_timeline_syncobj && !instance->drirc.legacy_sparse_binding;
203 }
204
205 static inline bool
radv_has_shader_buffer_float_minmax(const struct radv_physical_device * pdev,unsigned bitsize)206 radv_has_shader_buffer_float_minmax(const struct radv_physical_device *pdev, unsigned bitsize)
207 {
208 return (pdev->info.gfx_level <= GFX7 && !pdev->use_llvm) || pdev->info.gfx_level == GFX10 ||
209 pdev->info.gfx_level == GFX10_3 ||
210 ((pdev->info.gfx_level == GFX11 || pdev->info.gfx_level == GFX11_5) && bitsize == 32);
211 }
212
213 static inline bool
radv_has_pops(const struct radv_physical_device * pdev)214 radv_has_pops(const struct radv_physical_device *pdev)
215 {
216 return pdev->info.gfx_level >= GFX9 && !pdev->use_llvm;
217 }
218
219 static inline bool
radv_has_uvd(struct radv_physical_device * pdev)220 radv_has_uvd(struct radv_physical_device *pdev)
221 {
222 enum radeon_family family = pdev->info.family;
223 /* Only support UVD on TONGA+ */
224 if (family < CHIP_TONGA)
225 return false;
226 return pdev->info.ip[AMD_IP_UVD].num_queues > 0;
227 }
228
229 static inline enum radv_queue_family
vk_queue_to_radv(const struct radv_physical_device * pdev,int queue_family_index)230 vk_queue_to_radv(const struct radv_physical_device *pdev, int queue_family_index)
231 {
232 if (queue_family_index == VK_QUEUE_FAMILY_EXTERNAL || queue_family_index == VK_QUEUE_FAMILY_FOREIGN_EXT)
233 return RADV_QUEUE_FOREIGN;
234 if (queue_family_index == VK_QUEUE_FAMILY_IGNORED)
235 return RADV_QUEUE_IGNORED;
236
237 assert(queue_family_index < RADV_MAX_QUEUE_FAMILIES);
238 return pdev->vk_queue_to_radv[queue_family_index];
239 }
240
241 /**
242 * Helper used for debugging compiler issues by enabling/disabling LLVM for a
243 * specific shader stage (developers only).
244 */
245 static inline bool
radv_use_llvm_for_stage(const struct radv_physical_device * pdev,UNUSED gl_shader_stage stage)246 radv_use_llvm_for_stage(const struct radv_physical_device *pdev, UNUSED gl_shader_stage stage)
247 {
248 return pdev->use_llvm;
249 }
250
251 bool radv_enable_rt(const struct radv_physical_device *pdev);
252
253 bool radv_emulate_rt(const struct radv_physical_device *pdev);
254
255 uint32_t radv_find_memory_index(const struct radv_physical_device *pdev, VkMemoryPropertyFlags flags);
256
257 VkResult create_null_physical_device(struct vk_instance *vk_instance);
258
259 VkResult create_drm_physical_device(struct vk_instance *vk_instance, struct _drmDevice *device,
260 struct vk_physical_device **out);
261
262 void radv_physical_device_destroy(struct vk_physical_device *vk_pdev);
263
264 #endif /* RADV_PHYSICAL_DEVICE_H */
265