1gpu_id: 201 2cmd: deqp-gles2/185: fence=1250 3############################################################ 4cmdstream[0]: 124 dwords 5 write RB_BC_CONTROL (0f01) 6 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 70122d000: 0000: 00000f01 1c004046 8 opcode: CP_SET_CONSTANT (2d) (3 dwords) 9 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 100122d008: 0000: c0012d00 00040293 00000020 11 opcode: CP_SET_CONSTANT (2d) (3 dwords) 12 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 130122d014: 0000: c0012d00 00040316 00000002 14 opcode: CP_SET_CONSTANT (2d) (3 dwords) 15 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 160122d020: 0000: c0012d00 00040317 00000002 17 write CP_PERFMON_CNTL (0444) 18 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 190122d02c: 0000: 00000444 00000000 20 write RBBM_PM_OVERRIDE1 (039c) 21 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 22 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 230122d034: 0000: 0001039c ffffffff 00000fff 24 write TP0_CHICKEN (0e1e) 25 TP0_CHICKEN: 0x2 260122d040: 0000: 00000e1e 00000002 27 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 280122d048: 0000: c0003b00 00007fff 29 opcode: CP_SET_CONSTANT (2d) (3 dwords) 30 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 310122d050: 0000: c0012d00 00040307 00100020 32 opcode: CP_SET_CONSTANT (2d) (3 dwords) 33 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 340122d05c: 0000: c0012d00 00040308 000e0120 35 opcode: CP_SET_CONSTANT (2d) (4 dwords) 36 VGT_MAX_VTX_INDX: 0xffffffff 37 VGT_MIN_VTX_INDX: 0 380122d068: 0000: c0022d00 00040100 ffffffff 00000000 39 opcode: CP_SET_CONSTANT (2d) (3 dwords) 40 VGT_INDX_OFFSET: 0 410122d078: 0000: c0012d00 00040102 00000000 42 opcode: CP_SET_CONSTANT (2d) (3 dwords) 43 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 440122d084: 0000: c0012d00 00040181 00000004 45 opcode: CP_SET_CONSTANT (2d) (3 dwords) 46 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 470122d090: 0000: c0012d00 00040182 ffffffff 48 opcode: CP_SET_CONSTANT (2d) (3 dwords) 49 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 500122d09c: 0000: c0012d00 00040301 00000000 51 opcode: CP_SET_CONSTANT (2d) (3 dwords) 52 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 530122d0a8: 0000: c0012d00 00040300 00000000 54 opcode: CP_SET_CONSTANT (2d) (3 dwords) 55 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 560122d0b4: 0000: c0012d00 00040080 00000000 57 opcode: CP_SET_CONSTANT (2d) (3 dwords) 58 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 590122d0c0: 0000: c0012d00 00040208 00000004 60 opcode: CP_SET_CONSTANT (2d) (3 dwords) 61 RB_SAMPLE_POS: 0x88888888 620122d0cc: 0000: c0012d00 0004020a 88888888 63 opcode: CP_SET_CONSTANT (2d) (3 dwords) 64 RB_COLOR_DEST_MASK: 0xffffffff 650122d0d8: 0000: c0012d00 00040326 ffffffff 66 opcode: CP_SET_CONSTANT (2d) (3 dwords) 67 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 680122d0e4: 0000: c0012d00 0004031b 0003c000 69 opcode: CP_SET_CONSTANT (2d) (4 dwords) 70 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 71 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 720122d0f0: 0000: c0022d00 00040183 00000000 00000000 73 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 740122d100: 0000: c0004b00 00000000 75 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 760122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001 77 write SQ_INST_STORE_MANAGMENT (0d02) 78 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 790122d11c: 0000: 00000d02 00000180 80 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 810122d124: 0000: c0003b00 00000300 82 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 830122d12c: 0000: c0004a00 80000180 84 opcode: CP_SET_CONSTANT (2d) (14 dwords) 850122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 860122d15c: 2.000000 0.750000 0.375000 0.250000 870122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 880122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 89 opcode: CP_SET_CONSTANT (2d) (3 dwords) 90 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 910122d16c: 0000: c0012d00 00040104 0000000f 92 opcode: CP_SET_CONSTANT (2d) (6 dwords) 93 RB_BLEND_RED: 0 94 RB_BLEND_GREEN: 0 95 RB_BLEND_BLUE: 0 96 RB_BLEND_ALPHA: 0xff 970122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 98 opcode: CP_SET_CONSTANT (2d) (3 dwords) 99 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 1000122d190: 0000: c0012d00 00040206 0000043f 101 opcode: CP_SET_CONSTANT (2d) (3 dwords) 102 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 } 1030122d19c: 0000: c0012d00 00040000 00000040 104 opcode: CP_SET_CONSTANT (2d) (3 dwords) 105 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x110d000 } 1060122d1a8: 0000: c0012d00 00040001 0110d009 107 opcode: CP_SET_CONSTANT (2d) (4 dwords) 108 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 109 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 } 1100122d1b4: 0000: c0022d00 0004000e 80000000 00800040 111 opcode: CP_SET_CONSTANT (2d) (3 dwords) 112 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 1130122d1c4: 0000: c0012d00 00040080 00000000 114 write CP_SCRATCH_REG6 (057e) 115 CP_SCRATCH_REG6: 9 116 :0,0,9,0 1170122d1d0: 0000: 0000057e 00000009 118 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 119 ibaddr:0122e000 120 ibsize:000000b6 121 opcode: CP_SET_CONSTANT (2d) (6 dwords) 122 set shader const 0078 1230122e000: 0000: c0042d00 00010078 0112d003 00100000 0112d003 00100000 124 opcode: CP_SET_CONSTANT (2d) (3 dwords) 125 PA_SC_AA_MASK: 0xffff 1260122e018: 0000: c0012d00 00040312 0000ffff 127 opcode: CP_SET_CONSTANT (2d) (3 dwords) 128 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 1290122e024: 0000: c0012d00 00040200 00000000 130 opcode: CP_SET_CONSTANT (2d) (5 dwords) 131 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 132 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 133 RB_ALPHA_REF: 0 1340122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 135 opcode: CP_SET_CONSTANT (2d) (4 dwords) 136 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 137 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 1380122e044: 0000: c0022d00 00040204 00000000 00090244 139 opcode: CP_SET_CONSTANT (2d) (6 dwords) 140 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 141 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 142 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 143 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 1440122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 145 opcode: CP_SET_CONSTANT (2d) (7 dwords) 146 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 147 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 148 PA_CL_GB_VERT_DISC_ADJ: 1.000000 149 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 150 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 1510122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 152 opcode: CP_SET_CONSTANT (2d) (4 dwords) 153 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 154 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 } 1550122e088: 0000: c0022d00 00040081 00000000 00800040 156 opcode: CP_SET_CONSTANT (2d) (8 dwords) 157 PA_CL_VPORT_XSCALE: 32.000000 158 PA_CL_VPORT_XOFFSET: 32.000000 159 PA_CL_VPORT_YSCALE: 64.000000 160 PA_CL_VPORT_YOFFSET: 64.000000 161 PA_CL_VPORT_ZSCALE: 0.000000 162 PA_CL_VPORT_ZOFFSET: 0.000000 1630122e098: 0000: c0062d00 0004010f 42000000 42000000 42800000 42800000 00000000 00000000 164 opcode: CP_SET_CONSTANT (2d) (10 dwords) 1650122e0c0: 32.000000 64.000000 0.000000 0.000000 32.000000 64.000000 0.000000 0.000000 1660122e0b8: 0000: c0082d00 00000184 42000000 42800000 00000000 00000000 42000000 42800000 167* 168 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 169 vertex shader, start=0000, size=0015 170 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 171 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 172 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 173 0000 0000 c200 ALLOC POSITION SIZE(0x0) 174 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 175 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 176 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 177 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 178 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 179 0000 0000 0000 NOP 1800122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 1810122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 1820122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 183 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 184 fragment shader, start=0000, size=000c 185 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 186 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 187 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 188 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 189 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 190 0000 0000 0000 NOP 1910122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 1920122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 193 opcode: CP_SET_CONSTANT (2d) (3 dwords) 194 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 1950122e17c: 0000: c0012d00 00040181 00000106 196 opcode: CP_SET_CONSTANT (2d) (3 dwords) 197 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 1980122e188: 0000: c0012d00 00040180 10030002 199 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2000122e19c: 0.000000 0.000000 0.000000 0.000000 2010122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 202 opcode: CP_SET_CONSTANT (2d) (3 dwords) 203 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 2040122e1ac: 0000: c0012d00 00040202 00000c20 205 opcode: CP_SET_CONSTANT (2d) (3 dwords) 206 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 2070122e1b8: 0000: c0012d00 00040201 00000000 208 opcode: CP_SET_CONSTANT (2d) (3 dwords) 209 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 2100122e1c4: 0000: c0012d00 00040104 0000000f 211 opcode: CP_SET_CONSTANT (2d) (6 dwords) 212 RB_BLEND_RED: 0 213 RB_BLEND_GREEN: 0 214 RB_BLEND_BLUE: 0 215 RB_BLEND_ALPHA: 0 2160122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 217 opcode: CP_SET_CONSTANT (2d) (8 dwords) 218 set texture const 0000 219 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 220 filter min/mag: point/point 221 swizzle: xyzw 222 addr=0111d000 (flags=820), size=64x128, pitch=64, format=FMT_1_REVERSE 223 mipaddr=00000000 (flags=200) 2240122e1e8: 0000: c0062d00 00010000 00824800 0111d820 000fe03f 00000d11 00000000 00000200 225 opcode: CP_SET_CONSTANT (2d) (3 dwords) 226 VGT_INDX_OFFSET: 0 2270122e208: 0000: c0012d00 00040102 00000000 228 write TC_CNTL_STATUS (0e00) 229 TC_CNTL_STATUS: { L2_INVALIDATE } 2300122e214: 0000: 00000e00 00000001 231 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 2320122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 233 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 2340122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 235 write CP_SCRATCH_REG7 (057f) 236 CP_SCRATCH_REG7: 5 237 :0,0,9,5 2380122e24c: 0000: 0000057f 00000005 239 opcode: CP_NOP (10) (2 dwords) 2400122e254: 0000: c0001000 00000000 241 opcode: CP_DRAW_INDX (22) (3 dwords) 242 { VIZ_QUERY = 0 } 243 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 244 draw: 0 245 prim_type: DI_PT_TRIFAN (5) 246 source_select: DI_SRC_SEL_AUTO_INDEX (2) 247 num_indices: 1407 248 draw[0] register values 249!+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 250!+ 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 251 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 252!+ 00000009 CP_SCRATCH_REG6: 9 253 :0,0,9,5 254!+ 00000005 CP_SCRATCH_REG7: 5 255 :0,0,9,5 256!+ 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 257!+ 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 258!+ 00000002 TP0_CHICKEN: 0x2 259!+ 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 260!+ 00000040 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 } 261!+ 0110d009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x110d000 } 262!+ 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 263!+ 00800040 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 } 264 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 265 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 266!+ 00800040 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 } 267!+ ffffffff VGT_MAX_VTX_INDX: 0xffffffff 268 + 00000000 VGT_MIN_VTX_INDX: 0 269 + 00000000 VGT_INDX_OFFSET: 0 270!+ 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 271 + 00000000 RB_BLEND_RED: 0 272 + 00000000 RB_BLEND_GREEN: 0 273 + 00000000 RB_BLEND_BLUE: 0 274 + 00000000 RB_BLEND_ALPHA: 0 275 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 276 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 277 + 00000000 RB_ALPHA_REF: 0 278!+ 42000000 PA_CL_VPORT_XSCALE: 32.000000 279!+ 42000000 PA_CL_VPORT_XOFFSET: 32.000000 280!+ 42800000 PA_CL_VPORT_YSCALE: 64.000000 281!+ 42800000 PA_CL_VPORT_YOFFSET: 64.000000 282 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 283 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 284!+ 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 285!+ 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 286!+ ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 287 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 288 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 289 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 290 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 291!+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 292 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 293!+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 294!+ 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 295!+ 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 296!+ 88888888 RB_SAMPLE_POS: 0x88888888 297 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 298 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 299 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 300 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 301!+ 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 302 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 303 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 304!+ 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 305!+ 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 306!+ 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 307!+ 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 308!+ 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 309!+ 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 310!+ 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 311!+ 0000ffff PA_SC_AA_MASK: 0xffff 312!+ 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 313!+ 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 314!+ 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 315!+ ffffffff RB_COLOR_DEST_MASK: 0xffffffff 3160122e25c: 0000: c0012200 00000000 00040085 317 write CP_SCRATCH_REG7 (057f) 318NEEDS WFI: CP_SCRATCH_REG7 (57f) 319 CP_SCRATCH_REG7: 6 320 :0,0,9,6 3210122e268: 0000: 0000057f 00000006 322 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 3230122e270: 0000: c0002600 00000000 324 opcode: CP_EVENT_WRITE (46) (2 dwords) 325 { EVENT = CACHE_FLUSH } 326 event CACHE_FLUSH 3270122e278: 0000: c0004600 00000006 328 opcode: CP_EVENT_WRITE (46) (2 dwords) 329 { EVENT = CACHE_FLUSH } 330 event CACHE_FLUSH 3310122e280: 0000: c0004600 00000006 332 opcode: CP_EVENT_WRITE (46) (2 dwords) 333 { EVENT = CACHE_FLUSH } 334 event CACHE_FLUSH 3350122e288: 0000: c0004600 00000006 336 opcode: CP_EVENT_WRITE (46) (2 dwords) 337 { EVENT = CACHE_FLUSH } 338 event CACHE_FLUSH 3390122e290: 0000: c0004600 00000006 340 opcode: CP_EVENT_WRITE (46) (2 dwords) 341 { EVENT = CACHE_FLUSH } 342 event CACHE_FLUSH 3430122e298: 0000: c0004600 00000006 344 opcode: CP_EVENT_WRITE (46) (2 dwords) 345 { EVENT = CACHE_FLUSH } 346 event CACHE_FLUSH 3470122e2a0: 0000: c0004600 00000006 348 opcode: CP_EVENT_WRITE (46) (2 dwords) 349 { EVENT = CACHE_FLUSH } 350 event CACHE_FLUSH 3510122e2a8: 0000: c0004600 00000006 352 opcode: CP_EVENT_WRITE (46) (2 dwords) 353 { EVENT = CACHE_FLUSH } 354 event CACHE_FLUSH 3550122e2b0: 0000: c0004600 00000006 356 opcode: CP_EVENT_WRITE (46) (2 dwords) 357 { EVENT = CACHE_FLUSH } 358 event CACHE_FLUSH 3590122e2b8: 0000: c0004600 00000006 360 opcode: CP_EVENT_WRITE (46) (2 dwords) 361 { EVENT = CACHE_FLUSH } 362 event CACHE_FLUSH 3630122e2c0: 0000: c0004600 00000006 364 opcode: CP_EVENT_WRITE (46) (2 dwords) 365 { EVENT = CACHE_FLUSH } 366 event CACHE_FLUSH 3670122e2c8: 0000: c0004600 00000006 368 opcode: CP_EVENT_WRITE (46) (2 dwords) 369 { EVENT = CACHE_FLUSH } 370 event CACHE_FLUSH 3710122e2d0: 0000: c0004600 00000006 3720122d1d8: 0000: c0013700 0122e000 000000b6 373 nop 374 write CP_SCRATCH_REG6 (057e) 375 CP_SCRATCH_REG6: 10 376 :0,0,10,6 3770122d1e8: 0000: 0000057e 0000000a 378############################################################ 379vertices: 0 380cmd: deqp-gles2/185: fence=1251 381############################################################ 382cmdstream[1]: 124 dwords 383 write RB_BC_CONTROL (0f01) 384 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 3850122f000: 0000: 00000f01 1c004046 386 opcode: CP_SET_CONSTANT (2d) (3 dwords) 387 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 3880122f008: 0000: c0012d00 00040293 00000020 389 opcode: CP_SET_CONSTANT (2d) (3 dwords) 390 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 3910122f014: 0000: c0012d00 00040316 00000002 392 opcode: CP_SET_CONSTANT (2d) (3 dwords) 393 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 3940122f020: 0000: c0012d00 00040317 00000002 395 write CP_PERFMON_CNTL (0444) 396 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 3970122f02c: 0000: 00000444 00000000 398 write RBBM_PM_OVERRIDE1 (039c) 399 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 400 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 4010122f034: 0000: 0001039c ffffffff 00000fff 402 write TP0_CHICKEN (0e1e) 403 TP0_CHICKEN: 0x2 4040122f040: 0000: 00000e1e 00000002 405 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 4060122f048: 0000: c0003b00 00007fff 407 opcode: CP_SET_CONSTANT (2d) (3 dwords) 408 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 4090122f050: 0000: c0012d00 00040307 00100020 410 opcode: CP_SET_CONSTANT (2d) (3 dwords) 411 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 4120122f05c: 0000: c0012d00 00040308 000e0120 413 opcode: CP_SET_CONSTANT (2d) (4 dwords) 414 VGT_MAX_VTX_INDX: 0xffffffff 415 VGT_MIN_VTX_INDX: 0 4160122f068: 0000: c0022d00 00040100 ffffffff 00000000 417 opcode: CP_SET_CONSTANT (2d) (3 dwords) 418 VGT_INDX_OFFSET: 0 4190122f078: 0000: c0012d00 00040102 00000000 420 opcode: CP_SET_CONSTANT (2d) (3 dwords) 421 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 4220122f084: 0000: c0012d00 00040181 00000004 423 opcode: CP_SET_CONSTANT (2d) (3 dwords) 424 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 4250122f090: 0000: c0012d00 00040182 ffffffff 426 opcode: CP_SET_CONSTANT (2d) (3 dwords) 427 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 4280122f09c: 0000: c0012d00 00040301 00000000 429 opcode: CP_SET_CONSTANT (2d) (3 dwords) 430 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 4310122f0a8: 0000: c0012d00 00040300 00000000 432 opcode: CP_SET_CONSTANT (2d) (3 dwords) 433 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 4340122f0b4: 0000: c0012d00 00040080 00000000 435 opcode: CP_SET_CONSTANT (2d) (3 dwords) 436 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 4370122f0c0: 0000: c0012d00 00040208 00000004 438 opcode: CP_SET_CONSTANT (2d) (3 dwords) 439 RB_SAMPLE_POS: 0x88888888 4400122f0cc: 0000: c0012d00 0004020a 88888888 441 opcode: CP_SET_CONSTANT (2d) (3 dwords) 442 RB_COLOR_DEST_MASK: 0xffffffff 4430122f0d8: 0000: c0012d00 00040326 ffffffff 444 opcode: CP_SET_CONSTANT (2d) (3 dwords) 445 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 4460122f0e4: 0000: c0012d00 0004031b 0003c000 447 opcode: CP_SET_CONSTANT (2d) (4 dwords) 448 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 449 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 4500122f0f0: 0000: c0022d00 00040183 00000000 00000000 451 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 4520122f100: 0000: c0004b00 00000000 453 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 4540122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001 455 write SQ_INST_STORE_MANAGMENT (0d02) 456 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 4570122f11c: 0000: 00000d02 00000180 458 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 4590122f124: 0000: c0003b00 00000300 460 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 4610122f12c: 0000: c0004a00 80000180 462 opcode: CP_SET_CONSTANT (2d) (14 dwords) 4630122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 4640122f15c: 2.000000 0.750000 0.375000 0.250000 4650122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 4660122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 467 opcode: CP_SET_CONSTANT (2d) (3 dwords) 468 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 4690122f16c: 0000: c0012d00 00040104 0000000f 470 opcode: CP_SET_CONSTANT (2d) (6 dwords) 471 RB_BLEND_RED: 0 472 RB_BLEND_GREEN: 0 473 RB_BLEND_BLUE: 0 474 RB_BLEND_ALPHA: 0xff 4750122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 476 opcode: CP_SET_CONSTANT (2d) (3 dwords) 477 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 4780122f190: 0000: c0012d00 00040206 0000043f 479 opcode: CP_SET_CONSTANT (2d) (3 dwords) 480 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 4810122f19c: 0000: c0012d00 00040000 00000020 482 opcode: CP_SET_CONSTANT (2d) (3 dwords) 483 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1240000 } 4840122f1a8: 0000: c0012d00 00040001 01240009 485 opcode: CP_SET_CONSTANT (2d) (4 dwords) 486 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 487 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 } 4880122f1b4: 0000: c0022d00 0004000e 80000000 00400020 489 opcode: CP_SET_CONSTANT (2d) (3 dwords) 490 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 4910122f1c4: 0000: c0012d00 00040080 00000000 492 write CP_SCRATCH_REG6 (057e) 493 CP_SCRATCH_REG6: 15 494 :0,0,15,6 4950122f1d0: 0000: 0000057e 0000000f 496 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 497 ibaddr:0122e000 498 ibsize:000000b6 499 opcode: CP_SET_CONSTANT (2d) (6 dwords) 500 set shader const 0078 5010122e000: 0000: c0042d00 00010078 0112d083 00100000 0112d083 00100000 502 opcode: CP_SET_CONSTANT (2d) (3 dwords) 503 PA_SC_AA_MASK: 0xffff 5040122e018: 0000: c0012d00 00040312 0000ffff 505 opcode: CP_SET_CONSTANT (2d) (3 dwords) 506 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 5070122e024: 0000: c0012d00 00040200 00000000 508 opcode: CP_SET_CONSTANT (2d) (5 dwords) 509 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 510 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 511 RB_ALPHA_REF: 0 5120122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 513 opcode: CP_SET_CONSTANT (2d) (4 dwords) 514 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 515 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 5160122e044: 0000: c0022d00 00040204 00000000 00090244 517 opcode: CP_SET_CONSTANT (2d) (6 dwords) 518 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 519 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 520 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 521 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 5220122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 523 opcode: CP_SET_CONSTANT (2d) (7 dwords) 524 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 525 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 526 PA_CL_GB_VERT_DISC_ADJ: 1.000000 527 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 528 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 5290122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 530 opcode: CP_SET_CONSTANT (2d) (4 dwords) 531 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 532 PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 } 5330122e088: 0000: c0022d00 00040081 00000000 00400020 534 opcode: CP_SET_CONSTANT (2d) (8 dwords) 535 PA_CL_VPORT_XSCALE: 16.000000 536 PA_CL_VPORT_XOFFSET: 16.000000 537 PA_CL_VPORT_YSCALE: 32.000000 538 PA_CL_VPORT_YOFFSET: 32.000000 539 PA_CL_VPORT_ZSCALE: 0.000000 540 PA_CL_VPORT_ZOFFSET: 0.000000 5410122e098: 0000: c0062d00 0004010f 41800000 41800000 42000000 42000000 00000000 00000000 542 opcode: CP_SET_CONSTANT (2d) (10 dwords) 5430122e0c0: 16.000000 32.000000 0.000000 0.000000 16.000000 32.000000 0.000000 0.000000 5440122e0b8: 0000: c0082d00 00000184 41800000 42000000 00000000 00000000 41800000 42000000 545* 546 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 547 vertex shader, start=0000, size=0015 548 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 549 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 550 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 551 0000 0000 c200 ALLOC POSITION SIZE(0x0) 552 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 553 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 554 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 555 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 556 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 557 0000 0000 0000 NOP 5580122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 5590122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 5600122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 561 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 562 fragment shader, start=0000, size=000c 563 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 564 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 565 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 566 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 567 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 568 0000 0000 0000 NOP 5690122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 5700122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 571 opcode: CP_SET_CONSTANT (2d) (3 dwords) 572 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 5730122e17c: 0000: c0012d00 00040181 00000106 574 opcode: CP_SET_CONSTANT (2d) (3 dwords) 575 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 5760122e188: 0000: c0012d00 00040180 10030002 577 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5780122e19c: 0.000000 0.000000 0.000000 0.000000 5790122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 580 opcode: CP_SET_CONSTANT (2d) (3 dwords) 581 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 5820122e1ac: 0000: c0012d00 00040202 00000c20 583 opcode: CP_SET_CONSTANT (2d) (3 dwords) 584 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 5850122e1b8: 0000: c0012d00 00040201 00000000 586 opcode: CP_SET_CONSTANT (2d) (3 dwords) 587 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 5880122e1c4: 0000: c0012d00 00040104 0000000f 589 opcode: CP_SET_CONSTANT (2d) (6 dwords) 590 RB_BLEND_RED: 0 591 RB_BLEND_GREEN: 0 592 RB_BLEND_BLUE: 0 593 RB_BLEND_ALPHA: 0 5940122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 595 opcode: CP_SET_CONSTANT (2d) (8 dwords) 596 set texture const 0000 597 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 598 filter min/mag: point/point 599 swizzle: xyzw 600 addr=01250000 (flags=820), size=32x64, pitch=32, format=FMT_1_REVERSE 601 mipaddr=00000000 (flags=200) 6020122e1e8: 0000: c0062d00 00010000 00424800 01250820 0007e01f 00000d11 00000000 00000200 603 opcode: CP_SET_CONSTANT (2d) (3 dwords) 604 VGT_INDX_OFFSET: 0 6050122e208: 0000: c0012d00 00040102 00000000 606 write TC_CNTL_STATUS (0e00) 607 TC_CNTL_STATUS: { L2_INVALIDATE } 6080122e214: 0000: 00000e00 00000001 609 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 6100122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 611 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 6120122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 613 write CP_SCRATCH_REG7 (057f) 614 CP_SCRATCH_REG7: 11 615 :0,0,15,11 6160122e24c: 0000: 0000057f 0000000b 617 opcode: CP_NOP (10) (2 dwords) 6180122e254: 0000: c0001000 00000000 619 opcode: CP_DRAW_INDX (22) (3 dwords) 620 { VIZ_QUERY = 0 } 621 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 622 draw: 0 623 prim_type: DI_PT_TRIFAN (5) 624 source_select: DI_SRC_SEL_AUTO_INDEX (2) 625 num_indices: 1407 626 draw[1] register values 627 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 628 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 629 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 630!+ 0000000f CP_SCRATCH_REG6: 15 631 :0,0,15,11 632!+ 0000000b CP_SCRATCH_REG7: 11 633 :0,0,15,11 634 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 635 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 636 + 00000002 TP0_CHICKEN: 0x2 637 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 638!+ 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 639!+ 01240009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1240000 } 640 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 641!+ 00400020 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 } 642 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 643 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 644!+ 00400020 PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 } 645 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 646 + 00000000 VGT_MIN_VTX_INDX: 0 647 + 00000000 VGT_INDX_OFFSET: 0 648 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 649 + 00000000 RB_BLEND_RED: 0 650 + 00000000 RB_BLEND_GREEN: 0 651 + 00000000 RB_BLEND_BLUE: 0 652 + 00000000 RB_BLEND_ALPHA: 0 653 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 654 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 655 + 00000000 RB_ALPHA_REF: 0 656!+ 41800000 PA_CL_VPORT_XSCALE: 16.000000 657!+ 41800000 PA_CL_VPORT_XOFFSET: 16.000000 658!+ 42000000 PA_CL_VPORT_YSCALE: 32.000000 659!+ 42000000 PA_CL_VPORT_YOFFSET: 32.000000 660 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 661 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 662 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 663 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 664 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 665 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 666 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 667 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 668 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 669 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 670 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 671 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 672 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 673 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 674 + 88888888 RB_SAMPLE_POS: 0x88888888 675 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 676 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 677 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 678 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 679 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 680 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 681 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 682 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 683 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 684 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 685 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 686 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 687 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 688 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 689 + 0000ffff PA_SC_AA_MASK: 0xffff 690 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 691 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 692 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 693 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 6940122e25c: 0000: c0012200 00000000 00040085 695 write CP_SCRATCH_REG7 (057f) 696NEEDS WFI: CP_SCRATCH_REG7 (57f) 697 CP_SCRATCH_REG7: 12 698 :0,0,15,12 6990122e268: 0000: 0000057f 0000000c 700 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 7010122e270: 0000: c0002600 00000000 702 opcode: CP_EVENT_WRITE (46) (2 dwords) 703 { EVENT = CACHE_FLUSH } 704 event CACHE_FLUSH 7050122e278: 0000: c0004600 00000006 706 opcode: CP_EVENT_WRITE (46) (2 dwords) 707 { EVENT = CACHE_FLUSH } 708 event CACHE_FLUSH 7090122e280: 0000: c0004600 00000006 710 opcode: CP_EVENT_WRITE (46) (2 dwords) 711 { EVENT = CACHE_FLUSH } 712 event CACHE_FLUSH 7130122e288: 0000: c0004600 00000006 714 opcode: CP_EVENT_WRITE (46) (2 dwords) 715 { EVENT = CACHE_FLUSH } 716 event CACHE_FLUSH 7170122e290: 0000: c0004600 00000006 718 opcode: CP_EVENT_WRITE (46) (2 dwords) 719 { EVENT = CACHE_FLUSH } 720 event CACHE_FLUSH 7210122e298: 0000: c0004600 00000006 722 opcode: CP_EVENT_WRITE (46) (2 dwords) 723 { EVENT = CACHE_FLUSH } 724 event CACHE_FLUSH 7250122e2a0: 0000: c0004600 00000006 726 opcode: CP_EVENT_WRITE (46) (2 dwords) 727 { EVENT = CACHE_FLUSH } 728 event CACHE_FLUSH 7290122e2a8: 0000: c0004600 00000006 730 opcode: CP_EVENT_WRITE (46) (2 dwords) 731 { EVENT = CACHE_FLUSH } 732 event CACHE_FLUSH 7330122e2b0: 0000: c0004600 00000006 734 opcode: CP_EVENT_WRITE (46) (2 dwords) 735 { EVENT = CACHE_FLUSH } 736 event CACHE_FLUSH 7370122e2b8: 0000: c0004600 00000006 738 opcode: CP_EVENT_WRITE (46) (2 dwords) 739 { EVENT = CACHE_FLUSH } 740 event CACHE_FLUSH 7410122e2c0: 0000: c0004600 00000006 742 opcode: CP_EVENT_WRITE (46) (2 dwords) 743 { EVENT = CACHE_FLUSH } 744 event CACHE_FLUSH 7450122e2c8: 0000: c0004600 00000006 746 opcode: CP_EVENT_WRITE (46) (2 dwords) 747 { EVENT = CACHE_FLUSH } 748 event CACHE_FLUSH 7490122e2d0: 0000: c0004600 00000006 7500122f1d8: 0000: c0013700 0122e000 000000b6 751 nop 752 write CP_SCRATCH_REG6 (057e) 753 CP_SCRATCH_REG6: 16 754 :0,0,16,12 7550122f1e8: 0000: 0000057e 00000010 756############################################################ 757vertices: 0 758cmd: deqp-gles2/185: fence=1252 759############################################################ 760cmdstream[2]: 124 dwords 761 write RB_BC_CONTROL (0f01) 762 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 7630122d000: 0000: 00000f01 1c004046 764 opcode: CP_SET_CONSTANT (2d) (3 dwords) 765 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 7660122d008: 0000: c0012d00 00040293 00000020 767 opcode: CP_SET_CONSTANT (2d) (3 dwords) 768 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 7690122d014: 0000: c0012d00 00040316 00000002 770 opcode: CP_SET_CONSTANT (2d) (3 dwords) 771 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 7720122d020: 0000: c0012d00 00040317 00000002 773 write CP_PERFMON_CNTL (0444) 774 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 7750122d02c: 0000: 00000444 00000000 776 write RBBM_PM_OVERRIDE1 (039c) 777 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 778 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 7790122d034: 0000: 0001039c ffffffff 00000fff 780 write TP0_CHICKEN (0e1e) 781 TP0_CHICKEN: 0x2 7820122d040: 0000: 00000e1e 00000002 783 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 7840122d048: 0000: c0003b00 00007fff 785 opcode: CP_SET_CONSTANT (2d) (3 dwords) 786 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 7870122d050: 0000: c0012d00 00040307 00100020 788 opcode: CP_SET_CONSTANT (2d) (3 dwords) 789 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 7900122d05c: 0000: c0012d00 00040308 000e0120 791 opcode: CP_SET_CONSTANT (2d) (4 dwords) 792 VGT_MAX_VTX_INDX: 0xffffffff 793 VGT_MIN_VTX_INDX: 0 7940122d068: 0000: c0022d00 00040100 ffffffff 00000000 795 opcode: CP_SET_CONSTANT (2d) (3 dwords) 796 VGT_INDX_OFFSET: 0 7970122d078: 0000: c0012d00 00040102 00000000 798 opcode: CP_SET_CONSTANT (2d) (3 dwords) 799 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 8000122d084: 0000: c0012d00 00040181 00000004 801 opcode: CP_SET_CONSTANT (2d) (3 dwords) 802 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 8030122d090: 0000: c0012d00 00040182 ffffffff 804 opcode: CP_SET_CONSTANT (2d) (3 dwords) 805 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 8060122d09c: 0000: c0012d00 00040301 00000000 807 opcode: CP_SET_CONSTANT (2d) (3 dwords) 808 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 8090122d0a8: 0000: c0012d00 00040300 00000000 810 opcode: CP_SET_CONSTANT (2d) (3 dwords) 811 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 8120122d0b4: 0000: c0012d00 00040080 00000000 813 opcode: CP_SET_CONSTANT (2d) (3 dwords) 814 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 8150122d0c0: 0000: c0012d00 00040208 00000004 816 opcode: CP_SET_CONSTANT (2d) (3 dwords) 817 RB_SAMPLE_POS: 0x88888888 8180122d0cc: 0000: c0012d00 0004020a 88888888 819 opcode: CP_SET_CONSTANT (2d) (3 dwords) 820 RB_COLOR_DEST_MASK: 0xffffffff 8210122d0d8: 0000: c0012d00 00040326 ffffffff 822 opcode: CP_SET_CONSTANT (2d) (3 dwords) 823 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 8240122d0e4: 0000: c0012d00 0004031b 0003c000 825 opcode: CP_SET_CONSTANT (2d) (4 dwords) 826 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 827 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 8280122d0f0: 0000: c0022d00 00040183 00000000 00000000 829 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 8300122d100: 0000: c0004b00 00000000 831 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 8320122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001 833 write SQ_INST_STORE_MANAGMENT (0d02) 834 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 8350122d11c: 0000: 00000d02 00000180 836 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 8370122d124: 0000: c0003b00 00000300 838 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 8390122d12c: 0000: c0004a00 80000180 840 opcode: CP_SET_CONSTANT (2d) (14 dwords) 8410122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 8420122d15c: 2.000000 0.750000 0.375000 0.250000 8430122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 8440122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 845 opcode: CP_SET_CONSTANT (2d) (3 dwords) 846 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 8470122d16c: 0000: c0012d00 00040104 0000000f 848 opcode: CP_SET_CONSTANT (2d) (6 dwords) 849 RB_BLEND_RED: 0 850 RB_BLEND_GREEN: 0 851 RB_BLEND_BLUE: 0 852 RB_BLEND_ALPHA: 0xff 8530122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 854 opcode: CP_SET_CONSTANT (2d) (3 dwords) 855 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 8560122d190: 0000: c0012d00 00040206 0000043f 857 opcode: CP_SET_CONSTANT (2d) (3 dwords) 858 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 8590122d19c: 0000: c0012d00 00040000 00000020 860 opcode: CP_SET_CONSTANT (2d) (3 dwords) 861 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1244000 } 8620122d1a8: 0000: c0012d00 00040001 01244009 863 opcode: CP_SET_CONSTANT (2d) (4 dwords) 864 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 865 PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 } 8660122d1b4: 0000: c0022d00 0004000e 80000000 00200010 867 opcode: CP_SET_CONSTANT (2d) (3 dwords) 868 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 8690122d1c4: 0000: c0012d00 00040080 00000000 870 write CP_SCRATCH_REG6 (057e) 871 CP_SCRATCH_REG6: 21 872 :0,0,21,12 8730122d1d0: 0000: 0000057e 00000015 874 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 875 ibaddr:0122e000 876 ibsize:000000b6 877 opcode: CP_SET_CONSTANT (2d) (6 dwords) 878 set shader const 0078 8790122e000: 0000: c0042d00 00010078 0112d103 00100000 0112d103 00100000 880 opcode: CP_SET_CONSTANT (2d) (3 dwords) 881 PA_SC_AA_MASK: 0xffff 8820122e018: 0000: c0012d00 00040312 0000ffff 883 opcode: CP_SET_CONSTANT (2d) (3 dwords) 884 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 8850122e024: 0000: c0012d00 00040200 00000000 886 opcode: CP_SET_CONSTANT (2d) (5 dwords) 887 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 888 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 889 RB_ALPHA_REF: 0 8900122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 891 opcode: CP_SET_CONSTANT (2d) (4 dwords) 892 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 893 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 8940122e044: 0000: c0022d00 00040204 00000000 00090244 895 opcode: CP_SET_CONSTANT (2d) (6 dwords) 896 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 897 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 898 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 899 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 9000122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 901 opcode: CP_SET_CONSTANT (2d) (7 dwords) 902 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 903 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 904 PA_CL_GB_VERT_DISC_ADJ: 1.000000 905 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 906 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 9070122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 908 opcode: CP_SET_CONSTANT (2d) (4 dwords) 909 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 910 PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 } 9110122e088: 0000: c0022d00 00040081 00000000 00200010 912 opcode: CP_SET_CONSTANT (2d) (8 dwords) 913 PA_CL_VPORT_XSCALE: 8.000000 914 PA_CL_VPORT_XOFFSET: 8.000000 915 PA_CL_VPORT_YSCALE: 16.000000 916 PA_CL_VPORT_YOFFSET: 16.000000 917 PA_CL_VPORT_ZSCALE: 0.000000 918 PA_CL_VPORT_ZOFFSET: 0.000000 9190122e098: 0000: c0062d00 0004010f 41000000 41000000 41800000 41800000 00000000 00000000 920 opcode: CP_SET_CONSTANT (2d) (10 dwords) 9210122e0c0: 8.000000 16.000000 0.000000 0.000000 8.000000 16.000000 0.000000 0.000000 9220122e0b8: 0000: c0082d00 00000184 41000000 41800000 00000000 00000000 41000000 41800000 923* 924 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 925 vertex shader, start=0000, size=0015 926 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 927 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 928 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 929 0000 0000 c200 ALLOC POSITION SIZE(0x0) 930 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 931 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 932 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 933 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 934 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 935 0000 0000 0000 NOP 9360122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 9370122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 9380122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 939 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 940 fragment shader, start=0000, size=000c 941 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 942 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 943 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 944 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 945 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 946 0000 0000 0000 NOP 9470122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 9480122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 949 opcode: CP_SET_CONSTANT (2d) (3 dwords) 950 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 9510122e17c: 0000: c0012d00 00040181 00000106 952 opcode: CP_SET_CONSTANT (2d) (3 dwords) 953 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 9540122e188: 0000: c0012d00 00040180 10030002 955 opcode: CP_SET_CONSTANT (2d) (6 dwords) 9560122e19c: 0.000000 0.000000 0.000000 0.000000 9570122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 958 opcode: CP_SET_CONSTANT (2d) (3 dwords) 959 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 9600122e1ac: 0000: c0012d00 00040202 00000c20 961 opcode: CP_SET_CONSTANT (2d) (3 dwords) 962 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 9630122e1b8: 0000: c0012d00 00040201 00000000 964 opcode: CP_SET_CONSTANT (2d) (3 dwords) 965 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 9660122e1c4: 0000: c0012d00 00040104 0000000f 967 opcode: CP_SET_CONSTANT (2d) (6 dwords) 968 RB_BLEND_RED: 0 969 RB_BLEND_GREEN: 0 970 RB_BLEND_BLUE: 0 971 RB_BLEND_ALPHA: 0 9720122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 973 opcode: CP_SET_CONSTANT (2d) (8 dwords) 974 set texture const 0000 975 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 976 filter min/mag: point/point 977 swizzle: xyzw 978 addr=01254000 (flags=820), size=16x32, pitch=32, format=FMT_1_REVERSE 979 mipaddr=00000000 (flags=200) 9800122e1e8: 0000: c0062d00 00010000 00424800 01254820 0003e00f 00000d11 00000000 00000200 981 opcode: CP_SET_CONSTANT (2d) (3 dwords) 982 VGT_INDX_OFFSET: 0 9830122e208: 0000: c0012d00 00040102 00000000 984 write TC_CNTL_STATUS (0e00) 985 TC_CNTL_STATUS: { L2_INVALIDATE } 9860122e214: 0000: 00000e00 00000001 987 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 9880122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 989 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 9900122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 991 write CP_SCRATCH_REG7 (057f) 992 CP_SCRATCH_REG7: 17 993 :0,0,21,17 9940122e24c: 0000: 0000057f 00000011 995 opcode: CP_NOP (10) (2 dwords) 9960122e254: 0000: c0001000 00000000 997 opcode: CP_DRAW_INDX (22) (3 dwords) 998 { VIZ_QUERY = 0 } 999 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 1000 draw: 0 1001 prim_type: DI_PT_TRIFAN (5) 1002 source_select: DI_SRC_SEL_AUTO_INDEX (2) 1003 num_indices: 1407 1004 draw[2] register values 1005 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 1006 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 1007 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 1008!+ 00000015 CP_SCRATCH_REG6: 21 1009 :0,0,21,17 1010!+ 00000011 CP_SCRATCH_REG7: 17 1011 :0,0,21,17 1012 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 1013 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 1014 + 00000002 TP0_CHICKEN: 0x2 1015 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 1016 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 1017!+ 01244009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1244000 } 1018 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 1019!+ 00200010 PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 } 1020 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 1021 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 1022!+ 00200010 PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 } 1023 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 1024 + 00000000 VGT_MIN_VTX_INDX: 0 1025 + 00000000 VGT_INDX_OFFSET: 0 1026 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 1027 + 00000000 RB_BLEND_RED: 0 1028 + 00000000 RB_BLEND_GREEN: 0 1029 + 00000000 RB_BLEND_BLUE: 0 1030 + 00000000 RB_BLEND_ALPHA: 0 1031 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1032 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1033 + 00000000 RB_ALPHA_REF: 0 1034!+ 41000000 PA_CL_VPORT_XSCALE: 8.000000 1035!+ 41000000 PA_CL_VPORT_XOFFSET: 8.000000 1036!+ 41800000 PA_CL_VPORT_YSCALE: 16.000000 1037!+ 41800000 PA_CL_VPORT_YOFFSET: 16.000000 1038 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 1039 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 1040 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 1041 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 1042 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 1043 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 1044 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 1045 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 1046 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 1047 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 1048 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 1049 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 1050 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 1051 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 1052 + 88888888 RB_SAMPLE_POS: 0x88888888 1053 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 1054 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 1055 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 1056 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 1057 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 1058 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 1059 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 1060 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 1061 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 1062 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 1063 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 1064 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 1065 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 1066 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 1067 + 0000ffff PA_SC_AA_MASK: 0xffff 1068 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 1069 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 1070 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 1071 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 10720122e25c: 0000: c0012200 00000000 00040085 1073 write CP_SCRATCH_REG7 (057f) 1074NEEDS WFI: CP_SCRATCH_REG7 (57f) 1075 CP_SCRATCH_REG7: 18 1076 :0,0,21,18 10770122e268: 0000: 0000057f 00000012 1078 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 10790122e270: 0000: c0002600 00000000 1080 opcode: CP_EVENT_WRITE (46) (2 dwords) 1081 { EVENT = CACHE_FLUSH } 1082 event CACHE_FLUSH 10830122e278: 0000: c0004600 00000006 1084 opcode: CP_EVENT_WRITE (46) (2 dwords) 1085 { EVENT = CACHE_FLUSH } 1086 event CACHE_FLUSH 10870122e280: 0000: c0004600 00000006 1088 opcode: CP_EVENT_WRITE (46) (2 dwords) 1089 { EVENT = CACHE_FLUSH } 1090 event CACHE_FLUSH 10910122e288: 0000: c0004600 00000006 1092 opcode: CP_EVENT_WRITE (46) (2 dwords) 1093 { EVENT = CACHE_FLUSH } 1094 event CACHE_FLUSH 10950122e290: 0000: c0004600 00000006 1096 opcode: CP_EVENT_WRITE (46) (2 dwords) 1097 { EVENT = CACHE_FLUSH } 1098 event CACHE_FLUSH 10990122e298: 0000: c0004600 00000006 1100 opcode: CP_EVENT_WRITE (46) (2 dwords) 1101 { EVENT = CACHE_FLUSH } 1102 event CACHE_FLUSH 11030122e2a0: 0000: c0004600 00000006 1104 opcode: CP_EVENT_WRITE (46) (2 dwords) 1105 { EVENT = CACHE_FLUSH } 1106 event CACHE_FLUSH 11070122e2a8: 0000: c0004600 00000006 1108 opcode: CP_EVENT_WRITE (46) (2 dwords) 1109 { EVENT = CACHE_FLUSH } 1110 event CACHE_FLUSH 11110122e2b0: 0000: c0004600 00000006 1112 opcode: CP_EVENT_WRITE (46) (2 dwords) 1113 { EVENT = CACHE_FLUSH } 1114 event CACHE_FLUSH 11150122e2b8: 0000: c0004600 00000006 1116 opcode: CP_EVENT_WRITE (46) (2 dwords) 1117 { EVENT = CACHE_FLUSH } 1118 event CACHE_FLUSH 11190122e2c0: 0000: c0004600 00000006 1120 opcode: CP_EVENT_WRITE (46) (2 dwords) 1121 { EVENT = CACHE_FLUSH } 1122 event CACHE_FLUSH 11230122e2c8: 0000: c0004600 00000006 1124 opcode: CP_EVENT_WRITE (46) (2 dwords) 1125 { EVENT = CACHE_FLUSH } 1126 event CACHE_FLUSH 11270122e2d0: 0000: c0004600 00000006 11280122d1d8: 0000: c0013700 0122e000 000000b6 1129 nop 1130 write CP_SCRATCH_REG6 (057e) 1131 CP_SCRATCH_REG6: 22 1132 :0,0,22,18 11330122d1e8: 0000: 0000057e 00000016 1134############################################################ 1135vertices: 0 1136cmd: deqp-gles2/185: fence=1253 1137############################################################ 1138cmdstream[3]: 124 dwords 1139 write RB_BC_CONTROL (0f01) 1140 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 11410122f000: 0000: 00000f01 1c004046 1142 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1143 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 11440122f008: 0000: c0012d00 00040293 00000020 1145 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1146 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 11470122f014: 0000: c0012d00 00040316 00000002 1148 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1149 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 11500122f020: 0000: c0012d00 00040317 00000002 1151 write CP_PERFMON_CNTL (0444) 1152 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 11530122f02c: 0000: 00000444 00000000 1154 write RBBM_PM_OVERRIDE1 (039c) 1155 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 1156 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 11570122f034: 0000: 0001039c ffffffff 00000fff 1158 write TP0_CHICKEN (0e1e) 1159 TP0_CHICKEN: 0x2 11600122f040: 0000: 00000e1e 00000002 1161 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 11620122f048: 0000: c0003b00 00007fff 1163 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1164 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 11650122f050: 0000: c0012d00 00040307 00100020 1166 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1167 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 11680122f05c: 0000: c0012d00 00040308 000e0120 1169 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1170 VGT_MAX_VTX_INDX: 0xffffffff 1171 VGT_MIN_VTX_INDX: 0 11720122f068: 0000: c0022d00 00040100 ffffffff 00000000 1173 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1174 VGT_INDX_OFFSET: 0 11750122f078: 0000: c0012d00 00040102 00000000 1176 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1177 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 11780122f084: 0000: c0012d00 00040181 00000004 1179 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1180 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 11810122f090: 0000: c0012d00 00040182 ffffffff 1182 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1183 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 11840122f09c: 0000: c0012d00 00040301 00000000 1185 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1186 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 11870122f0a8: 0000: c0012d00 00040300 00000000 1188 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1189 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 11900122f0b4: 0000: c0012d00 00040080 00000000 1191 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1192 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 11930122f0c0: 0000: c0012d00 00040208 00000004 1194 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1195 RB_SAMPLE_POS: 0x88888888 11960122f0cc: 0000: c0012d00 0004020a 88888888 1197 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1198 RB_COLOR_DEST_MASK: 0xffffffff 11990122f0d8: 0000: c0012d00 00040326 ffffffff 1200 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1201 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 12020122f0e4: 0000: c0012d00 0004031b 0003c000 1203 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1204 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 1205 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 12060122f0f0: 0000: c0022d00 00040183 00000000 00000000 1207 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 12080122f100: 0000: c0004b00 00000000 1209 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 12100122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001 1211 write SQ_INST_STORE_MANAGMENT (0d02) 1212 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 12130122f11c: 0000: 00000d02 00000180 1214 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 12150122f124: 0000: c0003b00 00000300 1216 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 12170122f12c: 0000: c0004a00 80000180 1218 opcode: CP_SET_CONSTANT (2d) (14 dwords) 12190122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 12200122f15c: 2.000000 0.750000 0.375000 0.250000 12210122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 12220122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 1223 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1224 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 12250122f16c: 0000: c0012d00 00040104 0000000f 1226 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1227 RB_BLEND_RED: 0 1228 RB_BLEND_GREEN: 0 1229 RB_BLEND_BLUE: 0 1230 RB_BLEND_ALPHA: 0xff 12310122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 1232 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1233 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 12340122f190: 0000: c0012d00 00040206 0000043f 1235 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1236 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 12370122f19c: 0000: c0012d00 00040000 00000020 1238 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1239 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1246000 } 12400122f1a8: 0000: c0012d00 00040001 01246009 1241 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1242 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 1243 PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 } 12440122f1b4: 0000: c0022d00 0004000e 80000000 00100008 1245 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1246 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 12470122f1c4: 0000: c0012d00 00040080 00000000 1248 write CP_SCRATCH_REG6 (057e) 1249 CP_SCRATCH_REG6: 27 1250 :0,0,27,18 12510122f1d0: 0000: 0000057e 0000001b 1252 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 1253 ibaddr:0122e000 1254 ibsize:000000b6 1255 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1256 set shader const 0078 12570122e000: 0000: c0042d00 00010078 0112d183 00100000 0112d183 00100000 1258 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1259 PA_SC_AA_MASK: 0xffff 12600122e018: 0000: c0012d00 00040312 0000ffff 1261 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1262 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 12630122e024: 0000: c0012d00 00040200 00000000 1264 opcode: CP_SET_CONSTANT (2d) (5 dwords) 1265 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1266 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1267 RB_ALPHA_REF: 0 12680122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 1269 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1270 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 1271 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 12720122e044: 0000: c0022d00 00040204 00000000 00090244 1273 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1274 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 1275 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 1276 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 1277 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 12780122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 1279 opcode: CP_SET_CONSTANT (2d) (7 dwords) 1280 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 1281 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 1282 PA_CL_GB_VERT_DISC_ADJ: 1.000000 1283 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 1284 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 12850122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 1286 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1287 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 1288 PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 } 12890122e088: 0000: c0022d00 00040081 00000000 00100008 1290 opcode: CP_SET_CONSTANT (2d) (8 dwords) 1291 PA_CL_VPORT_XSCALE: 4.000000 1292 PA_CL_VPORT_XOFFSET: 4.000000 1293 PA_CL_VPORT_YSCALE: 8.000000 1294 PA_CL_VPORT_YOFFSET: 8.000000 1295 PA_CL_VPORT_ZSCALE: 0.000000 1296 PA_CL_VPORT_ZOFFSET: 0.000000 12970122e098: 0000: c0062d00 0004010f 40800000 40800000 41000000 41000000 00000000 00000000 1298 opcode: CP_SET_CONSTANT (2d) (10 dwords) 12990122e0c0: 4.000000 8.000000 0.000000 0.000000 4.000000 8.000000 0.000000 0.000000 13000122e0b8: 0000: c0082d00 00000184 40800000 41000000 00000000 00000000 40800000 41000000 1301* 1302 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 1303 vertex shader, start=0000, size=0015 1304 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 1305 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 1306 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 1307 0000 0000 c200 ALLOC POSITION SIZE(0x0) 1308 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 1309 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 1310 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 1311 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 1312 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 1313 0000 0000 0000 NOP 13140122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 13150122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 13160122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 1317 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 1318 fragment shader, start=0000, size=000c 1319 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 1320 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 1321 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 1322 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 1323 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 1324 0000 0000 0000 NOP 13250122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 13260122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 1327 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1328 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 13290122e17c: 0000: c0012d00 00040181 00000106 1330 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1331 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 13320122e188: 0000: c0012d00 00040180 10030002 1333 opcode: CP_SET_CONSTANT (2d) (6 dwords) 13340122e19c: 0.000000 0.000000 0.000000 0.000000 13350122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 1336 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1337 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 13380122e1ac: 0000: c0012d00 00040202 00000c20 1339 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1340 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 13410122e1b8: 0000: c0012d00 00040201 00000000 1342 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1343 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 13440122e1c4: 0000: c0012d00 00040104 0000000f 1345 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1346 RB_BLEND_RED: 0 1347 RB_BLEND_GREEN: 0 1348 RB_BLEND_BLUE: 0 1349 RB_BLEND_ALPHA: 0 13500122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 1351 opcode: CP_SET_CONSTANT (2d) (8 dwords) 1352 set texture const 0000 1353 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 1354 filter min/mag: point/point 1355 swizzle: xyzw 1356 addr=01254000 (flags=820), size=8x16, pitch=32, format=FMT_1_REVERSE 1357 mipaddr=00000000 (flags=200) 13580122e1e8: 0000: c0062d00 00010000 00424800 01254820 0001e007 00000d11 00000000 00000200 1359 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1360 VGT_INDX_OFFSET: 0 13610122e208: 0000: c0012d00 00040102 00000000 1362 write TC_CNTL_STATUS (0e00) 1363 TC_CNTL_STATUS: { L2_INVALIDATE } 13640122e214: 0000: 00000e00 00000001 1365 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 13660122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 1367 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 13680122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 1369 write CP_SCRATCH_REG7 (057f) 1370 CP_SCRATCH_REG7: 23 1371 :0,0,27,23 13720122e24c: 0000: 0000057f 00000017 1373 opcode: CP_NOP (10) (2 dwords) 13740122e254: 0000: c0001000 00000000 1375 opcode: CP_DRAW_INDX (22) (3 dwords) 1376 { VIZ_QUERY = 0 } 1377 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 1378 draw: 0 1379 prim_type: DI_PT_TRIFAN (5) 1380 source_select: DI_SRC_SEL_AUTO_INDEX (2) 1381 num_indices: 1407 1382 draw[3] register values 1383 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 1384 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 1385 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 1386!+ 0000001b CP_SCRATCH_REG6: 27 1387 :0,0,27,23 1388!+ 00000017 CP_SCRATCH_REG7: 23 1389 :0,0,27,23 1390 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 1391 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 1392 + 00000002 TP0_CHICKEN: 0x2 1393 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 1394 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 1395!+ 01246009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1246000 } 1396 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 1397!+ 00100008 PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 } 1398 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 1399 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 1400!+ 00100008 PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 } 1401 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 1402 + 00000000 VGT_MIN_VTX_INDX: 0 1403 + 00000000 VGT_INDX_OFFSET: 0 1404 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 1405 + 00000000 RB_BLEND_RED: 0 1406 + 00000000 RB_BLEND_GREEN: 0 1407 + 00000000 RB_BLEND_BLUE: 0 1408 + 00000000 RB_BLEND_ALPHA: 0 1409 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1410 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1411 + 00000000 RB_ALPHA_REF: 0 1412!+ 40800000 PA_CL_VPORT_XSCALE: 4.000000 1413!+ 40800000 PA_CL_VPORT_XOFFSET: 4.000000 1414!+ 41000000 PA_CL_VPORT_YSCALE: 8.000000 1415!+ 41000000 PA_CL_VPORT_YOFFSET: 8.000000 1416 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 1417 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 1418 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 1419 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 1420 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 1421 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 1422 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 1423 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 1424 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 1425 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 1426 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 1427 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 1428 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 1429 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 1430 + 88888888 RB_SAMPLE_POS: 0x88888888 1431 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 1432 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 1433 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 1434 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 1435 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 1436 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 1437 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 1438 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 1439 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 1440 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 1441 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 1442 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 1443 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 1444 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 1445 + 0000ffff PA_SC_AA_MASK: 0xffff 1446 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 1447 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 1448 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 1449 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 14500122e25c: 0000: c0012200 00000000 00040085 1451 write CP_SCRATCH_REG7 (057f) 1452NEEDS WFI: CP_SCRATCH_REG7 (57f) 1453 CP_SCRATCH_REG7: 24 1454 :0,0,27,24 14550122e268: 0000: 0000057f 00000018 1456 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 14570122e270: 0000: c0002600 00000000 1458 opcode: CP_EVENT_WRITE (46) (2 dwords) 1459 { EVENT = CACHE_FLUSH } 1460 event CACHE_FLUSH 14610122e278: 0000: c0004600 00000006 1462 opcode: CP_EVENT_WRITE (46) (2 dwords) 1463 { EVENT = CACHE_FLUSH } 1464 event CACHE_FLUSH 14650122e280: 0000: c0004600 00000006 1466 opcode: CP_EVENT_WRITE (46) (2 dwords) 1467 { EVENT = CACHE_FLUSH } 1468 event CACHE_FLUSH 14690122e288: 0000: c0004600 00000006 1470 opcode: CP_EVENT_WRITE (46) (2 dwords) 1471 { EVENT = CACHE_FLUSH } 1472 event CACHE_FLUSH 14730122e290: 0000: c0004600 00000006 1474 opcode: CP_EVENT_WRITE (46) (2 dwords) 1475 { EVENT = CACHE_FLUSH } 1476 event CACHE_FLUSH 14770122e298: 0000: c0004600 00000006 1478 opcode: CP_EVENT_WRITE (46) (2 dwords) 1479 { EVENT = CACHE_FLUSH } 1480 event CACHE_FLUSH 14810122e2a0: 0000: c0004600 00000006 1482 opcode: CP_EVENT_WRITE (46) (2 dwords) 1483 { EVENT = CACHE_FLUSH } 1484 event CACHE_FLUSH 14850122e2a8: 0000: c0004600 00000006 1486 opcode: CP_EVENT_WRITE (46) (2 dwords) 1487 { EVENT = CACHE_FLUSH } 1488 event CACHE_FLUSH 14890122e2b0: 0000: c0004600 00000006 1490 opcode: CP_EVENT_WRITE (46) (2 dwords) 1491 { EVENT = CACHE_FLUSH } 1492 event CACHE_FLUSH 14930122e2b8: 0000: c0004600 00000006 1494 opcode: CP_EVENT_WRITE (46) (2 dwords) 1495 { EVENT = CACHE_FLUSH } 1496 event CACHE_FLUSH 14970122e2c0: 0000: c0004600 00000006 1498 opcode: CP_EVENT_WRITE (46) (2 dwords) 1499 { EVENT = CACHE_FLUSH } 1500 event CACHE_FLUSH 15010122e2c8: 0000: c0004600 00000006 1502 opcode: CP_EVENT_WRITE (46) (2 dwords) 1503 { EVENT = CACHE_FLUSH } 1504 event CACHE_FLUSH 15050122e2d0: 0000: c0004600 00000006 15060122f1d8: 0000: c0013700 0122e000 000000b6 1507 nop 1508 write CP_SCRATCH_REG6 (057e) 1509 CP_SCRATCH_REG6: 28 1510 :0,0,28,24 15110122f1e8: 0000: 0000057e 0000001c 1512############################################################ 1513vertices: 0 1514cmd: deqp-gles2/185: fence=1254 1515############################################################ 1516cmdstream[4]: 124 dwords 1517 write RB_BC_CONTROL (0f01) 1518 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 15190122d000: 0000: 00000f01 1c004046 1520 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1521 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 15220122d008: 0000: c0012d00 00040293 00000020 1523 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1524 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 15250122d014: 0000: c0012d00 00040316 00000002 1526 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1527 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 15280122d020: 0000: c0012d00 00040317 00000002 1529 write CP_PERFMON_CNTL (0444) 1530 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 15310122d02c: 0000: 00000444 00000000 1532 write RBBM_PM_OVERRIDE1 (039c) 1533 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 1534 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 15350122d034: 0000: 0001039c ffffffff 00000fff 1536 write TP0_CHICKEN (0e1e) 1537 TP0_CHICKEN: 0x2 15380122d040: 0000: 00000e1e 00000002 1539 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 15400122d048: 0000: c0003b00 00007fff 1541 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1542 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 15430122d050: 0000: c0012d00 00040307 00100020 1544 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1545 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 15460122d05c: 0000: c0012d00 00040308 000e0120 1547 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1548 VGT_MAX_VTX_INDX: 0xffffffff 1549 VGT_MIN_VTX_INDX: 0 15500122d068: 0000: c0022d00 00040100 ffffffff 00000000 1551 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1552 VGT_INDX_OFFSET: 0 15530122d078: 0000: c0012d00 00040102 00000000 1554 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1555 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 15560122d084: 0000: c0012d00 00040181 00000004 1557 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1558 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 15590122d090: 0000: c0012d00 00040182 ffffffff 1560 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1561 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 15620122d09c: 0000: c0012d00 00040301 00000000 1563 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1564 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 15650122d0a8: 0000: c0012d00 00040300 00000000 1566 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1567 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 15680122d0b4: 0000: c0012d00 00040080 00000000 1569 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1570 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 15710122d0c0: 0000: c0012d00 00040208 00000004 1572 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1573 RB_SAMPLE_POS: 0x88888888 15740122d0cc: 0000: c0012d00 0004020a 88888888 1575 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1576 RB_COLOR_DEST_MASK: 0xffffffff 15770122d0d8: 0000: c0012d00 00040326 ffffffff 1578 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1579 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 15800122d0e4: 0000: c0012d00 0004031b 0003c000 1581 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1582 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 1583 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 15840122d0f0: 0000: c0022d00 00040183 00000000 00000000 1585 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 15860122d100: 0000: c0004b00 00000000 1587 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 15880122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001 1589 write SQ_INST_STORE_MANAGMENT (0d02) 1590 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 15910122d11c: 0000: 00000d02 00000180 1592 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 15930122d124: 0000: c0003b00 00000300 1594 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 15950122d12c: 0000: c0004a00 80000180 1596 opcode: CP_SET_CONSTANT (2d) (14 dwords) 15970122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 15980122d15c: 2.000000 0.750000 0.375000 0.250000 15990122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 16000122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 1601 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1602 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 16030122d16c: 0000: c0012d00 00040104 0000000f 1604 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1605 RB_BLEND_RED: 0 1606 RB_BLEND_GREEN: 0 1607 RB_BLEND_BLUE: 0 1608 RB_BLEND_ALPHA: 0xff 16090122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 1610 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1611 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 16120122d190: 0000: c0012d00 00040206 0000043f 1613 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1614 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 16150122d19c: 0000: c0012d00 00040000 00000020 1616 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1617 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1248000 } 16180122d1a8: 0000: c0012d00 00040001 01248009 1619 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1620 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 1621 PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 } 16220122d1b4: 0000: c0022d00 0004000e 80000000 00080004 1623 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1624 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 16250122d1c4: 0000: c0012d00 00040080 00000000 1626 write CP_SCRATCH_REG6 (057e) 1627 CP_SCRATCH_REG6: 33 1628 :0,0,33,24 16290122d1d0: 0000: 0000057e 00000021 1630 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 1631 ibaddr:0122e000 1632 ibsize:000000b6 1633 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1634 set shader const 0078 16350122e000: 0000: c0042d00 00010078 0112d203 00100000 0112d203 00100000 1636 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1637 PA_SC_AA_MASK: 0xffff 16380122e018: 0000: c0012d00 00040312 0000ffff 1639 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1640 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 16410122e024: 0000: c0012d00 00040200 00000000 1642 opcode: CP_SET_CONSTANT (2d) (5 dwords) 1643 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1644 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1645 RB_ALPHA_REF: 0 16460122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 1647 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1648 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 1649 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 16500122e044: 0000: c0022d00 00040204 00000000 00090244 1651 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1652 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 1653 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 1654 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 1655 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 16560122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 1657 opcode: CP_SET_CONSTANT (2d) (7 dwords) 1658 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 1659 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 1660 PA_CL_GB_VERT_DISC_ADJ: 1.000000 1661 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 1662 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 16630122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 1664 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1665 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 1666 PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 } 16670122e088: 0000: c0022d00 00040081 00000000 00080004 1668 opcode: CP_SET_CONSTANT (2d) (8 dwords) 1669 PA_CL_VPORT_XSCALE: 2.000000 1670 PA_CL_VPORT_XOFFSET: 2.000000 1671 PA_CL_VPORT_YSCALE: 4.000000 1672 PA_CL_VPORT_YOFFSET: 4.000000 1673 PA_CL_VPORT_ZSCALE: 0.000000 1674 PA_CL_VPORT_ZOFFSET: 0.000000 16750122e098: 0000: c0062d00 0004010f 40000000 40000000 40800000 40800000 00000000 00000000 1676 opcode: CP_SET_CONSTANT (2d) (10 dwords) 16770122e0c0: 2.000000 4.000000 0.000000 0.000000 2.000000 4.000000 0.000000 0.000000 16780122e0b8: 0000: c0082d00 00000184 40000000 40800000 00000000 00000000 40000000 40800000 1679* 1680 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 1681 vertex shader, start=0000, size=0015 1682 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 1683 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 1684 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 1685 0000 0000 c200 ALLOC POSITION SIZE(0x0) 1686 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 1687 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 1688 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 1689 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 1690 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 1691 0000 0000 0000 NOP 16920122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 16930122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 16940122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 1695 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 1696 fragment shader, start=0000, size=000c 1697 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 1698 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 1699 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 1700 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 1701 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 1702 0000 0000 0000 NOP 17030122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 17040122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 1705 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1706 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 17070122e17c: 0000: c0012d00 00040181 00000106 1708 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1709 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 17100122e188: 0000: c0012d00 00040180 10030002 1711 opcode: CP_SET_CONSTANT (2d) (6 dwords) 17120122e19c: 0.000000 0.000000 0.000000 0.000000 17130122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 1714 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1715 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 17160122e1ac: 0000: c0012d00 00040202 00000c20 1717 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1718 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 17190122e1b8: 0000: c0012d00 00040201 00000000 1720 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1721 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 17220122e1c4: 0000: c0012d00 00040104 0000000f 1723 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1724 RB_BLEND_RED: 0 1725 RB_BLEND_GREEN: 0 1726 RB_BLEND_BLUE: 0 1727 RB_BLEND_ALPHA: 0 17280122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 1729 opcode: CP_SET_CONSTANT (2d) (8 dwords) 1730 set texture const 0000 1731 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 1732 filter min/mag: point/point 1733 swizzle: xyzw 1734 addr=01254000 (flags=820), size=4x8, pitch=32, format=FMT_1_REVERSE 1735 mipaddr=00000000 (flags=200) 17360122e1e8: 0000: c0062d00 00010000 00424800 01254820 0000e003 00000d11 00000000 00000200 1737 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1738 VGT_INDX_OFFSET: 0 17390122e208: 0000: c0012d00 00040102 00000000 1740 write TC_CNTL_STATUS (0e00) 1741 TC_CNTL_STATUS: { L2_INVALIDATE } 17420122e214: 0000: 00000e00 00000001 1743 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 17440122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 1745 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 17460122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 1747 write CP_SCRATCH_REG7 (057f) 1748 CP_SCRATCH_REG7: 29 1749 :0,0,33,29 17500122e24c: 0000: 0000057f 0000001d 1751 opcode: CP_NOP (10) (2 dwords) 17520122e254: 0000: c0001000 00000000 1753 opcode: CP_DRAW_INDX (22) (3 dwords) 1754 { VIZ_QUERY = 0 } 1755 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 1756 draw: 0 1757 prim_type: DI_PT_TRIFAN (5) 1758 source_select: DI_SRC_SEL_AUTO_INDEX (2) 1759 num_indices: 1407 1760 draw[4] register values 1761 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 1762 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 1763 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 1764!+ 00000021 CP_SCRATCH_REG6: 33 1765 :0,0,33,29 1766!+ 0000001d CP_SCRATCH_REG7: 29 1767 :0,0,33,29 1768 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 1769 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 1770 + 00000002 TP0_CHICKEN: 0x2 1771 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 1772 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 1773!+ 01248009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1248000 } 1774 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 1775!+ 00080004 PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 } 1776 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 1777 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 1778!+ 00080004 PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 } 1779 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 1780 + 00000000 VGT_MIN_VTX_INDX: 0 1781 + 00000000 VGT_INDX_OFFSET: 0 1782 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 1783 + 00000000 RB_BLEND_RED: 0 1784 + 00000000 RB_BLEND_GREEN: 0 1785 + 00000000 RB_BLEND_BLUE: 0 1786 + 00000000 RB_BLEND_ALPHA: 0 1787 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1788 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1789 + 00000000 RB_ALPHA_REF: 0 1790!+ 40000000 PA_CL_VPORT_XSCALE: 2.000000 1791!+ 40000000 PA_CL_VPORT_XOFFSET: 2.000000 1792!+ 40800000 PA_CL_VPORT_YSCALE: 4.000000 1793!+ 40800000 PA_CL_VPORT_YOFFSET: 4.000000 1794 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 1795 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 1796 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 1797 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 1798 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 1799 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 1800 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 1801 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 1802 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 1803 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 1804 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 1805 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 1806 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 1807 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 1808 + 88888888 RB_SAMPLE_POS: 0x88888888 1809 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 1810 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 1811 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 1812 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 1813 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 1814 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 1815 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 1816 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 1817 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 1818 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 1819 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 1820 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 1821 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 1822 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 1823 + 0000ffff PA_SC_AA_MASK: 0xffff 1824 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 1825 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 1826 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 1827 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 18280122e25c: 0000: c0012200 00000000 00040085 1829 write CP_SCRATCH_REG7 (057f) 1830NEEDS WFI: CP_SCRATCH_REG7 (57f) 1831 CP_SCRATCH_REG7: 30 1832 :0,0,33,30 18330122e268: 0000: 0000057f 0000001e 1834 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 18350122e270: 0000: c0002600 00000000 1836 opcode: CP_EVENT_WRITE (46) (2 dwords) 1837 { EVENT = CACHE_FLUSH } 1838 event CACHE_FLUSH 18390122e278: 0000: c0004600 00000006 1840 opcode: CP_EVENT_WRITE (46) (2 dwords) 1841 { EVENT = CACHE_FLUSH } 1842 event CACHE_FLUSH 18430122e280: 0000: c0004600 00000006 1844 opcode: CP_EVENT_WRITE (46) (2 dwords) 1845 { EVENT = CACHE_FLUSH } 1846 event CACHE_FLUSH 18470122e288: 0000: c0004600 00000006 1848 opcode: CP_EVENT_WRITE (46) (2 dwords) 1849 { EVENT = CACHE_FLUSH } 1850 event CACHE_FLUSH 18510122e290: 0000: c0004600 00000006 1852 opcode: CP_EVENT_WRITE (46) (2 dwords) 1853 { EVENT = CACHE_FLUSH } 1854 event CACHE_FLUSH 18550122e298: 0000: c0004600 00000006 1856 opcode: CP_EVENT_WRITE (46) (2 dwords) 1857 { EVENT = CACHE_FLUSH } 1858 event CACHE_FLUSH 18590122e2a0: 0000: c0004600 00000006 1860 opcode: CP_EVENT_WRITE (46) (2 dwords) 1861 { EVENT = CACHE_FLUSH } 1862 event CACHE_FLUSH 18630122e2a8: 0000: c0004600 00000006 1864 opcode: CP_EVENT_WRITE (46) (2 dwords) 1865 { EVENT = CACHE_FLUSH } 1866 event CACHE_FLUSH 18670122e2b0: 0000: c0004600 00000006 1868 opcode: CP_EVENT_WRITE (46) (2 dwords) 1869 { EVENT = CACHE_FLUSH } 1870 event CACHE_FLUSH 18710122e2b8: 0000: c0004600 00000006 1872 opcode: CP_EVENT_WRITE (46) (2 dwords) 1873 { EVENT = CACHE_FLUSH } 1874 event CACHE_FLUSH 18750122e2c0: 0000: c0004600 00000006 1876 opcode: CP_EVENT_WRITE (46) (2 dwords) 1877 { EVENT = CACHE_FLUSH } 1878 event CACHE_FLUSH 18790122e2c8: 0000: c0004600 00000006 1880 opcode: CP_EVENT_WRITE (46) (2 dwords) 1881 { EVENT = CACHE_FLUSH } 1882 event CACHE_FLUSH 18830122e2d0: 0000: c0004600 00000006 18840122d1d8: 0000: c0013700 0122e000 000000b6 1885 nop 1886 write CP_SCRATCH_REG6 (057e) 1887 CP_SCRATCH_REG6: 34 1888 :0,0,34,30 18890122d1e8: 0000: 0000057e 00000022 1890############################################################ 1891vertices: 0 1892cmd: deqp-gles2/185: fence=1255 1893############################################################ 1894cmdstream[5]: 124 dwords 1895 write RB_BC_CONTROL (0f01) 1896 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 18970122f000: 0000: 00000f01 1c004046 1898 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1899 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 19000122f008: 0000: c0012d00 00040293 00000020 1901 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1902 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 19030122f014: 0000: c0012d00 00040316 00000002 1904 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1905 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 19060122f020: 0000: c0012d00 00040317 00000002 1907 write CP_PERFMON_CNTL (0444) 1908 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 19090122f02c: 0000: 00000444 00000000 1910 write RBBM_PM_OVERRIDE1 (039c) 1911 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 1912 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 19130122f034: 0000: 0001039c ffffffff 00000fff 1914 write TP0_CHICKEN (0e1e) 1915 TP0_CHICKEN: 0x2 19160122f040: 0000: 00000e1e 00000002 1917 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 19180122f048: 0000: c0003b00 00007fff 1919 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1920 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 19210122f050: 0000: c0012d00 00040307 00100020 1922 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1923 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 19240122f05c: 0000: c0012d00 00040308 000e0120 1925 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1926 VGT_MAX_VTX_INDX: 0xffffffff 1927 VGT_MIN_VTX_INDX: 0 19280122f068: 0000: c0022d00 00040100 ffffffff 00000000 1929 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1930 VGT_INDX_OFFSET: 0 19310122f078: 0000: c0012d00 00040102 00000000 1932 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1933 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 19340122f084: 0000: c0012d00 00040181 00000004 1935 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1936 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 19370122f090: 0000: c0012d00 00040182 ffffffff 1938 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1939 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 19400122f09c: 0000: c0012d00 00040301 00000000 1941 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1942 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 19430122f0a8: 0000: c0012d00 00040300 00000000 1944 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1945 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 19460122f0b4: 0000: c0012d00 00040080 00000000 1947 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1948 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 19490122f0c0: 0000: c0012d00 00040208 00000004 1950 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1951 RB_SAMPLE_POS: 0x88888888 19520122f0cc: 0000: c0012d00 0004020a 88888888 1953 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1954 RB_COLOR_DEST_MASK: 0xffffffff 19550122f0d8: 0000: c0012d00 00040326 ffffffff 1956 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1957 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 19580122f0e4: 0000: c0012d00 0004031b 0003c000 1959 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1960 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 1961 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 19620122f0f0: 0000: c0022d00 00040183 00000000 00000000 1963 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 19640122f100: 0000: c0004b00 00000000 1965 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 19660122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001 1967 write SQ_INST_STORE_MANAGMENT (0d02) 1968 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 19690122f11c: 0000: 00000d02 00000180 1970 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 19710122f124: 0000: c0003b00 00000300 1972 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 19730122f12c: 0000: c0004a00 80000180 1974 opcode: CP_SET_CONSTANT (2d) (14 dwords) 19750122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 19760122f15c: 2.000000 0.750000 0.375000 0.250000 19770122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 19780122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 1979 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1980 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 19810122f16c: 0000: c0012d00 00040104 0000000f 1982 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1983 RB_BLEND_RED: 0 1984 RB_BLEND_GREEN: 0 1985 RB_BLEND_BLUE: 0 1986 RB_BLEND_ALPHA: 0xff 19870122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 1988 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1989 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 19900122f190: 0000: c0012d00 00040206 0000043f 1991 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1992 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 19930122f19c: 0000: c0012d00 00040000 00000020 1994 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1995 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124a000 } 19960122f1a8: 0000: c0012d00 00040001 0124a009 1997 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1998 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 1999 PA_SC_SCREEN_SCISSOR_BR: { X = 2 | Y = 4 } 20000122f1b4: 0000: c0022d00 0004000e 80000000 00040002 2001 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2002 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 20030122f1c4: 0000: c0012d00 00040080 00000000 2004 write CP_SCRATCH_REG6 (057e) 2005 CP_SCRATCH_REG6: 39 2006 :0,0,39,30 20070122f1d0: 0000: 0000057e 00000027 2008 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 2009 ibaddr:0122e000 2010 ibsize:000000b6 2011 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2012 set shader const 0078 20130122e000: 0000: c0042d00 00010078 0112d283 00100000 0112d283 00100000 2014 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2015 PA_SC_AA_MASK: 0xffff 20160122e018: 0000: c0012d00 00040312 0000ffff 2017 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2018 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 20190122e024: 0000: c0012d00 00040200 00000000 2020 opcode: CP_SET_CONSTANT (2d) (5 dwords) 2021 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2022 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2023 RB_ALPHA_REF: 0 20240122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 2025 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2026 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 2027 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 20280122e044: 0000: c0022d00 00040204 00000000 00090244 2029 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2030 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 2031 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 2032 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 2033 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 20340122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 2035 opcode: CP_SET_CONSTANT (2d) (7 dwords) 2036 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 2037 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 2038 PA_CL_GB_VERT_DISC_ADJ: 1.000000 2039 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 2040 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 20410122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 2042 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2043 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 2044 PA_SC_WINDOW_SCISSOR_BR: { X = 2 | Y = 4 } 20450122e088: 0000: c0022d00 00040081 00000000 00040002 2046 opcode: CP_SET_CONSTANT (2d) (8 dwords) 2047 PA_CL_VPORT_XSCALE: 1.000000 2048 PA_CL_VPORT_XOFFSET: 1.000000 2049 PA_CL_VPORT_YSCALE: 2.000000 2050 PA_CL_VPORT_YOFFSET: 2.000000 2051 PA_CL_VPORT_ZSCALE: 0.000000 2052 PA_CL_VPORT_ZOFFSET: 0.000000 20530122e098: 0000: c0062d00 0004010f 3f800000 3f800000 40000000 40000000 00000000 00000000 2054 opcode: CP_SET_CONSTANT (2d) (10 dwords) 20550122e0c0: 1.000000 2.000000 0.000000 0.000000 1.000000 2.000000 0.000000 0.000000 20560122e0b8: 0000: c0082d00 00000184 3f800000 40000000 00000000 00000000 3f800000 40000000 2057* 2058 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 2059 vertex shader, start=0000, size=0015 2060 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 2061 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 2062 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 2063 0000 0000 c200 ALLOC POSITION SIZE(0x0) 2064 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 2065 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 2066 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 2067 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 2068 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 2069 0000 0000 0000 NOP 20700122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 20710122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 20720122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 2073 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 2074 fragment shader, start=0000, size=000c 2075 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 2076 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 2077 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 2078 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 2079 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 2080 0000 0000 0000 NOP 20810122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 20820122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 2083 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2084 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 20850122e17c: 0000: c0012d00 00040181 00000106 2086 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2087 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 20880122e188: 0000: c0012d00 00040180 10030002 2089 opcode: CP_SET_CONSTANT (2d) (6 dwords) 20900122e19c: 0.000000 0.000000 0.000000 0.000000 20910122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 2092 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2093 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 20940122e1ac: 0000: c0012d00 00040202 00000c20 2095 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2096 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 20970122e1b8: 0000: c0012d00 00040201 00000000 2098 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2099 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 21000122e1c4: 0000: c0012d00 00040104 0000000f 2101 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2102 RB_BLEND_RED: 0 2103 RB_BLEND_GREEN: 0 2104 RB_BLEND_BLUE: 0 2105 RB_BLEND_ALPHA: 0 21060122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 2107 opcode: CP_SET_CONSTANT (2d) (8 dwords) 2108 set texture const 0000 2109 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 2110 filter min/mag: point/point 2111 swizzle: xyzw 2112 addr=01254000 (flags=820), size=2x4, pitch=32, format=FMT_1_REVERSE 2113 mipaddr=00000000 (flags=200) 21140122e1e8: 0000: c0062d00 00010000 00424800 01254820 00006001 00000d11 00000000 00000200 2115 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2116 VGT_INDX_OFFSET: 0 21170122e208: 0000: c0012d00 00040102 00000000 2118 write TC_CNTL_STATUS (0e00) 2119 TC_CNTL_STATUS: { L2_INVALIDATE } 21200122e214: 0000: 00000e00 00000001 2121 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 21220122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 2123 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 21240122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 2125 write CP_SCRATCH_REG7 (057f) 2126 CP_SCRATCH_REG7: 35 2127 :0,0,39,35 21280122e24c: 0000: 0000057f 00000023 2129 opcode: CP_NOP (10) (2 dwords) 21300122e254: 0000: c0001000 00000000 2131 opcode: CP_DRAW_INDX (22) (3 dwords) 2132 { VIZ_QUERY = 0 } 2133 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 2134 draw: 0 2135 prim_type: DI_PT_TRIFAN (5) 2136 source_select: DI_SRC_SEL_AUTO_INDEX (2) 2137 num_indices: 1407 2138 draw[5] register values 2139 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 2140 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 2141 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 2142!+ 00000027 CP_SCRATCH_REG6: 39 2143 :0,0,39,35 2144!+ 00000023 CP_SCRATCH_REG7: 35 2145 :0,0,39,35 2146 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 2147 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 2148 + 00000002 TP0_CHICKEN: 0x2 2149 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 2150 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 2151!+ 0124a009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124a000 } 2152 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 2153!+ 00040002 PA_SC_SCREEN_SCISSOR_BR: { X = 2 | Y = 4 } 2154 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 2155 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 2156!+ 00040002 PA_SC_WINDOW_SCISSOR_BR: { X = 2 | Y = 4 } 2157 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 2158 + 00000000 VGT_MIN_VTX_INDX: 0 2159 + 00000000 VGT_INDX_OFFSET: 0 2160 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 2161 + 00000000 RB_BLEND_RED: 0 2162 + 00000000 RB_BLEND_GREEN: 0 2163 + 00000000 RB_BLEND_BLUE: 0 2164 + 00000000 RB_BLEND_ALPHA: 0 2165 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2166 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2167 + 00000000 RB_ALPHA_REF: 0 2168!+ 3f800000 PA_CL_VPORT_XSCALE: 1.000000 2169!+ 3f800000 PA_CL_VPORT_XOFFSET: 1.000000 2170!+ 40000000 PA_CL_VPORT_YSCALE: 2.000000 2171!+ 40000000 PA_CL_VPORT_YOFFSET: 2.000000 2172 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 2173 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 2174 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 2175 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 2176 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 2177 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 2178 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 2179 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 2180 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 2181 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 2182 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 2183 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 2184 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 2185 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 2186 + 88888888 RB_SAMPLE_POS: 0x88888888 2187 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 2188 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 2189 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 2190 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 2191 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 2192 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 2193 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 2194 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 2195 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 2196 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 2197 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 2198 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 2199 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 2200 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 2201 + 0000ffff PA_SC_AA_MASK: 0xffff 2202 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 2203 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 2204 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 2205 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 22060122e25c: 0000: c0012200 00000000 00040085 2207 write CP_SCRATCH_REG7 (057f) 2208NEEDS WFI: CP_SCRATCH_REG7 (57f) 2209 CP_SCRATCH_REG7: 36 2210 :0,0,39,36 22110122e268: 0000: 0000057f 00000024 2212 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 22130122e270: 0000: c0002600 00000000 2214 opcode: CP_EVENT_WRITE (46) (2 dwords) 2215 { EVENT = CACHE_FLUSH } 2216 event CACHE_FLUSH 22170122e278: 0000: c0004600 00000006 2218 opcode: CP_EVENT_WRITE (46) (2 dwords) 2219 { EVENT = CACHE_FLUSH } 2220 event CACHE_FLUSH 22210122e280: 0000: c0004600 00000006 2222 opcode: CP_EVENT_WRITE (46) (2 dwords) 2223 { EVENT = CACHE_FLUSH } 2224 event CACHE_FLUSH 22250122e288: 0000: c0004600 00000006 2226 opcode: CP_EVENT_WRITE (46) (2 dwords) 2227 { EVENT = CACHE_FLUSH } 2228 event CACHE_FLUSH 22290122e290: 0000: c0004600 00000006 2230 opcode: CP_EVENT_WRITE (46) (2 dwords) 2231 { EVENT = CACHE_FLUSH } 2232 event CACHE_FLUSH 22330122e298: 0000: c0004600 00000006 2234 opcode: CP_EVENT_WRITE (46) (2 dwords) 2235 { EVENT = CACHE_FLUSH } 2236 event CACHE_FLUSH 22370122e2a0: 0000: c0004600 00000006 2238 opcode: CP_EVENT_WRITE (46) (2 dwords) 2239 { EVENT = CACHE_FLUSH } 2240 event CACHE_FLUSH 22410122e2a8: 0000: c0004600 00000006 2242 opcode: CP_EVENT_WRITE (46) (2 dwords) 2243 { EVENT = CACHE_FLUSH } 2244 event CACHE_FLUSH 22450122e2b0: 0000: c0004600 00000006 2246 opcode: CP_EVENT_WRITE (46) (2 dwords) 2247 { EVENT = CACHE_FLUSH } 2248 event CACHE_FLUSH 22490122e2b8: 0000: c0004600 00000006 2250 opcode: CP_EVENT_WRITE (46) (2 dwords) 2251 { EVENT = CACHE_FLUSH } 2252 event CACHE_FLUSH 22530122e2c0: 0000: c0004600 00000006 2254 opcode: CP_EVENT_WRITE (46) (2 dwords) 2255 { EVENT = CACHE_FLUSH } 2256 event CACHE_FLUSH 22570122e2c8: 0000: c0004600 00000006 2258 opcode: CP_EVENT_WRITE (46) (2 dwords) 2259 { EVENT = CACHE_FLUSH } 2260 event CACHE_FLUSH 22610122e2d0: 0000: c0004600 00000006 22620122f1d8: 0000: c0013700 0122e000 000000b6 2263 nop 2264 write CP_SCRATCH_REG6 (057e) 2265 CP_SCRATCH_REG6: 40 2266 :0,0,40,36 22670122f1e8: 0000: 0000057e 00000028 2268############################################################ 2269vertices: 0 2270cmd: deqp-gles2/185: fence=1256 2271############################################################ 2272cmdstream[6]: 124 dwords 2273 write RB_BC_CONTROL (0f01) 2274 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 22750122d000: 0000: 00000f01 1c004046 2276 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2277 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 22780122d008: 0000: c0012d00 00040293 00000020 2279 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2280 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 22810122d014: 0000: c0012d00 00040316 00000002 2282 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2283 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 22840122d020: 0000: c0012d00 00040317 00000002 2285 write CP_PERFMON_CNTL (0444) 2286 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 22870122d02c: 0000: 00000444 00000000 2288 write RBBM_PM_OVERRIDE1 (039c) 2289 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 2290 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 22910122d034: 0000: 0001039c ffffffff 00000fff 2292 write TP0_CHICKEN (0e1e) 2293 TP0_CHICKEN: 0x2 22940122d040: 0000: 00000e1e 00000002 2295 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 22960122d048: 0000: c0003b00 00007fff 2297 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2298 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 22990122d050: 0000: c0012d00 00040307 00100020 2300 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2301 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 23020122d05c: 0000: c0012d00 00040308 000e0120 2303 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2304 VGT_MAX_VTX_INDX: 0xffffffff 2305 VGT_MIN_VTX_INDX: 0 23060122d068: 0000: c0022d00 00040100 ffffffff 00000000 2307 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2308 VGT_INDX_OFFSET: 0 23090122d078: 0000: c0012d00 00040102 00000000 2310 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2311 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 23120122d084: 0000: c0012d00 00040181 00000004 2313 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2314 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 23150122d090: 0000: c0012d00 00040182 ffffffff 2316 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2317 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 23180122d09c: 0000: c0012d00 00040301 00000000 2319 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2320 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 23210122d0a8: 0000: c0012d00 00040300 00000000 2322 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2323 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 23240122d0b4: 0000: c0012d00 00040080 00000000 2325 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2326 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 23270122d0c0: 0000: c0012d00 00040208 00000004 2328 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2329 RB_SAMPLE_POS: 0x88888888 23300122d0cc: 0000: c0012d00 0004020a 88888888 2331 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2332 RB_COLOR_DEST_MASK: 0xffffffff 23330122d0d8: 0000: c0012d00 00040326 ffffffff 2334 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2335 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 23360122d0e4: 0000: c0012d00 0004031b 0003c000 2337 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2338 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 2339 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 23400122d0f0: 0000: c0022d00 00040183 00000000 00000000 2341 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 23420122d100: 0000: c0004b00 00000000 2343 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 23440122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001 2345 write SQ_INST_STORE_MANAGMENT (0d02) 2346 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 23470122d11c: 0000: 00000d02 00000180 2348 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 23490122d124: 0000: c0003b00 00000300 2350 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 23510122d12c: 0000: c0004a00 80000180 2352 opcode: CP_SET_CONSTANT (2d) (14 dwords) 23530122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 23540122d15c: 2.000000 0.750000 0.375000 0.250000 23550122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 23560122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 2357 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2358 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 23590122d16c: 0000: c0012d00 00040104 0000000f 2360 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2361 RB_BLEND_RED: 0 2362 RB_BLEND_GREEN: 0 2363 RB_BLEND_BLUE: 0 2364 RB_BLEND_ALPHA: 0xff 23650122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 2366 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2367 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 23680122d190: 0000: c0012d00 00040206 0000043f 2369 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2370 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 23710122d19c: 0000: c0012d00 00040000 00000020 2372 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2373 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124c000 } 23740122d1a8: 0000: c0012d00 00040001 0124c009 2375 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2376 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 2377 PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 2 } 23780122d1b4: 0000: c0022d00 0004000e 80000000 00020001 2379 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2380 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 23810122d1c4: 0000: c0012d00 00040080 00000000 2382 write CP_SCRATCH_REG6 (057e) 2383 CP_SCRATCH_REG6: 45 2384 :0,0,45,36 23850122d1d0: 0000: 0000057e 0000002d 2386 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 2387 ibaddr:0122e000 2388 ibsize:000000b6 2389 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2390 set shader const 0078 23910122e000: 0000: c0042d00 00010078 0112d303 00100000 0112d303 00100000 2392 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2393 PA_SC_AA_MASK: 0xffff 23940122e018: 0000: c0012d00 00040312 0000ffff 2395 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2396 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 23970122e024: 0000: c0012d00 00040200 00000000 2398 opcode: CP_SET_CONSTANT (2d) (5 dwords) 2399 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2400 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2401 RB_ALPHA_REF: 0 24020122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 2403 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2404 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 2405 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 24060122e044: 0000: c0022d00 00040204 00000000 00090244 2407 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2408 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 2409 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 2410 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 2411 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 24120122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 2413 opcode: CP_SET_CONSTANT (2d) (7 dwords) 2414 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 2415 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 2416 PA_CL_GB_VERT_DISC_ADJ: 1.000000 2417 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 2418 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 24190122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 2420 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2421 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 2422 PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 2 } 24230122e088: 0000: c0022d00 00040081 00000000 00020001 2424 opcode: CP_SET_CONSTANT (2d) (8 dwords) 2425 PA_CL_VPORT_XSCALE: 0.500000 2426 PA_CL_VPORT_XOFFSET: 0.500000 2427 PA_CL_VPORT_YSCALE: 1.000000 2428 PA_CL_VPORT_YOFFSET: 1.000000 2429 PA_CL_VPORT_ZSCALE: 0.000000 2430 PA_CL_VPORT_ZOFFSET: 0.000000 24310122e098: 0000: c0062d00 0004010f 3f000000 3f000000 3f800000 3f800000 00000000 00000000 2432 opcode: CP_SET_CONSTANT (2d) (10 dwords) 24330122e0c0: 0.500000 1.000000 0.000000 0.000000 0.500000 1.000000 0.000000 0.000000 24340122e0b8: 0000: c0082d00 00000184 3f000000 3f800000 00000000 00000000 3f000000 3f800000 2435* 2436 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 2437 vertex shader, start=0000, size=0015 2438 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 2439 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 2440 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 2441 0000 0000 c200 ALLOC POSITION SIZE(0x0) 2442 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 2443 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 2444 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 2445 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 2446 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 2447 0000 0000 0000 NOP 24480122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 24490122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 24500122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 2451 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 2452 fragment shader, start=0000, size=000c 2453 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 2454 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 2455 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 2456 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 2457 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 2458 0000 0000 0000 NOP 24590122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 24600122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 2461 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2462 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 24630122e17c: 0000: c0012d00 00040181 00000106 2464 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2465 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 24660122e188: 0000: c0012d00 00040180 10030002 2467 opcode: CP_SET_CONSTANT (2d) (6 dwords) 24680122e19c: 0.000000 0.000000 0.000000 0.000000 24690122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 2470 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2471 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 24720122e1ac: 0000: c0012d00 00040202 00000c20 2473 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2474 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 24750122e1b8: 0000: c0012d00 00040201 00000000 2476 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2477 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 24780122e1c4: 0000: c0012d00 00040104 0000000f 2479 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2480 RB_BLEND_RED: 0 2481 RB_BLEND_GREEN: 0 2482 RB_BLEND_BLUE: 0 2483 RB_BLEND_ALPHA: 0 24840122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 2485 opcode: CP_SET_CONSTANT (2d) (8 dwords) 2486 set texture const 0000 2487 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 2488 filter min/mag: point/point 2489 swizzle: xyzw 2490 addr=01254000 (flags=820), size=1x2, pitch=32, format=FMT_1_REVERSE 2491 mipaddr=00000000 (flags=200) 24920122e1e8: 0000: c0062d00 00010000 00424800 01254820 00002000 00000d11 00000000 00000200 2493 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2494 VGT_INDX_OFFSET: 0 24950122e208: 0000: c0012d00 00040102 00000000 2496 write TC_CNTL_STATUS (0e00) 2497 TC_CNTL_STATUS: { L2_INVALIDATE } 24980122e214: 0000: 00000e00 00000001 2499 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 25000122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 2501 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 25020122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 2503 write CP_SCRATCH_REG7 (057f) 2504 CP_SCRATCH_REG7: 41 2505 :0,0,45,41 25060122e24c: 0000: 0000057f 00000029 2507 opcode: CP_NOP (10) (2 dwords) 25080122e254: 0000: c0001000 00000000 2509 opcode: CP_DRAW_INDX (22) (3 dwords) 2510 { VIZ_QUERY = 0 } 2511 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 2512 draw: 0 2513 prim_type: DI_PT_TRIFAN (5) 2514 source_select: DI_SRC_SEL_AUTO_INDEX (2) 2515 num_indices: 1407 2516 draw[6] register values 2517 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 2518 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 2519 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 2520!+ 0000002d CP_SCRATCH_REG6: 45 2521 :0,0,45,41 2522!+ 00000029 CP_SCRATCH_REG7: 41 2523 :0,0,45,41 2524 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 2525 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 2526 + 00000002 TP0_CHICKEN: 0x2 2527 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 2528 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 2529!+ 0124c009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124c000 } 2530 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 2531!+ 00020001 PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 2 } 2532 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 2533 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 2534!+ 00020001 PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 2 } 2535 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 2536 + 00000000 VGT_MIN_VTX_INDX: 0 2537 + 00000000 VGT_INDX_OFFSET: 0 2538 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 2539 + 00000000 RB_BLEND_RED: 0 2540 + 00000000 RB_BLEND_GREEN: 0 2541 + 00000000 RB_BLEND_BLUE: 0 2542 + 00000000 RB_BLEND_ALPHA: 0 2543 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2544 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2545 + 00000000 RB_ALPHA_REF: 0 2546!+ 3f000000 PA_CL_VPORT_XSCALE: 0.500000 2547!+ 3f000000 PA_CL_VPORT_XOFFSET: 0.500000 2548!+ 3f800000 PA_CL_VPORT_YSCALE: 1.000000 2549!+ 3f800000 PA_CL_VPORT_YOFFSET: 1.000000 2550 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 2551 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 2552 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 2553 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 2554 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 2555 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 2556 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 2557 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 2558 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 2559 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 2560 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 2561 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 2562 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 2563 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 2564 + 88888888 RB_SAMPLE_POS: 0x88888888 2565 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 2566 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 2567 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 2568 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 2569 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 2570 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 2571 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 2572 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 2573 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 2574 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 2575 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 2576 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 2577 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 2578 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 2579 + 0000ffff PA_SC_AA_MASK: 0xffff 2580 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 2581 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 2582 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 2583 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 25840122e25c: 0000: c0012200 00000000 00040085 2585 write CP_SCRATCH_REG7 (057f) 2586NEEDS WFI: CP_SCRATCH_REG7 (57f) 2587 CP_SCRATCH_REG7: 42 2588 :0,0,45,42 25890122e268: 0000: 0000057f 0000002a 2590 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 25910122e270: 0000: c0002600 00000000 2592 opcode: CP_EVENT_WRITE (46) (2 dwords) 2593 { EVENT = CACHE_FLUSH } 2594 event CACHE_FLUSH 25950122e278: 0000: c0004600 00000006 2596 opcode: CP_EVENT_WRITE (46) (2 dwords) 2597 { EVENT = CACHE_FLUSH } 2598 event CACHE_FLUSH 25990122e280: 0000: c0004600 00000006 2600 opcode: CP_EVENT_WRITE (46) (2 dwords) 2601 { EVENT = CACHE_FLUSH } 2602 event CACHE_FLUSH 26030122e288: 0000: c0004600 00000006 2604 opcode: CP_EVENT_WRITE (46) (2 dwords) 2605 { EVENT = CACHE_FLUSH } 2606 event CACHE_FLUSH 26070122e290: 0000: c0004600 00000006 2608 opcode: CP_EVENT_WRITE (46) (2 dwords) 2609 { EVENT = CACHE_FLUSH } 2610 event CACHE_FLUSH 26110122e298: 0000: c0004600 00000006 2612 opcode: CP_EVENT_WRITE (46) (2 dwords) 2613 { EVENT = CACHE_FLUSH } 2614 event CACHE_FLUSH 26150122e2a0: 0000: c0004600 00000006 2616 opcode: CP_EVENT_WRITE (46) (2 dwords) 2617 { EVENT = CACHE_FLUSH } 2618 event CACHE_FLUSH 26190122e2a8: 0000: c0004600 00000006 2620 opcode: CP_EVENT_WRITE (46) (2 dwords) 2621 { EVENT = CACHE_FLUSH } 2622 event CACHE_FLUSH 26230122e2b0: 0000: c0004600 00000006 2624 opcode: CP_EVENT_WRITE (46) (2 dwords) 2625 { EVENT = CACHE_FLUSH } 2626 event CACHE_FLUSH 26270122e2b8: 0000: c0004600 00000006 2628 opcode: CP_EVENT_WRITE (46) (2 dwords) 2629 { EVENT = CACHE_FLUSH } 2630 event CACHE_FLUSH 26310122e2c0: 0000: c0004600 00000006 2632 opcode: CP_EVENT_WRITE (46) (2 dwords) 2633 { EVENT = CACHE_FLUSH } 2634 event CACHE_FLUSH 26350122e2c8: 0000: c0004600 00000006 2636 opcode: CP_EVENT_WRITE (46) (2 dwords) 2637 { EVENT = CACHE_FLUSH } 2638 event CACHE_FLUSH 26390122e2d0: 0000: c0004600 00000006 26400122d1d8: 0000: c0013700 0122e000 000000b6 2641 nop 2642 write CP_SCRATCH_REG6 (057e) 2643 CP_SCRATCH_REG6: 46 2644 :0,0,46,42 26450122d1e8: 0000: 0000057e 0000002e 2646############################################################ 2647vertices: 0 2648cmd: deqp-gles2/185: fence=1257 2649############################################################ 2650cmdstream[7]: 124 dwords 2651 write RB_BC_CONTROL (0f01) 2652 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 26530122f000: 0000: 00000f01 1c004046 2654 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2655 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 26560122f008: 0000: c0012d00 00040293 00000020 2657 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2658 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 26590122f014: 0000: c0012d00 00040316 00000002 2660 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2661 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 26620122f020: 0000: c0012d00 00040317 00000002 2663 write CP_PERFMON_CNTL (0444) 2664 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 26650122f02c: 0000: 00000444 00000000 2666 write RBBM_PM_OVERRIDE1 (039c) 2667 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 2668 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 26690122f034: 0000: 0001039c ffffffff 00000fff 2670 write TP0_CHICKEN (0e1e) 2671 TP0_CHICKEN: 0x2 26720122f040: 0000: 00000e1e 00000002 2673 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 26740122f048: 0000: c0003b00 00007fff 2675 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2676 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 26770122f050: 0000: c0012d00 00040307 00100020 2678 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2679 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 26800122f05c: 0000: c0012d00 00040308 000e0120 2681 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2682 VGT_MAX_VTX_INDX: 0xffffffff 2683 VGT_MIN_VTX_INDX: 0 26840122f068: 0000: c0022d00 00040100 ffffffff 00000000 2685 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2686 VGT_INDX_OFFSET: 0 26870122f078: 0000: c0012d00 00040102 00000000 2688 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2689 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 26900122f084: 0000: c0012d00 00040181 00000004 2691 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2692 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 26930122f090: 0000: c0012d00 00040182 ffffffff 2694 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2695 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 26960122f09c: 0000: c0012d00 00040301 00000000 2697 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2698 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 26990122f0a8: 0000: c0012d00 00040300 00000000 2700 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2701 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 27020122f0b4: 0000: c0012d00 00040080 00000000 2703 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2704 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 27050122f0c0: 0000: c0012d00 00040208 00000004 2706 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2707 RB_SAMPLE_POS: 0x88888888 27080122f0cc: 0000: c0012d00 0004020a 88888888 2709 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2710 RB_COLOR_DEST_MASK: 0xffffffff 27110122f0d8: 0000: c0012d00 00040326 ffffffff 2712 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2713 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 27140122f0e4: 0000: c0012d00 0004031b 0003c000 2715 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2716 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 2717 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 27180122f0f0: 0000: c0022d00 00040183 00000000 00000000 2719 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 27200122f100: 0000: c0004b00 00000000 2721 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 27220122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001 2723 write SQ_INST_STORE_MANAGMENT (0d02) 2724 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 27250122f11c: 0000: 00000d02 00000180 2726 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 27270122f124: 0000: c0003b00 00000300 2728 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 27290122f12c: 0000: c0004a00 80000180 2730 opcode: CP_SET_CONSTANT (2d) (14 dwords) 27310122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 27320122f15c: 2.000000 0.750000 0.375000 0.250000 27330122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 27340122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 2735 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2736 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 27370122f16c: 0000: c0012d00 00040104 0000000f 2738 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2739 RB_BLEND_RED: 0 2740 RB_BLEND_GREEN: 0 2741 RB_BLEND_BLUE: 0 2742 RB_BLEND_ALPHA: 0xff 27430122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 2744 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2745 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 27460122f190: 0000: c0012d00 00040206 0000043f 2747 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2748 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 27490122f19c: 0000: c0012d00 00040000 00000020 2750 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2751 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124e000 } 27520122f1a8: 0000: c0012d00 00040001 0124e009 2753 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2754 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 2755 PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 1 } 27560122f1b4: 0000: c0022d00 0004000e 80000000 00010001 2757 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2758 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 27590122f1c4: 0000: c0012d00 00040080 00000000 2760 write CP_SCRATCH_REG6 (057e) 2761 CP_SCRATCH_REG6: 51 2762 :0,0,51,42 27630122f1d0: 0000: 0000057e 00000033 2764 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 2765 ibaddr:0122e000 2766 ibsize:000000b6 2767 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2768 set shader const 0078 27690122e000: 0000: c0042d00 00010078 0112d383 00100000 0112d383 00100000 2770 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2771 PA_SC_AA_MASK: 0xffff 27720122e018: 0000: c0012d00 00040312 0000ffff 2773 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2774 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 27750122e024: 0000: c0012d00 00040200 00000000 2776 opcode: CP_SET_CONSTANT (2d) (5 dwords) 2777 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2778 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2779 RB_ALPHA_REF: 0 27800122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 2781 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2782 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 2783 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 27840122e044: 0000: c0022d00 00040204 00000000 00090244 2785 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2786 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 2787 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 2788 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 2789 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 27900122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 2791 opcode: CP_SET_CONSTANT (2d) (7 dwords) 2792 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 2793 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 2794 PA_CL_GB_VERT_DISC_ADJ: 1.000000 2795 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 2796 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 27970122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 2798 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2799 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 2800 PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 1 } 28010122e088: 0000: c0022d00 00040081 00000000 00010001 2802 opcode: CP_SET_CONSTANT (2d) (8 dwords) 2803 PA_CL_VPORT_XSCALE: 0.500000 2804 PA_CL_VPORT_XOFFSET: 0.500000 2805 PA_CL_VPORT_YSCALE: 0.500000 2806 PA_CL_VPORT_YOFFSET: 0.500000 2807 PA_CL_VPORT_ZSCALE: 0.000000 2808 PA_CL_VPORT_ZOFFSET: 0.000000 28090122e098: 0000: c0062d00 0004010f 3f000000 3f000000 3f000000 3f000000 00000000 00000000 2810 opcode: CP_SET_CONSTANT (2d) (10 dwords) 28110122e0c0: 0.500000 0.500000 0.000000 0.000000 0.500000 0.500000 0.000000 0.000000 28120122e0b8: 0000: c0082d00 00000184 3f000000 3f000000 00000000 00000000 3f000000 3f000000 2813* 2814 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 2815 vertex shader, start=0000, size=0015 2816 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 2817 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 2818 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 2819 0000 0000 c200 ALLOC POSITION SIZE(0x0) 2820 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 2821 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 2822 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 2823 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 2824 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 2825 0000 0000 0000 NOP 28260122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 28270122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 28280122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 2829 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 2830 fragment shader, start=0000, size=000c 2831 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 2832 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 2833 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 2834 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 2835 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 2836 0000 0000 0000 NOP 28370122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 28380122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 2839 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2840 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 28410122e17c: 0000: c0012d00 00040181 00000106 2842 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2843 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 28440122e188: 0000: c0012d00 00040180 10030002 2845 opcode: CP_SET_CONSTANT (2d) (6 dwords) 28460122e19c: 0.000000 0.000000 0.000000 0.000000 28470122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 2848 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2849 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 28500122e1ac: 0000: c0012d00 00040202 00000c20 2851 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2852 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 28530122e1b8: 0000: c0012d00 00040201 00000000 2854 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2855 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 28560122e1c4: 0000: c0012d00 00040104 0000000f 2857 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2858 RB_BLEND_RED: 0 2859 RB_BLEND_GREEN: 0 2860 RB_BLEND_BLUE: 0 2861 RB_BLEND_ALPHA: 0 28620122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 2863 opcode: CP_SET_CONSTANT (2d) (8 dwords) 2864 set texture const 0000 2865 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 2866 filter min/mag: point/point 2867 swizzle: xyzw 2868 addr=01254000 (flags=820), size=1x1, pitch=32, format=FMT_1_REVERSE 2869 mipaddr=00000000 (flags=200) 28700122e1e8: 0000: c0062d00 00010000 00424800 01254820 00000000 00000d11 00000000 00000200 2871 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2872 VGT_INDX_OFFSET: 0 28730122e208: 0000: c0012d00 00040102 00000000 2874 write TC_CNTL_STATUS (0e00) 2875 TC_CNTL_STATUS: { L2_INVALIDATE } 28760122e214: 0000: 00000e00 00000001 2877 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 28780122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 2879 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 28800122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 2881 write CP_SCRATCH_REG7 (057f) 2882 CP_SCRATCH_REG7: 47 2883 :0,0,51,47 28840122e24c: 0000: 0000057f 0000002f 2885 opcode: CP_NOP (10) (2 dwords) 28860122e254: 0000: c0001000 00000000 2887 opcode: CP_DRAW_INDX (22) (3 dwords) 2888 { VIZ_QUERY = 0 } 2889 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 2890 draw: 0 2891 prim_type: DI_PT_TRIFAN (5) 2892 source_select: DI_SRC_SEL_AUTO_INDEX (2) 2893 num_indices: 1407 2894 draw[7] register values 2895 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 2896 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 2897 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 2898!+ 00000033 CP_SCRATCH_REG6: 51 2899 :0,0,51,47 2900!+ 0000002f CP_SCRATCH_REG7: 47 2901 :0,0,51,47 2902 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 2903 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 2904 + 00000002 TP0_CHICKEN: 0x2 2905 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 2906 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 2907!+ 0124e009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124e000 } 2908 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 2909!+ 00010001 PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 1 } 2910 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 2911 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 2912!+ 00010001 PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 1 } 2913 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 2914 + 00000000 VGT_MIN_VTX_INDX: 0 2915 + 00000000 VGT_INDX_OFFSET: 0 2916 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 2917 + 00000000 RB_BLEND_RED: 0 2918 + 00000000 RB_BLEND_GREEN: 0 2919 + 00000000 RB_BLEND_BLUE: 0 2920 + 00000000 RB_BLEND_ALPHA: 0 2921 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2922 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2923 + 00000000 RB_ALPHA_REF: 0 2924 + 3f000000 PA_CL_VPORT_XSCALE: 0.500000 2925 + 3f000000 PA_CL_VPORT_XOFFSET: 0.500000 2926!+ 3f000000 PA_CL_VPORT_YSCALE: 0.500000 2927!+ 3f000000 PA_CL_VPORT_YOFFSET: 0.500000 2928 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 2929 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 2930 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 2931 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 2932 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 2933 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 2934 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 2935 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 2936 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 2937 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 2938 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 2939 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 2940 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 2941 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 2942 + 88888888 RB_SAMPLE_POS: 0x88888888 2943 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 2944 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 2945 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 2946 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 2947 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 2948 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 2949 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 2950 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 2951 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 2952 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 2953 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 2954 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 2955 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 2956 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 2957 + 0000ffff PA_SC_AA_MASK: 0xffff 2958 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 2959 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 2960 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 2961 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 29620122e25c: 0000: c0012200 00000000 00040085 2963 write CP_SCRATCH_REG7 (057f) 2964NEEDS WFI: CP_SCRATCH_REG7 (57f) 2965 CP_SCRATCH_REG7: 48 2966 :0,0,51,48 29670122e268: 0000: 0000057f 00000030 2968 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 29690122e270: 0000: c0002600 00000000 2970 opcode: CP_EVENT_WRITE (46) (2 dwords) 2971 { EVENT = CACHE_FLUSH } 2972 event CACHE_FLUSH 29730122e278: 0000: c0004600 00000006 2974 opcode: CP_EVENT_WRITE (46) (2 dwords) 2975 { EVENT = CACHE_FLUSH } 2976 event CACHE_FLUSH 29770122e280: 0000: c0004600 00000006 2978 opcode: CP_EVENT_WRITE (46) (2 dwords) 2979 { EVENT = CACHE_FLUSH } 2980 event CACHE_FLUSH 29810122e288: 0000: c0004600 00000006 2982 opcode: CP_EVENT_WRITE (46) (2 dwords) 2983 { EVENT = CACHE_FLUSH } 2984 event CACHE_FLUSH 29850122e290: 0000: c0004600 00000006 2986 opcode: CP_EVENT_WRITE (46) (2 dwords) 2987 { EVENT = CACHE_FLUSH } 2988 event CACHE_FLUSH 29890122e298: 0000: c0004600 00000006 2990 opcode: CP_EVENT_WRITE (46) (2 dwords) 2991 { EVENT = CACHE_FLUSH } 2992 event CACHE_FLUSH 29930122e2a0: 0000: c0004600 00000006 2994 opcode: CP_EVENT_WRITE (46) (2 dwords) 2995 { EVENT = CACHE_FLUSH } 2996 event CACHE_FLUSH 29970122e2a8: 0000: c0004600 00000006 2998 opcode: CP_EVENT_WRITE (46) (2 dwords) 2999 { EVENT = CACHE_FLUSH } 3000 event CACHE_FLUSH 30010122e2b0: 0000: c0004600 00000006 3002 opcode: CP_EVENT_WRITE (46) (2 dwords) 3003 { EVENT = CACHE_FLUSH } 3004 event CACHE_FLUSH 30050122e2b8: 0000: c0004600 00000006 3006 opcode: CP_EVENT_WRITE (46) (2 dwords) 3007 { EVENT = CACHE_FLUSH } 3008 event CACHE_FLUSH 30090122e2c0: 0000: c0004600 00000006 3010 opcode: CP_EVENT_WRITE (46) (2 dwords) 3011 { EVENT = CACHE_FLUSH } 3012 event CACHE_FLUSH 30130122e2c8: 0000: c0004600 00000006 3014 opcode: CP_EVENT_WRITE (46) (2 dwords) 3015 { EVENT = CACHE_FLUSH } 3016 event CACHE_FLUSH 30170122e2d0: 0000: c0004600 00000006 30180122f1d8: 0000: c0013700 0122e000 000000b6 3019 nop 3020 write CP_SCRATCH_REG6 (057e) 3021 CP_SCRATCH_REG6: 52 3022 :0,0,52,48 30230122f1e8: 0000: 0000057e 00000034 3024############################################################ 3025vertices: 0 3026cmd: deqp-gles2/185: fence=1258 3027############################################################ 3028cmdstream[8]: 124 dwords 3029 write RB_BC_CONTROL (0f01) 3030 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 30310122d000: 0000: 00000f01 1c004046 3032 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3033 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 30340122d008: 0000: c0012d00 00040293 00000020 3035 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3036 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 30370122d014: 0000: c0012d00 00040316 00000002 3038 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3039 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 30400122d020: 0000: c0012d00 00040317 00000002 3041 write CP_PERFMON_CNTL (0444) 3042 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 30430122d02c: 0000: 00000444 00000000 3044 write RBBM_PM_OVERRIDE1 (039c) 3045 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 3046 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 30470122d034: 0000: 0001039c ffffffff 00000fff 3048 write TP0_CHICKEN (0e1e) 3049 TP0_CHICKEN: 0x2 30500122d040: 0000: 00000e1e 00000002 3051 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 30520122d048: 0000: c0003b00 00007fff 3053 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3054 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 30550122d050: 0000: c0012d00 00040307 00100020 3056 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3057 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 30580122d05c: 0000: c0012d00 00040308 000e0120 3059 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3060 VGT_MAX_VTX_INDX: 0xffffffff 3061 VGT_MIN_VTX_INDX: 0 30620122d068: 0000: c0022d00 00040100 ffffffff 00000000 3063 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3064 VGT_INDX_OFFSET: 0 30650122d078: 0000: c0012d00 00040102 00000000 3066 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3067 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 30680122d084: 0000: c0012d00 00040181 00000004 3069 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3070 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 30710122d090: 0000: c0012d00 00040182 ffffffff 3072 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3073 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 30740122d09c: 0000: c0012d00 00040301 00000000 3075 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3076 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 30770122d0a8: 0000: c0012d00 00040300 00000000 3078 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3079 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 30800122d0b4: 0000: c0012d00 00040080 00000000 3081 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3082 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 30830122d0c0: 0000: c0012d00 00040208 00000004 3084 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3085 RB_SAMPLE_POS: 0x88888888 30860122d0cc: 0000: c0012d00 0004020a 88888888 3087 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3088 RB_COLOR_DEST_MASK: 0xffffffff 30890122d0d8: 0000: c0012d00 00040326 ffffffff 3090 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3091 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 30920122d0e4: 0000: c0012d00 0004031b 0003c000 3093 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3094 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 3095 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 30960122d0f0: 0000: c0022d00 00040183 00000000 00000000 3097 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 30980122d100: 0000: c0004b00 00000000 3099 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 31000122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001 3101 write SQ_INST_STORE_MANAGMENT (0d02) 3102 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 31030122d11c: 0000: 00000d02 00000180 3104 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 31050122d124: 0000: c0003b00 00000300 3106 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 31070122d12c: 0000: c0004a00 80000180 3108 opcode: CP_SET_CONSTANT (2d) (14 dwords) 31090122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 31100122d15c: 2.000000 0.750000 0.375000 0.250000 31110122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 31120122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 3113 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3114 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 31150122d16c: 0000: c0012d00 00040104 0000000f 3116 opcode: CP_SET_CONSTANT (2d) (6 dwords) 3117 RB_BLEND_RED: 0 3118 RB_BLEND_GREEN: 0 3119 RB_BLEND_BLUE: 0 3120 RB_BLEND_ALPHA: 0xff 31210122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 3122 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3123 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 31240122d190: 0000: c0012d00 00040206 0000043f 3125 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3126 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 } 31270122d19c: 0000: c0012d00 00040000 00000040 3128 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3129 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1230000 } 31300122d1a8: 0000: c0012d00 00040001 01230009 3131 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3132 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 3133 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 } 31340122d1b4: 0000: c0022d00 0004000e 80000000 00800040 3135 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3136 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 31370122d1c4: 0000: c0012d00 00040080 00000000 3138 write CP_SCRATCH_REG6 (057e) 3139 CP_SCRATCH_REG6: 57 3140 :0,0,57,48 31410122d1d0: 0000: 0000057e 00000039 3142 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 3143 ibaddr:0122e000 3144 ibsize:000000b6 3145 opcode: CP_SET_CONSTANT (2d) (6 dwords) 3146 set shader const 0078 31470122e000: 0000: c0042d00 00010078 0112d403 00100000 0112d403 00100000 3148 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3149 PA_SC_AA_MASK: 0xffff 31500122e018: 0000: c0012d00 00040312 0000ffff 3151 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3152 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 31530122e024: 0000: c0012d00 00040200 00000000 3154 opcode: CP_SET_CONSTANT (2d) (5 dwords) 3155 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 3156 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 3157 RB_ALPHA_REF: 0 31580122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 3159 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3160 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 3161 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 31620122e044: 0000: c0022d00 00040204 00000000 00090244 3163 opcode: CP_SET_CONSTANT (2d) (6 dwords) 3164 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 3165 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 3166 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 3167 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 31680122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 3169 opcode: CP_SET_CONSTANT (2d) (7 dwords) 3170 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 3171 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 3172 PA_CL_GB_VERT_DISC_ADJ: 1.000000 3173 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 3174 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 31750122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 3176 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3177 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 3178 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 } 31790122e088: 0000: c0022d00 00040081 00000000 00800040 3180 opcode: CP_SET_CONSTANT (2d) (8 dwords) 3181 PA_CL_VPORT_XSCALE: 32.000000 3182 PA_CL_VPORT_XOFFSET: 32.000000 3183 PA_CL_VPORT_YSCALE: 64.000000 3184 PA_CL_VPORT_YOFFSET: 64.000000 3185 PA_CL_VPORT_ZSCALE: 0.000000 3186 PA_CL_VPORT_ZOFFSET: 0.000000 31870122e098: 0000: c0062d00 0004010f 42000000 42000000 42800000 42800000 00000000 00000000 3188 opcode: CP_SET_CONSTANT (2d) (10 dwords) 31890122e0c0: 32.000000 64.000000 0.000000 0.000000 32.000000 64.000000 0.000000 0.000000 31900122e0b8: 0000: c0082d00 00000184 42000000 42800000 00000000 00000000 42000000 42800000 3191* 3192 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 3193 vertex shader, start=0000, size=0015 3194 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 3195 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 3196 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 3197 0000 0000 c200 ALLOC POSITION SIZE(0x0) 3198 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 3199 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 3200 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 3201 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 3202 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 3203 0000 0000 0000 NOP 32040122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 32050122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 32060122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 3207 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 3208 fragment shader, start=0000, size=000c 3209 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 3210 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 3211 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 3212 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 3213 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 3214 0000 0000 0000 NOP 32150122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 32160122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 3217 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3218 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 32190122e17c: 0000: c0012d00 00040181 00000106 3220 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3221 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 32220122e188: 0000: c0012d00 00040180 10030002 3223 opcode: CP_SET_CONSTANT (2d) (6 dwords) 32240122e19c: 0.000000 0.000000 0.000000 0.000000 32250122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 3226 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3227 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 32280122e1ac: 0000: c0012d00 00040202 00000c20 3229 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3230 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 32310122e1b8: 0000: c0012d00 00040201 00000000 3232 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3233 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 32340122e1c4: 0000: c0012d00 00040104 0000000f 3235 opcode: CP_SET_CONSTANT (2d) (6 dwords) 3236 RB_BLEND_RED: 0 3237 RB_BLEND_GREEN: 0 3238 RB_BLEND_BLUE: 0 3239 RB_BLEND_ALPHA: 0 32400122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 3241 opcode: CP_SET_CONSTANT (2d) (8 dwords) 3242 set texture const 0000 3243 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 3244 filter min/mag: point/point 3245 swizzle: xyzw 3246 addr=0110d000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE 3247 mipaddr=00000000 (flags=200) 32480122e1e8: 0000: c0062d00 00010000 80824800 0110d820 000fe03f 00000d11 00000000 00000200 3249 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3250 VGT_INDX_OFFSET: 0 32510122e208: 0000: c0012d00 00040102 00000000 3252 write TC_CNTL_STATUS (0e00) 3253 TC_CNTL_STATUS: { L2_INVALIDATE } 32540122e214: 0000: 00000e00 00000001 3255 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 32560122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 3257 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 32580122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 3259 write CP_SCRATCH_REG7 (057f) 3260 CP_SCRATCH_REG7: 53 3261 :0,0,57,53 32620122e24c: 0000: 0000057f 00000035 3263 opcode: CP_NOP (10) (2 dwords) 32640122e254: 0000: c0001000 00000000 3265 opcode: CP_DRAW_INDX (22) (3 dwords) 3266 { VIZ_QUERY = 0 } 3267 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 3268 draw: 0 3269 prim_type: DI_PT_TRIFAN (5) 3270 source_select: DI_SRC_SEL_AUTO_INDEX (2) 3271 num_indices: 1407 3272 draw[8] register values 3273 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 3274 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 3275 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 3276!+ 00000039 CP_SCRATCH_REG6: 57 3277 :0,0,57,53 3278!+ 00000035 CP_SCRATCH_REG7: 53 3279 :0,0,57,53 3280 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 3281 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 3282 + 00000002 TP0_CHICKEN: 0x2 3283 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 3284!+ 00000040 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 } 3285!+ 01230009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1230000 } 3286 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 3287!+ 00800040 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 } 3288 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 3289 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 3290!+ 00800040 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 } 3291 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 3292 + 00000000 VGT_MIN_VTX_INDX: 0 3293 + 00000000 VGT_INDX_OFFSET: 0 3294 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 3295 + 00000000 RB_BLEND_RED: 0 3296 + 00000000 RB_BLEND_GREEN: 0 3297 + 00000000 RB_BLEND_BLUE: 0 3298 + 00000000 RB_BLEND_ALPHA: 0 3299 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 3300 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 3301 + 00000000 RB_ALPHA_REF: 0 3302!+ 42000000 PA_CL_VPORT_XSCALE: 32.000000 3303!+ 42000000 PA_CL_VPORT_XOFFSET: 32.000000 3304!+ 42800000 PA_CL_VPORT_YSCALE: 64.000000 3305!+ 42800000 PA_CL_VPORT_YOFFSET: 64.000000 3306 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 3307 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 3308 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 3309 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 3310 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 3311 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 3312 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 3313 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 3314 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 3315 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 3316 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 3317 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 3318 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 3319 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 3320 + 88888888 RB_SAMPLE_POS: 0x88888888 3321 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 3322 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 3323 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 3324 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 3325 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 3326 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 3327 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 3328 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 3329 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 3330 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 3331 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 3332 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 3333 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 3334 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 3335 + 0000ffff PA_SC_AA_MASK: 0xffff 3336 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 3337 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 3338 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 3339 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 33400122e25c: 0000: c0012200 00000000 00040085 3341 write CP_SCRATCH_REG7 (057f) 3342NEEDS WFI: CP_SCRATCH_REG7 (57f) 3343 CP_SCRATCH_REG7: 54 3344 :0,0,57,54 33450122e268: 0000: 0000057f 00000036 3346 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 33470122e270: 0000: c0002600 00000000 3348 opcode: CP_EVENT_WRITE (46) (2 dwords) 3349 { EVENT = CACHE_FLUSH } 3350 event CACHE_FLUSH 33510122e278: 0000: c0004600 00000006 3352 opcode: CP_EVENT_WRITE (46) (2 dwords) 3353 { EVENT = CACHE_FLUSH } 3354 event CACHE_FLUSH 33550122e280: 0000: c0004600 00000006 3356 opcode: CP_EVENT_WRITE (46) (2 dwords) 3357 { EVENT = CACHE_FLUSH } 3358 event CACHE_FLUSH 33590122e288: 0000: c0004600 00000006 3360 opcode: CP_EVENT_WRITE (46) (2 dwords) 3361 { EVENT = CACHE_FLUSH } 3362 event CACHE_FLUSH 33630122e290: 0000: c0004600 00000006 3364 opcode: CP_EVENT_WRITE (46) (2 dwords) 3365 { EVENT = CACHE_FLUSH } 3366 event CACHE_FLUSH 33670122e298: 0000: c0004600 00000006 3368 opcode: CP_EVENT_WRITE (46) (2 dwords) 3369 { EVENT = CACHE_FLUSH } 3370 event CACHE_FLUSH 33710122e2a0: 0000: c0004600 00000006 3372 opcode: CP_EVENT_WRITE (46) (2 dwords) 3373 { EVENT = CACHE_FLUSH } 3374 event CACHE_FLUSH 33750122e2a8: 0000: c0004600 00000006 3376 opcode: CP_EVENT_WRITE (46) (2 dwords) 3377 { EVENT = CACHE_FLUSH } 3378 event CACHE_FLUSH 33790122e2b0: 0000: c0004600 00000006 3380 opcode: CP_EVENT_WRITE (46) (2 dwords) 3381 { EVENT = CACHE_FLUSH } 3382 event CACHE_FLUSH 33830122e2b8: 0000: c0004600 00000006 3384 opcode: CP_EVENT_WRITE (46) (2 dwords) 3385 { EVENT = CACHE_FLUSH } 3386 event CACHE_FLUSH 33870122e2c0: 0000: c0004600 00000006 3388 opcode: CP_EVENT_WRITE (46) (2 dwords) 3389 { EVENT = CACHE_FLUSH } 3390 event CACHE_FLUSH 33910122e2c8: 0000: c0004600 00000006 3392 opcode: CP_EVENT_WRITE (46) (2 dwords) 3393 { EVENT = CACHE_FLUSH } 3394 event CACHE_FLUSH 33950122e2d0: 0000: c0004600 00000006 33960122d1d8: 0000: c0013700 0122e000 000000b6 3397 nop 3398 write CP_SCRATCH_REG6 (057e) 3399 CP_SCRATCH_REG6: 58 3400 :0,0,58,54 34010122d1e8: 0000: 0000057e 0000003a 3402############################################################ 3403vertices: 0 3404cmd: deqp-gles2/185: fence=1259 3405############################################################ 3406cmdstream[9]: 340 dwords 3407 write RB_BC_CONTROL (0f01) 3408 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 34090110a000: 0000: 00000f01 1c004046 3410 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3411 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 34120110a008: 0000: c0012d00 00040293 00000020 3413 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3414 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 34150110a014: 0000: c0012d00 00040316 00000002 3416 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3417 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 34180110a020: 0000: c0012d00 00040317 00000002 3419 write CP_PERFMON_CNTL (0444) 3420 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 34210110a02c: 0000: 00000444 00000000 3422 write RBBM_PM_OVERRIDE1 (039c) 3423 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 3424 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 34250110a034: 0000: 0001039c ffffffff 00000fff 3426 write TP0_CHICKEN (0e1e) 3427 TP0_CHICKEN: 0x2 34280110a040: 0000: 00000e1e 00000002 3429 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 34300110a048: 0000: c0003b00 00007fff 3431 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3432 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 34330110a050: 0000: c0012d00 00040307 00100020 3434 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3435 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 34360110a05c: 0000: c0012d00 00040308 000e0120 3437 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3438 VGT_MAX_VTX_INDX: 0xffffffff 3439 VGT_MIN_VTX_INDX: 0 34400110a068: 0000: c0022d00 00040100 ffffffff 00000000 3441 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3442 VGT_INDX_OFFSET: 0 34430110a078: 0000: c0012d00 00040102 00000000 3444 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3445 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 34460110a084: 0000: c0012d00 00040181 00000004 3447 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3448 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 34490110a090: 0000: c0012d00 00040182 ffffffff 3450 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3451 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 34520110a09c: 0000: c0012d00 00040301 00000000 3453 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3454 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 34550110a0a8: 0000: c0012d00 00040300 00000000 3456 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3457 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 34580110a0b4: 0000: c0012d00 00040080 00000000 3459 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3460 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 34610110a0c0: 0000: c0012d00 00040208 00000004 3462 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3463 RB_SAMPLE_POS: 0x88888888 34640110a0cc: 0000: c0012d00 0004020a 88888888 3465 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3466 RB_COLOR_DEST_MASK: 0xffffffff 34670110a0d8: 0000: c0012d00 00040326 ffffffff 3468 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3469 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 34700110a0e4: 0000: c0012d00 0004031b 0003c000 3471 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3472 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 3473 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 34740110a0f0: 0000: c0022d00 00040183 00000000 00000000 3475 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 34760110a100: 0000: c0004b00 00000000 3477 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 34780110a108: 0000: c0035200 000005d0 00000000 5f601000 00000001 3479 write SQ_INST_STORE_MANAGMENT (0d02) 3480 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 34810110a11c: 0000: 00000d02 00000180 3482 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 34830110a124: 0000: c0003b00 00000300 3484 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 34850110a12c: 0000: c0004a00 80000180 3486 opcode: CP_SET_CONSTANT (2d) (14 dwords) 34870110a13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 34880110a15c: 2.000000 0.750000 0.375000 0.250000 34890110a134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 34900110a154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 3491 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3492 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 34930110a16c: 0000: c0012d00 00040104 0000000f 3494 opcode: CP_SET_CONSTANT (2d) (6 dwords) 3495 RB_BLEND_RED: 0 3496 RB_BLEND_GREEN: 0 3497 RB_BLEND_BLUE: 0 3498 RB_BLEND_ALPHA: 0xff 34990110a178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 3500 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3501 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 35020110a190: 0000: c0012d00 00040206 0000043f 3503 opcode: CP_SET_CONSTANT (2d) (5 dwords) 3504 RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 } 3505 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 3506 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 } 35070110a19c: 0000: c0032d00 00040000 00000080 00000205 00010001 3508 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3509 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 } 35100110a1b0: 0000: c0012d00 00040207 00000000 3511 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3512 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 } 35130110a1bc: 0000: c0012d00 00040203 00000000 3514 opcode: CP_SET_CONSTANT (2d) (6 dwords) 35150110a1d0: 3.069580 0.000000 8441856.000000 8454144.000000 35160110a1c8: 0000: c0042d00 0000000c 40447400 00000000 4b00d000 4b010000 3517 opcode: CP_SET_CONSTANT (2d) (10 dwords) 35180110a1e8: 0.125490 0.125490 0.500000 0.000000 0.000980 0.000980 0.000000 0.000000 35190110a1e0: 0000: c0082d00 0000018c 3e008081 3e008081 3f000000 00000000 3a808081 3a808081 3520* 3521 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3522 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 0 } 35230110a208: 0000: c0012d00 00040316 00000000 3524 write CP_SCRATCH_REG6 (057e) 3525 CP_SCRATCH_REG6: 67 3526 :0,0,67,54 35270110a214: 0000: 0000057e 00000043 3528 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 3529 ibaddr:0110c000 3530 ibsize:000000c5 3531 opcode: CP_SET_CONSTANT (2d) (6 dwords) 3532 set shader const 0078 35330110c000: 0000: c0042d00 00010078 0112d483 00100000 0112d4c3 00100000 3534 opcode: CP_IM_LOAD_IMMEDIATE (2b) (102 dwords) 3535 vertex shader, start=0000, size=0063 3536 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 3537 100b 0003 1000 EXEC ADDR(0xb) CNT(0x1) 3538 0b: 19480000 00262688 00000010 (S)FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0) 3539 400c 0002 1000 EXEC ADDR(0xc) CNT(0x4) 3540 0c: 00010001 00036c00 82000000 (S)ALU: MAXv R1.x___ = R0.wyzw, C0.xxxx 3541 0d: 4c110302 0000006c 60400201 ALU: ADDv R2.x___ = C0, R2 3542 RECIP_IEEE R3.x___ = R1.xxxx 3543 0e: 000f0004 00006c00 c1000300 ALU: MULv R4 = R0, R3.xxxx 3544 0f: 000f0005 00000000 4b420441 ALU: MULADDv R5 = C1, C2, R4 3545 0000 0000 c200 ALLOC POSITION SIZE(0x0) 3546 1010 0000 1000 EXEC ADDR(0x10) CNT(0x1) 3547 10: 000f803e 00000000 c2000000 ALU: MAXv export62 = R0, R0 ; gl_Position 3548 0000 0000 c600 ALLOC MEMORY SIZE(0x0) 3549 2011 0000 2000 EXEC_END ADDR(0x11) CNT(0x2) 3550 11: 000f8020 20136c00 4b010203 ALU: MULADDv export32 = C3, C1.wyww, R2.xxxx 3551 12: 000f8021 00000000 4b440543 ALU: MULADDv export33 = C3, C4, R5 3552 0000 0000 c600 ALLOC MEMORY SIZE(0x0) 3553 2013 0000 1000 EXEC ADDR(0x13) CNT(0x2) 3554 13: 000f8020 20136c00 4b010204 ALU: MULADDv export32 = C4, C1.wyww, R2.xxxx 3555 14: 000f8021 00000000 4b460545 ALU: MULADDv export33 = C5, C6, R5 3556 0000 0000 c600 ALLOC MEMORY SIZE(0x0) 3557 2015 0000 1000 EXEC ADDR(0x15) CNT(0x2) 3558 15: 000f8020 20136c00 4b010205 ALU: MULADDv export32 = C5, C1.wyww, R2.xxxx 3559 16: 000f8021 00000000 4b480547 ALU: MULADDv export33 = C7, C8, R5 3560 0000 0000 c600 ALLOC MEMORY SIZE(0x0) 3561 2017 0000 1000 EXEC ADDR(0x17) CNT(0x2) 3562 17: 000f8020 20136c00 4b010206 ALU: MULADDv export32 = C6, C1.wyww, R2.xxxx 3563 18: 000f8021 00000000 4b4a0549 ALU: MULADDv export33 = C9, C10, R5 3564 0000 0000 c600 ALLOC MEMORY SIZE(0x0) 3565 2019 0000 1000 EXEC ADDR(0x19) CNT(0x2) 3566 19: 000f8020 20136c00 4b010207 ALU: MULADDv export32 = C7, C1.wyww, R2.xxxx 3567 1a: 000f8021 00000000 4b4c054b ALU: MULADDv export33 = C11, C12, R5 3568 0000 0000 c600 ALLOC MEMORY SIZE(0x0) 3569 201b 0000 1000 EXEC ADDR(0x1b) CNT(0x2) 3570 1b: 000f8020 20136c00 4b010208 ALU: MULADDv export32 = C8, C1.wyww, R2.xxxx 3571 1c: 000f8021 00000000 4b4e054d ALU: MULADDv export33 = C13, C14, R5 3572 0000 0000 c600 ALLOC MEMORY SIZE(0x0) 3573 201d 0000 1000 EXEC ADDR(0x1d) CNT(0x2) 3574 1d: 000f8020 20136c00 4b010209 ALU: MULADDv export32 = C9, C1.wyww, R2.xxxx 3575 1e: 000f8021 00000000 4b50054f ALU: MULADDv export33 = C15, C16, R5 3576 0000 0000 c600 ALLOC MEMORY SIZE(0x0) 3577 201f 0000 2000 EXEC_END ADDR(0x1f) CNT(0x2) 3578 1f: 000f8020 20136c00 4b01020a ALU: MULADDv export32 = C10, C1.wyww, R2.xxxx 3579 20: 000f8021 00000000 4b520551 ALU: MULADDv export33 = C17, C18, R5 3580 0000 0000 0000 NOP 35810110c018: 0000: c0642b00 00000000 00000063 00000000 100bc400 10000003 0002400c 00001000 35820110c038: 0020: c2000000 00001010 00001000 c6000000 00002011 00002000 c6000000 00002013 35830110c058: 0040: 00001000 c6000000 00002015 00001000 c6000000 00002017 00001000 c6000000 35840110c078: 0060: 00002019 00001000 c6000000 0000201b 00001000 c6000000 0000201d 00001000 35850110c098: 0080: c6000000 0000201f 00002000 00000000 19480000 00262688 00000010 00010001 35860110c0b8: 00a0: 00036c00 82000000 4c110302 0000006c 60400201 000f0004 00006c00 c1000300 35870110c0d8: 00c0: 000f0005 00000000 4b420441 000f803e 00000000 c2000000 000f8020 20136c00 35880110c0f8: 00e0: 4b010203 000f8021 00000000 4b440543 000f8020 20136c00 4b010204 000f8021 35890110c118: 0100: 00000000 4b460545 000f8020 20136c00 4b010205 000f8021 00000000 4b480547 35900110c138: 0120: 000f8020 20136c00 4b010206 000f8021 00000000 4b4a0549 000f8020 20136c00 35910110c158: 0140: 4b010207 000f8021 00000000 4b4c054b 000f8020 20136c00 4b010208 000f8021 35920110c178: 0160: 00000000 4b4e054d 000f8020 20136c00 4b010209 000f8021 00000000 4b50054f 35930110c198: 0180: 000f8020 20136c00 4b01020a 000f8021 00000000 4b520551 3594 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3595 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 35960110c1b0: 0000: c0012d00 00040181 00000006 3597 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3598 SQ_PROGRAM_CNTL: { VS_REGS = 5 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 | GEN_INDEX_VTX } 35990110c1bc: 0000: c0012d00 00040180 90030005 3600 opcode: CP_SET_CONSTANT (2d) (6 dwords) 36010110c1d0: 0.000000 0.000000 0.000000 0.000000 36020110c1c8: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 3603 opcode: CP_SET_CONSTANT (2d) (10 dwords) 36040110c1e8: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000 36050110c1e0: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000 36060110c200: 0020: 3f000000 00000000 3607 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3608 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 36090110c208: 0000: c0012d00 00040201 00000000 3610 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3611 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 36120110c214: 0000: c0012d00 00040104 0000000f 3613 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3614 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_POINTS | BACK_PTYPE = PC_DRAW_POINTS | FACE_KILL_ENABLE } 36150110c220: 0000: c0012d00 00040205 40000000 3616 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3617 VGT_INDX_OFFSET: 0 36180110c22c: 0000: c0012d00 00040102 00000000 3619 write TC_CNTL_STATUS (0e00) 3620 TC_CNTL_STATUS: { L2_INVALIDATE } 36210110c238: 0000: 00000e00 00000001 3622 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 36230110c240: 0000: c0035200 000005d0 00000000 00001000 00000001 3624 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 36250110c254: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 3626 opcode: CP_SET_CONSTANT (2d) (6 dwords) 36270110c278: 0.000000 0.000000 0.000000 0.000000 36280110c270: 0000: c0042d00 00000180 00000000 00000000 00000000 00000000 3629 write CP_SCRATCH_REG7 (057f) 3630 CP_SCRATCH_REG7: 61 3631 :0,0,67,61 36320110c288: 0000: 0000057f 0000003d 3633 opcode: CP_DRAW_INDX (22) (5 dwords) 3634 { VIZ_QUERY = 0 } 3635 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 } 3636 { NUM_INDICES = 18011360 } 3637 { INDX_BASE = 0xc } 3638 draw: 0 3639 prim_type: DI_PT_TRILIST (4) 3640 source_select: DI_SRC_SEL_DMA (0) 3641 num_indices: 18011360 3642 draw[9] register values 3643 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 3644 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 3645 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 3646!+ 00000043 CP_SCRATCH_REG6: 67 3647 :0,0,67,61 3648!+ 0000003d CP_SCRATCH_REG7: 61 3649 :0,0,67,61 3650 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 3651 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 3652 + 00000002 TP0_CHICKEN: 0x2 3653 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 3654!+ 00000080 RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 } 3655!+ 00000205 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 3656!+ 00010001 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 } 3657 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 3658 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 3659 + 00000000 VGT_MIN_VTX_INDX: 0 3660 + 00000000 VGT_INDX_OFFSET: 0 3661 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 3662 + 00000000 RB_BLEND_RED: 0 3663 + 00000000 RB_BLEND_GREEN: 0 3664 + 00000000 RB_BLEND_BLUE: 0 3665!+ 000000ff RB_BLEND_ALPHA: 0xff 3666!+ 90030005 SQ_PROGRAM_CNTL: { VS_REGS = 5 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 | GEN_INDEX_VTX } 3667!+ 00000006 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 3668 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 3669 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 3670 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 3671 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 3672 + 00000000 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 } 3673!+ 40000000 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_POINTS | BACK_PTYPE = PC_DRAW_POINTS | FACE_KILL_ENABLE } 3674 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 3675 + 00000000 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 } 3676 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 3677 + 88888888 RB_SAMPLE_POS: 0x88888888 3678 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 3679 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 3680 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 3681 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 3682 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 3683!+ 00000000 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 0 } 3684 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 3685 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 3686 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 36870110c290: 0000: c0032200 00000000 00060004 0112d4e0 0000000c 3688 write CP_SCRATCH_REG7 (057f) 3689NEEDS WFI: CP_SCRATCH_REG7 (57f) 3690 CP_SCRATCH_REG7: 62 3691 :0,0,67,62 36920110c2a4: 0000: 0000057f 0000003e 3693 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 36940110c2ac: 0000: c0002600 00000000 3695 opcode: CP_EVENT_WRITE (46) (2 dwords) 3696 { EVENT = CACHE_FLUSH } 3697 event CACHE_FLUSH 36980110c2b4: 0000: c0004600 00000006 3699 opcode: CP_EVENT_WRITE (46) (2 dwords) 3700 { EVENT = CACHE_FLUSH } 3701 event CACHE_FLUSH 37020110c2bc: 0000: c0004600 00000006 3703 opcode: CP_EVENT_WRITE (46) (2 dwords) 3704 { EVENT = CACHE_FLUSH } 3705 event CACHE_FLUSH 37060110c2c4: 0000: c0004600 00000006 3707 opcode: CP_EVENT_WRITE (46) (2 dwords) 3708 { EVENT = CACHE_FLUSH } 3709 event CACHE_FLUSH 37100110c2cc: 0000: c0004600 00000006 3711 opcode: CP_EVENT_WRITE (46) (2 dwords) 3712 { EVENT = CACHE_FLUSH } 3713 event CACHE_FLUSH 37140110c2d4: 0000: c0004600 00000006 3715 opcode: CP_EVENT_WRITE (46) (2 dwords) 3716 { EVENT = CACHE_FLUSH } 3717 event CACHE_FLUSH 37180110c2dc: 0000: c0004600 00000006 3719 opcode: CP_EVENT_WRITE (46) (2 dwords) 3720 { EVENT = CACHE_FLUSH } 3721 event CACHE_FLUSH 37220110c2e4: 0000: c0004600 00000006 3723 opcode: CP_EVENT_WRITE (46) (2 dwords) 3724 { EVENT = CACHE_FLUSH } 3725 event CACHE_FLUSH 37260110c2ec: 0000: c0004600 00000006 3727 opcode: CP_EVENT_WRITE (46) (2 dwords) 3728 { EVENT = CACHE_FLUSH } 3729 event CACHE_FLUSH 37300110c2f4: 0000: c0004600 00000006 3731 opcode: CP_EVENT_WRITE (46) (2 dwords) 3732 { EVENT = CACHE_FLUSH } 3733 event CACHE_FLUSH 37340110c2fc: 0000: c0004600 00000006 3735 opcode: CP_EVENT_WRITE (46) (2 dwords) 3736 { EVENT = CACHE_FLUSH } 3737 event CACHE_FLUSH 37380110c304: 0000: c0004600 00000006 3739 opcode: CP_EVENT_WRITE (46) (2 dwords) 3740 { EVENT = CACHE_FLUSH } 3741 event CACHE_FLUSH 37420110c30c: 0000: c0004600 00000006 37430110a21c: 0000: c0013700 0110c000 000000c5 3744 nop 3745 write CP_SCRATCH_REG6 (057e) 3746 CP_SCRATCH_REG6: 68 3747 :0,0,68,62 37480110a22c: 0000: 0000057e 00000044 3749 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3750 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 37510110a234: 0000: c0012d00 00040316 00000002 3752 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3753 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 37540110a240: 0000: c0012d00 00040001 00000205 3755 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3756 PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } 3757 PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 } 37580110a24c: 0000: c0022d00 0004000e 00000000 00800080 3759 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3760 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 37610110a25c: 0000: c0012d00 00040001 00000205 3762 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3763 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 37640110a268: 0000: c0012d00 00040080 00000000 3765 opcode: CP_MEM_WRITE (3d) (3 dwords) 3766 { ADDR_LO = 0x100903c } 3767 { ADDR_HI = 0x800080 } 3768 gpuaddr:0100903c 37690110a27c: 0.000000 37700110a274: 0000: c0013d00 0100903c 00800080 3771 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3772 RB_COPY_DEST_OFFSET: { X = 0 | Y = 0 } 37730110a280: 0000: c0012d00 0004031c 00000000 3774 opcode: CP_SET_CONSTANT (2d) (6 dwords) 37750110a294: 0.000000 0.000000 0.000000 0.000000 37760110a28c: 0000: c0042d00 00000580 00000000 00000000 00000000 00000000 3777 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3778 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 } 37790110a2a4: 0000: c0012d00 00040207 00000009 3780 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3781 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 } 37820110a2b0: 0000: c0012d00 00040203 00000009 3783 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 37840110a2bc: 0000: c0004b00 0111d000 3785 write CP_SCRATCH_REG6 (057e) 3786 CP_SCRATCH_REG6: 69 3787 :0,0,69,62 37880110a2c4: 0000: 0000057e 00000045 3789 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 3790 ibaddr:0110b000 3791 ibsize:00000198 3792 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3793 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 3794 PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 } 37950110b000: 0000: c0022d00 00040081 00000000 3fff3fff 3796 opcode: CP_SET_CONSTANT (2d) (6 dwords) 3797 PA_CL_VPORT_XSCALE: 4096.000000 3798 PA_CL_VPORT_XOFFSET: 4096.000000 3799 PA_CL_VPORT_YSCALE: 4096.000000 3800 PA_CL_VPORT_YOFFSET: 4096.000000 38010110b010: 0000: c0042d00 0004010f 45800000 45800000 45800000 45800000 3802 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3803 set shader const 009c 38040110b028: 0000: c0022d00 0001009c 01009003 00000024 3805 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3806 VGT_INDX_OFFSET: 0 38070110b038: 0000: c0012d00 00040102 00000000 3808 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 3809 vertex shader, start=0000, size=000c 3810 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 3811 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 3812 02: 19a80000 00392a88 0000000c (S)FETCH: VERTEX R0.xyz1 = R0.x FMT_32_32_32_FLOAT UNSIGNED STRIDE(12) CONST(26, 0) 3813 0000 0000 c200 ALLOC POSITION SIZE(0x0) 3814 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 3815 03: 000f803e 00000000 c2000000 (S)ALU: MAXv export62 = R0, R0 ; gl_Position 38160110b044: 0000: c00d2b00 00000000 0000000c 00000000 1002c400 10000003 00000000 1003c200 38170110b064: 0020: 20000002 19a80000 00392a88 0000000c 000f803e 00000000 c2000000 3818 opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords) 3819 fragment shader, start=0000, size=0006 3820 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 3821 1001 0002 2000 EXEC_END ADDR(0x1) CNT(0x1) 3822 01: 000f8000 00000000 02000000 (S)ALU: MAXv export0 = C0, C0 ; gl_FragColor 38230110b080: 0000: c0072b00 00000001 00000006 00000000 1001c400 20000002 000f8000 00000000 38240110b0a0: 0020: 02000000 3825 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3826 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 38270110b0a4: 0000: c0012d00 00040181 00000006 3828 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3829 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 38300110b0b0: 0000: c0012d00 00040180 10038002 3831 write TC_CNTL_STATUS (0e00) 3832 TC_CNTL_STATUS: { L2_INVALIDATE } 38330110b0bc: 0000: 00000e00 00000001 3834 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3835 RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 38360110b0c4: 0000: c0012d00 00040200 0000877f 3837 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3838 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 38390110b0d0: 0000: c0012d00 00040202 00000c27 3840 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3841 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 3842 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST } 38430110b0dc: 0000: c0022d00 00040204 00000000 00088240 3844 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3845 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 } 38460110b0ec: 0000: c0012d00 00040301 00000003 3847 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3848 PA_SC_AA_MASK: 0xffff 38490110b0f8: 0000: c0012d00 00040312 0000ffff 3850 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3851 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 38520110b104: 0000: c0012d00 00040104 0000000f 3853 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3854 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 38550110b110: 0000: c0012d00 00040201 00000000 3856 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3857 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 } 38580110b11c: 0000: c0012d00 0004000f 00400020 3859 opcode: CP_SET_CONSTANT (2d) (5 dwords) 3860 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 } 3861 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 } 3862 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 32768 } 38630110b128: 0000: c0032d00 00040000 00008020 00000005 00008001 3864 opcode: CP_SET_CONSTANT (2d) (6 dwords) 38650110b144: 0.501961 0.250980 0.125490 1.000000 38660110b13c: 0000: c0042d00 00000480 3f008081 3e808081 3e008081 3f800000 3867 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3868 PA_CL_VPORT_ZSCALE: 0.000000 3869 PA_CL_VPORT_ZOFFSET: 0.996586 38700110b154: 0000: c0022d00 00040113 00000000 3f7f2041 3871 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3872 RB_STENCILREFMASK_BF: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 3873 RB_STENCILREFMASK: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 38740110b164: 0000: c0022d00 0004010c ffff0080 ffff0080 3875 write CP_SCRATCH_REG7 (057f) 3876 CP_SCRATCH_REG7: 1 3877 :0,0,69,1 38780110b174: 0000: 0000057f 00000001 3879 opcode: CP_DRAW_INDX (22) (3 dwords) 3880 { VIZ_QUERY = 0 } 3881 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 } 3882 draw: 0 3883 prim_type: DI_PT_RECTLIST (8) 3884 source_select: DI_SRC_SEL_AUTO_INDEX (2) 3885 num_indices: 1407 3886 draw[10] register values 3887!+ 00000045 CP_SCRATCH_REG6: 69 3888 :0,0,69,1 3889!+ 00000001 CP_SCRATCH_REG7: 1 3890 :0,0,69,1 3891 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 3892!+ 00008020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 } 3893!+ 00000005 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 } 3894!+ 00008001 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 32768 } 3895!+ 00000000 PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } 3896!+ 00400020 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 } 3897 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 3898 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 3899!+ 3fff3fff PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 } 3900 + 00000000 VGT_INDX_OFFSET: 0 3901 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 3902!+ ffff0080 RB_STENCILREFMASK_BF: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 3903!+ ffff0080 RB_STENCILREFMASK: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 3904!+ 45800000 PA_CL_VPORT_XSCALE: 4096.000000 3905!+ 45800000 PA_CL_VPORT_XOFFSET: 4096.000000 3906!+ 45800000 PA_CL_VPORT_YSCALE: 4096.000000 3907!+ 45800000 PA_CL_VPORT_YOFFSET: 4096.000000 3908 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 3909!+ 3f7f2041 PA_CL_VPORT_ZOFFSET: 0.996586 3910!+ 10038002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 3911 + 00000006 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 3912!+ 0000877f RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 3913 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 3914!+ 00000c27 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 3915!+ 00000009 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 } 3916 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 3917!+ 00088240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST } 3918!+ 00000009 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 } 3919!+ 00000003 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 } 3920 + 0000ffff PA_SC_AA_MASK: 0xffff 3921!+ 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 3922 + 00000000 RB_COPY_DEST_OFFSET: { X = 0 | Y = 0 } 39230110b17c: 0000: c0012200 00000000 00030088 3924 write CP_SCRATCH_REG7 (057f) 3925NEEDS WFI: CP_SCRATCH_REG7 (57f) 3926 CP_SCRATCH_REG7: 2 3927 :0,0,69,2 39280110b188: 0000: 0000057f 00000002 3929 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3930 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 39310110b190: 0000: c0012d00 00040301 00000000 3932 opcode: CP_LOAD_CONSTANT_CONTEXT (2e) (4 dwords) 39330110b19c: 0000: c0022e00 01009000 0004000f 00000001 3934 opcode: CP_SET_CONSTANT (2d) (5 dwords) 3935 RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 } 3936 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 3937 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 } 39380110b1ac: 0000: c0032d00 00040000 00000080 00000205 00010001 3939 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3940 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 3941 PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 } 39420110b1c0: 0000: c0022d00 00040081 00000000 3fff3fff 3943 opcode: CP_SET_CONSTANT (2d) (6 dwords) 3944 PA_CL_VPORT_XSCALE: 4096.000000 3945 PA_CL_VPORT_XOFFSET: 4096.000000 3946 PA_CL_VPORT_YSCALE: 4096.000000 3947 PA_CL_VPORT_YOFFSET: 4096.000000 39480110b1d0: 0000: c0042d00 0004010f 45800000 45800000 45800000 45800000 3949 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3950 set shader const 009c 39510110b1e8: 0000: c0022d00 0001009c 01009003 00000024 3952 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3953 VGT_INDX_OFFSET: 0 39540110b1f8: 0000: c0012d00 00040102 00000000 3955 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 3956 vertex shader, start=0000, size=000c 3957 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 3958 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 3959 02: 19a80000 00392a88 0000000c (S)FETCH: VERTEX R0.xyz1 = R0.x FMT_32_32_32_FLOAT UNSIGNED STRIDE(12) CONST(26, 0) 3960 0000 0000 c200 ALLOC POSITION SIZE(0x0) 3961 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 3962 03: 000f803e 00000000 c2000000 (S)ALU: MAXv export62 = R0, R0 ; gl_Position 39630110b204: 0000: c00d2b00 00000000 0000000c 00000000 1002c400 10000003 00000000 1003c200 39640110b224: 0020: 20000002 19a80000 00392a88 0000000c 000f803e 00000000 c2000000 3965 opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords) 3966 fragment shader, start=0000, size=0006 3967 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 3968 1001 0002 2000 EXEC_END ADDR(0x1) CNT(0x1) 3969 01: 000f8000 00000000 02000000 (S)ALU: MAXv export0 = C0, C0 ; gl_FragColor 39700110b240: 0000: c0072b00 00000001 00000006 00000000 1001c400 20000002 000f8000 00000000 39710110b260: 0020: 02000000 3972 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3973 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 39740110b264: 0000: c0012d00 00040181 00000006 3975 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3976 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 39770110b270: 0000: c0012d00 00040180 10038002 3978 write TC_CNTL_STATUS (0e00) 3979NEEDS WFI: TC_CNTL_STATUS (e00) 3980 TC_CNTL_STATUS: { L2_INVALIDATE } 39810110b27c: 0000: 00000e00 00000001 3982 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3983 RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 39840110b284: 0000: c0012d00 00040200 0000877f 3985 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3986 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 39870110b290: 0000: c0012d00 00040202 00000c27 3988 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3989 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 3990 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST } 39910110b29c: 0000: c0022d00 00040204 00000000 00088240 3992 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3993 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 } 39940110b2ac: 0000: c0012d00 00040301 00000003 3995 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3996 PA_SC_AA_MASK: 0xffff 39970110b2b8: 0000: c0012d00 00040312 0000ffff 3998 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3999 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 40000110b2c4: 0000: c0012d00 00040104 0000000f 4001 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4002 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 40030110b2d0: 0000: c0012d00 00040201 00000000 4004 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4005 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 128 } 40060110b2dc: 0000: c0012d00 0004000f 00800020 4007 opcode: CP_SET_CONSTANT (2d) (5 dwords) 4008 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 } 4009 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 } 4010 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 } 40110110b2e8: 0000: c0032d00 00040000 00008020 00000005 00010001 4012 opcode: CP_SET_CONSTANT (2d) (6 dwords) 40130110b304: 0.501961 0.250980 0.125490 1.000000 40140110b2fc: 0000: c0042d00 00000480 3f008081 3e808081 3e008081 3f800000 4015 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4016 PA_CL_VPORT_ZSCALE: 0.000000 4017 PA_CL_VPORT_ZOFFSET: 1.000000 40180110b314: 0000: c0022d00 00040113 00000000 3f800000 4019 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4020 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 4021 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 40220110b324: 0000: c0022d00 0004010c ffff0000 ffff0000 4023 write CP_SCRATCH_REG7 (057f) 4024NEEDS WFI: CP_SCRATCH_REG7 (57f) 4025 CP_SCRATCH_REG7: 3 4026 :0,0,69,3 40270110b334: 0000: 0000057f 00000003 4028 opcode: CP_DRAW_INDX (22) (3 dwords) 4029 { VIZ_QUERY = 0 } 4030 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 } 4031 draw: 1 4032 prim_type: DI_PT_RECTLIST (8) 4033 source_select: DI_SRC_SEL_AUTO_INDEX (2) 4034 num_indices: 1407 4035 draw[11] register values 4036!+ 00000003 CP_SCRATCH_REG7: 3 4037 :0,0,69,3 4038 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 4039 + 00008020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 } 4040 + 00000005 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 } 4041!+ 00010001 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 } 4042!+ 00800020 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 128 } 4043 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 4044 + 3fff3fff PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 } 4045 + 00000000 VGT_INDX_OFFSET: 0 4046 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 4047!+ ffff0000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 4048!+ ffff0000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 4049 + 45800000 PA_CL_VPORT_XSCALE: 4096.000000 4050 + 45800000 PA_CL_VPORT_XOFFSET: 4096.000000 4051 + 45800000 PA_CL_VPORT_YSCALE: 4096.000000 4052 + 45800000 PA_CL_VPORT_YOFFSET: 4096.000000 4053 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 4054!+ 3f800000 PA_CL_VPORT_ZOFFSET: 1.000000 4055 + 10038002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 4056 + 00000006 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 4057 + 0000877f RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 4058 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 4059 + 00000c27 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 4060 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 4061 + 00088240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST } 4062 + 00000003 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 } 4063 + 0000ffff PA_SC_AA_MASK: 0xffff 40640110b33c: 0000: c0012200 00000000 00030088 4065 write CP_SCRATCH_REG7 (057f) 4066NEEDS WFI: CP_SCRATCH_REG7 (57f) 4067 CP_SCRATCH_REG7: 4 4068 :0,0,69,4 40690110b348: 0000: 0000057f 00000004 4070 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4071 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 40720110b350: 0000: c0012d00 00040301 00000000 4073 opcode: CP_LOAD_CONSTANT_CONTEXT (2e) (4 dwords) 40740110b35c: 0000: c0022e00 01009000 0004000f 00000001 4075 opcode: CP_SET_CONSTANT (2d) (5 dwords) 4076 RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 } 4077 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 4078 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 } 40790110b36c: 0000: c0032d00 00040000 00000080 00000205 00010001 4080 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4081 set shader const 0078 40820110b380: 0000: c0042d00 00010078 0112d483 00100000 0112d4c3 00100000 4083 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4084 PA_SC_AA_MASK: 0xffff 40850110b398: 0000: c0012d00 00040312 0000ffff 4086 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4087 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 40880110b3a4: 0000: c0012d00 00040200 00000000 4089 opcode: CP_SET_CONSTANT (2d) (5 dwords) 4090 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 4091 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 4092 RB_ALPHA_REF: 0 40930110b3b0: 0000: c0032d00 0004010c 00000000 00000000 00000000 4094 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4095 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 4096 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 40970110b3c4: 0000: c0022d00 00040204 00000000 00090240 4098 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4099 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 4100 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 4101 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 4102 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 41030110b3d4: 0000: c0042d00 00040280 00080008 00080008 00000008 00000000 4104 opcode: CP_SET_CONSTANT (2d) (7 dwords) 4105 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 4106 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 4107 PA_CL_GB_VERT_DISC_ADJ: 1.000000 4108 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 4109 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 41100110b3ec: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 4111 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4112 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 4113 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 41140110b408: 0000: c0022d00 00040081 00000000 01000100 4115 opcode: CP_SET_CONSTANT (2d) (8 dwords) 4116 PA_CL_VPORT_XSCALE: 128.000000 4117 PA_CL_VPORT_XOFFSET: 128.000000 4118 PA_CL_VPORT_YSCALE: -128.000000 4119 PA_CL_VPORT_YOFFSET: 128.000000 4120 PA_CL_VPORT_ZSCALE: 0.500000 4121 PA_CL_VPORT_ZOFFSET: 0.500000 41220110b418: 0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000 4123 opcode: CP_SET_CONSTANT (2d) (10 dwords) 41240110b440: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000 41250110b438: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000 41260110b458: 0020: 3f000000 00000000 4127 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 4128 vertex shader, start=0000, size=0015 4129 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 4130 03: 19481000 00262688 00000010 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0) 4131 04: 13480000 40252fc8 00000008 FETCH: VERTEX R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1) 4132 0000 0000 c200 ALLOC POSITION SIZE(0x0) 4133 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 4134 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 4135 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 4136 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 4137 06: 00038000 00000000 c2000000 ALU: MAXv export0.xy__ = R0, R0 4138 0000 0000 0000 NOP 41390110b460: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 41400110b480: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000 41410110b4a0: 0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000 4142 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 4143 fragment shader, start=0000, size=000c 4144 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 4145 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 4146 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 4147 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 4148 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 4149 0000 0000 0000 NOP 41500110b4c0: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 41510110b4e0: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 4152 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4153 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 41540110b4fc: 0000: c0012d00 00040181 00000106 4155 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4156 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 41570110b508: 0000: c0012d00 00040180 10030002 4158 opcode: CP_SET_CONSTANT (2d) (6 dwords) 41590110b51c: 0.000000 0.000000 0.000000 0.000000 41600110b514: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 4161 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4162 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 41630110b52c: 0000: c0012d00 00040202 00001c20 4164 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4165 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 41660110b538: 0000: c0012d00 00040201 00000000 4167 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4168 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 41690110b544: 0000: c0012d00 00040104 0000000f 4170 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4171 RB_BLEND_RED: 0 4172 RB_BLEND_GREEN: 0 4173 RB_BLEND_BLUE: 0 4174 RB_BLEND_ALPHA: 0 41750110b550: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 4176 opcode: CP_SET_CONSTANT (2d) (8 dwords) 4177 set texture const 0000 4178 clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap 4179 filter min/mag: point/point 4180 swizzle: xyzw 4181 addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE 4182 mipaddr=01240000 (flags=200) 41830110b568: 0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200 4184 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4185 VGT_INDX_OFFSET: 0 41860110b588: 0000: c0012d00 00040102 00000000 4187 write TC_CNTL_STATUS (0e00) 4188NEEDS WFI: TC_CNTL_STATUS (e00) 4189 TC_CNTL_STATUS: { L2_INVALIDATE } 41900110b594: 0000: 00000e00 00000001 4191 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 41920110b59c: 0000: c0035200 000005d0 00000000 00001000 00000001 4193 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 41940110b5b0: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 4195 write CP_SCRATCH_REG7 (057f) 4196NEEDS WFI: CP_SCRATCH_REG7 (57f) 4197 CP_SCRATCH_REG7: 59 4198 :0,0,69,59 41990110b5cc: 0000: 0000057f 0000003b 4200 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 42010110b5d4: 0000: c0053400 00000000 0006c004 00000000 00000006 0112d4e0 0000000c 4202 write CP_SCRATCH_REG7 (057f) 4203NEEDS WFI: CP_SCRATCH_REG7 (57f) 4204 CP_SCRATCH_REG7: 60 4205 :0,0,69,60 42060110b5f0: 0000: 0000057f 0000003c 4207 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 42080110b5f8: 0000: c0002600 00000000 4209 opcode: CP_EVENT_WRITE (46) (2 dwords) 4210 { EVENT = CACHE_FLUSH } 4211 event CACHE_FLUSH 42120110b600: 0000: c0004600 00000006 4213 opcode: CP_EVENT_WRITE (46) (2 dwords) 4214 { EVENT = CACHE_FLUSH } 4215 event CACHE_FLUSH 42160110b608: 0000: c0004600 00000006 4217 opcode: CP_EVENT_WRITE (46) (2 dwords) 4218 { EVENT = CACHE_FLUSH } 4219 event CACHE_FLUSH 42200110b610: 0000: c0004600 00000006 4221 opcode: CP_EVENT_WRITE (46) (2 dwords) 4222 { EVENT = CACHE_FLUSH } 4223 event CACHE_FLUSH 42240110b618: 0000: c0004600 00000006 4225 opcode: CP_EVENT_WRITE (46) (2 dwords) 4226 { EVENT = CACHE_FLUSH } 4227 event CACHE_FLUSH 42280110b620: 0000: c0004600 00000006 4229 opcode: CP_EVENT_WRITE (46) (2 dwords) 4230 { EVENT = CACHE_FLUSH } 4231 event CACHE_FLUSH 42320110b628: 0000: c0004600 00000006 4233 opcode: CP_EVENT_WRITE (46) (2 dwords) 4234 { EVENT = CACHE_FLUSH } 4235 event CACHE_FLUSH 42360110b630: 0000: c0004600 00000006 4237 opcode: CP_EVENT_WRITE (46) (2 dwords) 4238 { EVENT = CACHE_FLUSH } 4239 event CACHE_FLUSH 42400110b638: 0000: c0004600 00000006 4241 opcode: CP_EVENT_WRITE (46) (2 dwords) 4242 { EVENT = CACHE_FLUSH } 4243 event CACHE_FLUSH 42440110b640: 0000: c0004600 00000006 4245 opcode: CP_EVENT_WRITE (46) (2 dwords) 4246 { EVENT = CACHE_FLUSH } 4247 event CACHE_FLUSH 42480110b648: 0000: c0004600 00000006 4249 opcode: CP_EVENT_WRITE (46) (2 dwords) 4250 { EVENT = CACHE_FLUSH } 4251 event CACHE_FLUSH 42520110b650: 0000: c0004600 00000006 4253 opcode: CP_EVENT_WRITE (46) (2 dwords) 4254 { EVENT = CACHE_FLUSH } 4255 event CACHE_FLUSH 42560110b658: 0000: c0004600 00000006 42570110a2cc: 0000: c0013700 0110b000 00000198 4258 nop 4259 write CP_SCRATCH_REG6 (057e) 4260 CP_SCRATCH_REG6: 70 4261 :0,0,70,60 42620110a2dc: 0000: 0000057e 00000046 4263 write CP_SCRATCH_REG6 (057e) 4264 CP_SCRATCH_REG6: 71 4265 :0,0,71,60 42660110a2e4: 0000: 0000057e 00000047 4267 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 4268 ibaddr:0125e000 4269 ibsize:00000064 4270 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4271 set shader const 009c 42720125e000: 0000: c0022d00 0001009c 01009003 00000024 4273 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4274 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 42750125e010: 0000: c0012d00 00040080 00000000 4276 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4277 VGT_INDX_OFFSET: 0 42780125e01c: 0000: c0012d00 00040102 00000000 4279 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 4280 vertex shader, start=0000, size=000c 4281 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 4282 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 4283 02: 19a80000 00392a88 0000000c (S)FETCH: VERTEX R0.xyz1 = R0.x FMT_32_32_32_FLOAT UNSIGNED STRIDE(12) CONST(26, 0) 4284 0000 0000 c200 ALLOC POSITION SIZE(0x0) 4285 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 4286 03: 000f803e 00000000 c2000000 (S)ALU: MAXv export62 = R0, R0 ; gl_Position 42870125e028: 0000: c00d2b00 00000000 0000000c 00000000 1002c400 10000003 00000000 1003c200 42880125e048: 0020: 20000002 19a80000 00392a88 0000000c 000f803e 00000000 c2000000 4289 opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords) 4290 fragment shader, start=0000, size=0006 4291 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 4292 1001 0002 2000 EXEC_END ADDR(0x1) CNT(0x1) 4293 01: 000f8000 00000000 02000000 (S)ALU: MAXv export0 = C0, C0 ; gl_FragColor 42940125e064: 0000: c0072b00 00000001 00000006 00000000 1001c400 20000002 000f8000 00000000 42950125e084: 0020: 02000000 4296 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4297 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 42980125e088: 0000: c0012d00 00040181 00000006 4299 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4300 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 43010125e094: 0000: c0012d00 00040180 10038002 4302 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4303 PA_SC_AA_MASK: 0xffff 43040125e0a0: 0000: c0012d00 00040312 0000ffff 4305 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4306 RB_DEPTHCONTROL: { EARLY_Z_ENABLE | ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 43070125e0ac: 0000: c0012d00 00040200 00000008 4308 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4309 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST } 43100125e0b8: 0000: c0012d00 00040205 00080240 4311 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4312 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 4313 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 43140125e0c4: 0000: c0022d00 00040081 00000000 01000100 4315 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4316 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 43170125e0d4: 0000: c0012d00 00040204 00000000 4318 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4319 PA_CL_VPORT_XSCALE: 64.000000 4320 PA_CL_VPORT_XOFFSET: 64.000000 4321 PA_CL_VPORT_YSCALE: 64.000000 4322 PA_CL_VPORT_YOFFSET: 64.000000 43230125e0e0: 0000: c0042d00 0004010f 42800000 42800000 42800000 42800000 4324 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4325 RB_MODECONTROL: { EDRAM_MODE = EDRAM_COPY } 43260125e0f8: 0000: c0012d00 00040208 00000006 4327 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4328 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x10000 } 43290125e104: 0000: c0012d00 00040001 00010005 4330 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4331 RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 } 4332 RB_COPY_DEST_BASE: 0x10ca000 4333 RB_COPY_DEST_PITCH: 256 4334 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | LINEAR | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 43350125e110: 0000: c0042d00 00040318 00000000 010ca000 00000008 0003c058 4336 write CP_SCRATCH_REG7 (057f) 4337 CP_SCRATCH_REG7: 63 4338 :0,0,71,63 43390125e128: 0000: 0000057f 0000003f 4340 opcode: CP_DRAW_INDX (22) (3 dwords) 4341 { VIZ_QUERY = 0 } 4342 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 } 4343 draw: 0 4344 prim_type: DI_PT_RECTLIST (8) 4345 source_select: DI_SRC_SEL_AUTO_INDEX (2) 4346 num_indices: 1407 4347 draw[12] register values 4348!+ 00000047 CP_SCRATCH_REG6: 71 4349 :0,0,71,63 4350!+ 0000003f CP_SCRATCH_REG7: 63 4351 :0,0,71,63 4352 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 4353!+ 00000080 RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 } 4354!+ 00010005 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x10000 } 4355 + 00010001 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 } 4356 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 4357 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 4358!+ 01000100 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 4359 + 00000000 VGT_INDX_OFFSET: 0 4360 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 4361 + 00000000 RB_BLEND_RED: 0 4362 + 00000000 RB_BLEND_GREEN: 0 4363 + 00000000 RB_BLEND_BLUE: 0 4364!+ 00000000 RB_BLEND_ALPHA: 0 4365!+ 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 4366!+ 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 4367 + 00000000 RB_ALPHA_REF: 0 4368!+ 42800000 PA_CL_VPORT_XSCALE: 64.000000 4369!+ 42800000 PA_CL_VPORT_XOFFSET: 64.000000 4370!+ 42800000 PA_CL_VPORT_YSCALE: 64.000000 4371!+ 42800000 PA_CL_VPORT_YOFFSET: 64.000000 4372!+ 3f000000 PA_CL_VPORT_ZSCALE: 0.500000 4373!+ 3f000000 PA_CL_VPORT_ZOFFSET: 0.500000 4374 + 10038002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 4375 + 00000006 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 4376!+ 00000008 RB_DEPTHCONTROL: { EARLY_Z_ENABLE | ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 4377 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 4378!+ 00001c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 4379 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 4380!+ 00080240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST } 4381!+ 00000006 RB_MODECONTROL: { EDRAM_MODE = EDRAM_COPY } 4382!+ 00080008 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 4383!+ 00080008 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 4384!+ 00000008 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 4385 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 4386!+ 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 4387 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 4388 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 4389 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 4390 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 4391 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 4392 + 0000ffff PA_SC_AA_MASK: 0xffff 4393 + 00000000 RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 } 4394!+ 010ca000 RB_COPY_DEST_BASE: 0x10ca000 4395!+ 00000008 RB_COPY_DEST_PITCH: 256 4396!+ 0003c058 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | LINEAR | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 43970125e130: 0000: c0012200 00000000 00030088 4398 write CP_SCRATCH_REG7 (057f) 4399NEEDS WFI: CP_SCRATCH_REG7 (57f) 4400 CP_SCRATCH_REG7: 64 4401 :0,0,71,64 44020125e13c: 0000: 0000057f 00000040 4403 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4404 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 } 44050125e144: 0000: c0012d00 00040001 00000005 4406 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4407 RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 } 4408 RB_COPY_DEST_BASE: 0x108a000 4409 RB_COPY_DEST_PITCH: 256 4410 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 44110125e150: 0000: c0042d00 00040318 00000000 0108a000 00000008 0003c050 4412 write CP_SCRATCH_REG7 (057f) 4413NEEDS WFI: CP_SCRATCH_REG7 (57f) 4414 CP_SCRATCH_REG7: 65 4415 :0,0,71,65 44160125e168: 0000: 0000057f 00000041 4417 opcode: CP_DRAW_INDX (22) (3 dwords) 4418 { VIZ_QUERY = 0 } 4419 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 } 4420 draw: 1 4421 prim_type: DI_PT_RECTLIST (8) 4422 source_select: DI_SRC_SEL_AUTO_INDEX (2) 4423 num_indices: 1407 4424 draw[13] register values 4425!+ 00000041 CP_SCRATCH_REG7: 65 4426 :0,0,71,65 4427!+ 00000005 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 } 4428 + 00000000 RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 } 4429!+ 0108a000 RB_COPY_DEST_BASE: 0x108a000 4430 + 00000008 RB_COPY_DEST_PITCH: 256 4431!+ 0003c050 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 44320125e170: 0000: c0012200 00000000 00030088 4433 write CP_SCRATCH_REG7 (057f) 4434NEEDS WFI: CP_SCRATCH_REG7 (57f) 4435 CP_SCRATCH_REG7: 66 4436 :0,0,71,66 44370125e17c: 0000: 0000057f 00000042 4438 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4439 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 44400125e184: 0000: c0012d00 00040208 00000004 44410110a2ec: 0000: c0013700 0125e000 00000064 4442 nop 4443 write CP_SCRATCH_REG6 (057e) 4444NEEDS WFI: CP_SCRATCH_REG6 (57e) 4445 CP_SCRATCH_REG6: 72 4446 :0,0,72,66 44470110a2fc: 0000: 0000057e 00000048 4448 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4449 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 44500110a304: 0000: c0012d00 00040001 00000205 4451 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4452 PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } 4453 PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 } 44540110a310: 0000: c0022d00 0004000e 00000000 00800080 4455 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4456 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 44570110a320: 0000: c0012d00 00040001 00000205 4458 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4459 PA_SC_WINDOW_OFFSET: { X = -128 | Y = 0 } 44600110a32c: 0000: c0012d00 00040080 00007f80 4461 opcode: CP_MEM_WRITE (3d) (3 dwords) 4462 { ADDR_LO = 0x100903c } 4463 { ADDR_HI = 0x800080 } 4464 gpuaddr:0100903c 44650110a340: 0.000000 44660110a338: 0000: c0013d00 0100903c 00800080 4467 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4468 RB_COPY_DEST_OFFSET: { X = 128 | Y = 0 } 44690110a344: 0000: c0012d00 0004031c 00000080 4470 opcode: CP_SET_CONSTANT (2d) (6 dwords) 44710110a358: 128.000000 0.000000 0.000000 0.000000 44720110a350: 0000: c0042d00 00000580 43000000 00000000 00000000 00000000 4473 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4474 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 2 | ROW = 1 | GUARD_BAND_MASK = 0 } 44750110a368: 0000: c0012d00 00040207 0000000a 4476 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4477 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 2 | ROW = 1 | GUARD_BAND_MASK = 0 } 44780110a374: 0000: c0012d00 00040203 0000000a 4479 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 44800110a380: 0000: c0004b00 0111d000 4481 write CP_SCRATCH_REG6 (057e) 4482NEEDS WFI: CP_SCRATCH_REG6 (57e) 4483 CP_SCRATCH_REG6: 73 4484 :0,0,73,66 44850110a388: 0000: 0000057e 00000049 4486 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 4487 ibaddr:0110b000 4488 ibsize:00000198 44890110a390: 0000: c0013700 0110b000 00000198 4490 nop 4491 write CP_SCRATCH_REG6 (057e) 4492NEEDS WFI: CP_SCRATCH_REG6 (57e) 4493 CP_SCRATCH_REG6: 74 4494 :0,0,74,66 44950110a3a0: 0000: 0000057e 0000004a 4496 write CP_SCRATCH_REG6 (057e) 4497NEEDS WFI: CP_SCRATCH_REG6 (57e) 4498 CP_SCRATCH_REG6: 75 4499 :0,0,75,66 45000110a3a8: 0000: 0000057e 0000004b 4501 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 4502 ibaddr:0125e000 4503 ibsize:00000064 45040110a3b0: 0000: c0013700 0125e000 00000064 4505 nop 4506 write CP_SCRATCH_REG6 (057e) 4507NEEDS WFI: CP_SCRATCH_REG6 (57e) 4508 CP_SCRATCH_REG6: 76 4509 :0,0,76,66 45100110a3c0: 0000: 0000057e 0000004c 4511 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4512 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 45130110a3c8: 0000: c0012d00 00040001 00000205 4514 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4515 PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } 4516 PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 } 45170110a3d4: 0000: c0022d00 0004000e 00000000 00800080 4518 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4519 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 45200110a3e4: 0000: c0012d00 00040001 00000205 4521 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4522 PA_SC_WINDOW_OFFSET: { X = 0 | Y = -128 } 45230110a3f0: 0000: c0012d00 00040080 7f800000 4524 opcode: CP_MEM_WRITE (3d) (3 dwords) 4525 { ADDR_LO = 0x100903c } 4526 { ADDR_HI = 0x800080 } 4527 gpuaddr:0100903c 45280110a404: 0.000000 45290110a3fc: 0000: c0013d00 0100903c 00800080 4530 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4531 RB_COPY_DEST_OFFSET: { X = 0 | Y = 128 } 45320110a408: 0000: c0012d00 0004031c 00100000 4533 opcode: CP_SET_CONSTANT (2d) (6 dwords) 45340110a41c: 0.000000 128.000000 0.000000 0.000000 45350110a414: 0000: c0042d00 00000580 00000000 43000000 00000000 00000000 4536 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4537 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 1 | ROW = 2 | GUARD_BAND_MASK = 0 } 45380110a42c: 0000: c0012d00 00040207 00000011 4539 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4540 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 1 | ROW = 2 | GUARD_BAND_MASK = 0 } 45410110a438: 0000: c0012d00 00040203 00000011 4542 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 45430110a444: 0000: c0004b00 0111d000 4544 write CP_SCRATCH_REG6 (057e) 4545NEEDS WFI: CP_SCRATCH_REG6 (57e) 4546 CP_SCRATCH_REG6: 77 4547 :0,0,77,66 45480110a44c: 0000: 0000057e 0000004d 4549 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 4550 ibaddr:0110b000 4551 ibsize:00000198 45520110a454: 0000: c0013700 0110b000 00000198 4553 nop 4554 write CP_SCRATCH_REG6 (057e) 4555NEEDS WFI: CP_SCRATCH_REG6 (57e) 4556 CP_SCRATCH_REG6: 78 4557 :0,0,78,66 45580110a464: 0000: 0000057e 0000004e 4559 write CP_SCRATCH_REG6 (057e) 4560NEEDS WFI: CP_SCRATCH_REG6 (57e) 4561 CP_SCRATCH_REG6: 79 4562 :0,0,79,66 45630110a46c: 0000: 0000057e 0000004f 4564 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 4565 ibaddr:0125e000 4566 ibsize:00000064 45670110a474: 0000: c0013700 0125e000 00000064 4568 nop 4569 write CP_SCRATCH_REG6 (057e) 4570NEEDS WFI: CP_SCRATCH_REG6 (57e) 4571 CP_SCRATCH_REG6: 80 4572 :0,0,80,66 45730110a484: 0000: 0000057e 00000050 4574 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4575 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 45760110a48c: 0000: c0012d00 00040001 00000205 4577 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4578 PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } 4579 PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 } 45800110a498: 0000: c0022d00 0004000e 00000000 00800080 4581 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4582 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 45830110a4a8: 0000: c0012d00 00040001 00000205 4584 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4585 PA_SC_WINDOW_OFFSET: { X = -128 | Y = -128 } 45860110a4b4: 0000: c0012d00 00040080 7f807f80 4587 opcode: CP_MEM_WRITE (3d) (3 dwords) 4588 { ADDR_LO = 0x100903c } 4589 { ADDR_HI = 0x800080 } 4590 gpuaddr:0100903c 45910110a4c8: 0.000000 45920110a4c0: 0000: c0013d00 0100903c 00800080 4593 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4594 RB_COPY_DEST_OFFSET: { X = 128 | Y = 128 } 45950110a4cc: 0000: c0012d00 0004031c 00100080 4596 opcode: CP_SET_CONSTANT (2d) (6 dwords) 45970110a4e0: 128.000000 128.000000 0.000000 0.000000 45980110a4d8: 0000: c0042d00 00000580 43000000 43000000 00000000 00000000 4599 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4600 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 } 46010110a4f0: 0000: c0012d00 00040207 00000012 4602 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4603 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 } 46040110a4fc: 0000: c0012d00 00040203 00000012 4605 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 46060110a508: 0000: c0004b00 0111d000 4607 write CP_SCRATCH_REG6 (057e) 4608NEEDS WFI: CP_SCRATCH_REG6 (57e) 4609 CP_SCRATCH_REG6: 81 4610 :0,0,81,66 46110110a510: 0000: 0000057e 00000051 4612 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 4613 ibaddr:0110b000 4614 ibsize:00000198 46150110a518: 0000: c0013700 0110b000 00000198 4616 nop 4617 write CP_SCRATCH_REG6 (057e) 4618NEEDS WFI: CP_SCRATCH_REG6 (57e) 4619 CP_SCRATCH_REG6: 82 4620 :0,0,82,66 46210110a528: 0000: 0000057e 00000052 4622 write CP_SCRATCH_REG6 (057e) 4623NEEDS WFI: CP_SCRATCH_REG6 (57e) 4624 CP_SCRATCH_REG6: 83 4625 :0,0,83,66 46260110a530: 0000: 0000057e 00000053 4627 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 4628 ibaddr:0125e000 4629 ibsize:00000064 46300110a538: 0000: c0013700 0125e000 00000064 4631 nop 4632 write CP_SCRATCH_REG6 (057e) 4633NEEDS WFI: CP_SCRATCH_REG6 (57e) 4634 CP_SCRATCH_REG6: 84 4635 :0,0,84,66 46360110a548: 0000: 0000057e 00000054 4637############################################################ 4638vertices: 0 4639cmd: deqp-gles2/185: fence=1260 4640############################################################ 4641cmdstream[10]: 124 dwords 4642 write RB_BC_CONTROL (0f01) 4643NEEDS WFI: RB_BC_CONTROL (f01) 4644 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 46450122f000: 0000: 00000f01 1c004046 4646 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4647 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 46480122f008: 0000: c0012d00 00040293 00000020 4649 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4650 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 46510122f014: 0000: c0012d00 00040316 00000002 4652 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4653 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 46540122f020: 0000: c0012d00 00040317 00000002 4655 write CP_PERFMON_CNTL (0444) 4656NEEDS WFI: CP_PERFMON_CNTL (444) 4657 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 46580122f02c: 0000: 00000444 00000000 4659 write RBBM_PM_OVERRIDE1 (039c) 4660NEEDS WFI: RBBM_PM_OVERRIDE1 (39c) 4661 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 4662NEEDS WFI: RBBM_PM_OVERRIDE2 (39d) 4663 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 46640122f034: 0000: 0001039c ffffffff 00000fff 4665 write TP0_CHICKEN (0e1e) 4666NEEDS WFI: TP0_CHICKEN (e1e) 4667 TP0_CHICKEN: 0x2 46680122f040: 0000: 00000e1e 00000002 4669 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 46700122f048: 0000: c0003b00 00007fff 4671 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4672 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 46730122f050: 0000: c0012d00 00040307 00100020 4674 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4675 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 46760122f05c: 0000: c0012d00 00040308 000e0120 4677 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4678 VGT_MAX_VTX_INDX: 0xffffffff 4679 VGT_MIN_VTX_INDX: 0 46800122f068: 0000: c0022d00 00040100 ffffffff 00000000 4681 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4682 VGT_INDX_OFFSET: 0 46830122f078: 0000: c0012d00 00040102 00000000 4684 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4685 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 46860122f084: 0000: c0012d00 00040181 00000004 4687 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4688 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 46890122f090: 0000: c0012d00 00040182 ffffffff 4690 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4691 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 46920122f09c: 0000: c0012d00 00040301 00000000 4693 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4694 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 46950122f0a8: 0000: c0012d00 00040300 00000000 4696 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4697 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 46980122f0b4: 0000: c0012d00 00040080 00000000 4699 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4700 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 47010122f0c0: 0000: c0012d00 00040208 00000004 4702 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4703 RB_SAMPLE_POS: 0x88888888 47040122f0cc: 0000: c0012d00 0004020a 88888888 4705 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4706 RB_COLOR_DEST_MASK: 0xffffffff 47070122f0d8: 0000: c0012d00 00040326 ffffffff 4708 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4709 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 47100122f0e4: 0000: c0012d00 0004031b 0003c000 4711 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4712 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 4713 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 47140122f0f0: 0000: c0022d00 00040183 00000000 00000000 4715 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 47160122f100: 0000: c0004b00 00000000 4717 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 47180122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001 4719 write SQ_INST_STORE_MANAGMENT (0d02) 4720NEEDS WFI: SQ_INST_STORE_MANAGMENT (d02) 4721 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 47220122f11c: 0000: 00000d02 00000180 4723 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 47240122f124: 0000: c0003b00 00000300 4725 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 47260122f12c: 0000: c0004a00 80000180 4727 opcode: CP_SET_CONSTANT (2d) (14 dwords) 47280122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 47290122f15c: 2.000000 0.750000 0.375000 0.250000 47300122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 47310122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 4732 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4733 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 47340122f16c: 0000: c0012d00 00040104 0000000f 4735 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4736 RB_BLEND_RED: 0 4737 RB_BLEND_GREEN: 0 4738 RB_BLEND_BLUE: 0 4739 RB_BLEND_ALPHA: 0xff 47400122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 4741 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4742 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 47430122f190: 0000: c0012d00 00040206 0000043f 4744 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4745 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 } 47460122f19c: 0000: c0012d00 00040000 00000040 4747 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4748 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1256000 } 47490122f1a8: 0000: c0012d00 00040001 01256245 4750 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4751 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 4752 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 } 47530122f1b4: 0000: c0022d00 0004000e 80000000 00800040 4754 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4755 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 47560122f1c4: 0000: c0012d00 00040080 00000000 4757 write CP_SCRATCH_REG6 (057e) 4758NEEDS WFI: CP_SCRATCH_REG6 (57e) 4759 CP_SCRATCH_REG6: 89 4760 :0,0,89,66 47610122f1d0: 0000: 0000057e 00000059 4762 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 4763 ibaddr:0122e000 4764 ibsize:000000b6 4765 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4766 set shader const 0078 47670122e000: 0000: c0042d00 00010078 0112d4ef 00100000 0112d4ef 00100000 4768 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4769 PA_SC_AA_MASK: 0xffff 47700122e018: 0000: c0012d00 00040312 0000ffff 4771 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4772 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 47730122e024: 0000: c0012d00 00040200 00000000 4774 opcode: CP_SET_CONSTANT (2d) (5 dwords) 4775 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 4776 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 4777 RB_ALPHA_REF: 0 47780122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 4779 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4780 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 4781 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 47820122e044: 0000: c0022d00 00040204 00000000 00090244 4783 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4784 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 4785 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 4786 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 4787 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 47880122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 4789 opcode: CP_SET_CONSTANT (2d) (7 dwords) 4790 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 4791 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 4792 PA_CL_GB_VERT_DISC_ADJ: 1.000000 4793 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 4794 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 47950122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 4796 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4797 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 4798 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 } 47990122e088: 0000: c0022d00 00040081 00000000 00800040 4800 opcode: CP_SET_CONSTANT (2d) (8 dwords) 4801 PA_CL_VPORT_XSCALE: 32.000000 4802 PA_CL_VPORT_XOFFSET: 32.000000 4803 PA_CL_VPORT_YSCALE: 64.000000 4804 PA_CL_VPORT_YOFFSET: 64.000000 4805 PA_CL_VPORT_ZSCALE: 0.000000 4806 PA_CL_VPORT_ZOFFSET: 0.000000 48070122e098: 0000: c0062d00 0004010f 42000000 42000000 42800000 42800000 00000000 00000000 4808 opcode: CP_SET_CONSTANT (2d) (10 dwords) 48090122e0c0: 32.000000 64.000000 0.000000 0.000000 32.000000 64.000000 0.000000 0.000000 48100122e0b8: 0000: c0082d00 00000184 42000000 42800000 00000000 00000000 42000000 42800000 4811* 4812 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 4813 vertex shader, start=0000, size=0015 4814 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 4815 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 4816 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 4817 0000 0000 c200 ALLOC POSITION SIZE(0x0) 4818 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 4819 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 4820 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 4821 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 4822 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 4823 0000 0000 0000 NOP 48240122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 48250122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 48260122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 4827 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 4828 fragment shader, start=0000, size=000c 4829 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 4830 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 4831 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 4832 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 4833 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 4834 0000 0000 0000 NOP 48350122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 48360122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 4837 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4838 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 48390122e17c: 0000: c0012d00 00040181 00000106 4840 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4841 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 48420122e188: 0000: c0012d00 00040180 10030002 4843 opcode: CP_SET_CONSTANT (2d) (6 dwords) 48440122e19c: 0.000000 0.000000 0.000000 0.000000 48450122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 4846 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4847 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 48480122e1ac: 0000: c0012d00 00040202 00000c20 4849 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4850 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 48510122e1b8: 0000: c0012d00 00040201 00000000 4852 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4853 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 48540122e1c4: 0000: c0012d00 00040104 0000000f 4855 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4856 RB_BLEND_RED: 0 4857 RB_BLEND_GREEN: 0 4858 RB_BLEND_BLUE: 0 4859 RB_BLEND_ALPHA: 0 48600122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 4861 opcode: CP_SET_CONSTANT (2d) (8 dwords) 4862 set texture const 0000 4863 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 4864 filter min/mag: point/point 4865 swizzle: zyxw 4866 addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8 4867 mipaddr=00000000 (flags=200) 48680122e1e8: 0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200 4869 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4870 VGT_INDX_OFFSET: 0 48710122e208: 0000: c0012d00 00040102 00000000 4872 write TC_CNTL_STATUS (0e00) 4873NEEDS WFI: TC_CNTL_STATUS (e00) 4874 TC_CNTL_STATUS: { L2_INVALIDATE } 48750122e214: 0000: 00000e00 00000001 4876 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 48770122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 4878 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 48790122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 4880 write CP_SCRATCH_REG7 (057f) 4881NEEDS WFI: CP_SCRATCH_REG7 (57f) 4882 CP_SCRATCH_REG7: 85 4883 :0,0,89,85 48840122e24c: 0000: 0000057f 00000055 4885 opcode: CP_NOP (10) (2 dwords) 48860122e254: 0000: c0001000 00000000 4887 opcode: CP_DRAW_INDX (22) (3 dwords) 4888 { VIZ_QUERY = 0 } 4889 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 4890 draw: 0 4891 prim_type: DI_PT_TRIFAN (5) 4892 source_select: DI_SRC_SEL_AUTO_INDEX (2) 4893 num_indices: 1407 4894 draw[14] register values 4895 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 4896 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 4897 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 4898!+ 00000059 CP_SCRATCH_REG6: 89 4899 :0,0,89,85 4900!+ 00000055 CP_SCRATCH_REG7: 85 4901 :0,0,89,85 4902 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 4903 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 4904 + 00000002 TP0_CHICKEN: 0x2 4905 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 4906!+ 00000040 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 } 4907!+ 01256245 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1256000 } 4908!+ 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 4909!+ 00800040 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 } 4910 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 4911 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 4912!+ 00800040 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 } 4913 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 4914 + 00000000 VGT_MIN_VTX_INDX: 0 4915 + 00000000 VGT_INDX_OFFSET: 0 4916 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 4917 + 00000000 RB_BLEND_RED: 0 4918 + 00000000 RB_BLEND_GREEN: 0 4919 + 00000000 RB_BLEND_BLUE: 0 4920 + 00000000 RB_BLEND_ALPHA: 0 4921 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 4922 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 4923 + 00000000 RB_ALPHA_REF: 0 4924!+ 42000000 PA_CL_VPORT_XSCALE: 32.000000 4925!+ 42000000 PA_CL_VPORT_XOFFSET: 32.000000 4926 + 42800000 PA_CL_VPORT_YSCALE: 64.000000 4927 + 42800000 PA_CL_VPORT_YOFFSET: 64.000000 4928!+ 00000000 PA_CL_VPORT_ZSCALE: 0.000000 4929!+ 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 4930!+ 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 4931!+ 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 4932 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 4933 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 4934 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 4935!+ 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 4936 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 4937!+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 4938!+ 00000012 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 } 4939 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 4940!+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 4941 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 4942!+ 00000012 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 } 4943!+ 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 4944 + 88888888 RB_SAMPLE_POS: 0x88888888 4945!+ 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 4946!+ 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 4947!+ 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 4948 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 4949 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 4950 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 4951 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 4952 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 4953 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 4954 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 4955 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 4956 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 4957 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 4958 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 4959 + 0000ffff PA_SC_AA_MASK: 0xffff 4960 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 4961 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 4962!+ 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 4963!+ 00100080 RB_COPY_DEST_OFFSET: { X = 128 | Y = 128 } 4964 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 49650122e25c: 0000: c0012200 00000000 00040085 4966 write CP_SCRATCH_REG7 (057f) 4967NEEDS WFI: CP_SCRATCH_REG7 (57f) 4968 CP_SCRATCH_REG7: 86 4969 :0,0,89,86 49700122e268: 0000: 0000057f 00000056 4971 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 49720122e270: 0000: c0002600 00000000 4973 opcode: CP_EVENT_WRITE (46) (2 dwords) 4974 { EVENT = CACHE_FLUSH } 4975 event CACHE_FLUSH 49760122e278: 0000: c0004600 00000006 4977 opcode: CP_EVENT_WRITE (46) (2 dwords) 4978 { EVENT = CACHE_FLUSH } 4979 event CACHE_FLUSH 49800122e280: 0000: c0004600 00000006 4981 opcode: CP_EVENT_WRITE (46) (2 dwords) 4982 { EVENT = CACHE_FLUSH } 4983 event CACHE_FLUSH 49840122e288: 0000: c0004600 00000006 4985 opcode: CP_EVENT_WRITE (46) (2 dwords) 4986 { EVENT = CACHE_FLUSH } 4987 event CACHE_FLUSH 49880122e290: 0000: c0004600 00000006 4989 opcode: CP_EVENT_WRITE (46) (2 dwords) 4990 { EVENT = CACHE_FLUSH } 4991 event CACHE_FLUSH 49920122e298: 0000: c0004600 00000006 4993 opcode: CP_EVENT_WRITE (46) (2 dwords) 4994 { EVENT = CACHE_FLUSH } 4995 event CACHE_FLUSH 49960122e2a0: 0000: c0004600 00000006 4997 opcode: CP_EVENT_WRITE (46) (2 dwords) 4998 { EVENT = CACHE_FLUSH } 4999 event CACHE_FLUSH 50000122e2a8: 0000: c0004600 00000006 5001 opcode: CP_EVENT_WRITE (46) (2 dwords) 5002 { EVENT = CACHE_FLUSH } 5003 event CACHE_FLUSH 50040122e2b0: 0000: c0004600 00000006 5005 opcode: CP_EVENT_WRITE (46) (2 dwords) 5006 { EVENT = CACHE_FLUSH } 5007 event CACHE_FLUSH 50080122e2b8: 0000: c0004600 00000006 5009 opcode: CP_EVENT_WRITE (46) (2 dwords) 5010 { EVENT = CACHE_FLUSH } 5011 event CACHE_FLUSH 50120122e2c0: 0000: c0004600 00000006 5013 opcode: CP_EVENT_WRITE (46) (2 dwords) 5014 { EVENT = CACHE_FLUSH } 5015 event CACHE_FLUSH 50160122e2c8: 0000: c0004600 00000006 5017 opcode: CP_EVENT_WRITE (46) (2 dwords) 5018 { EVENT = CACHE_FLUSH } 5019 event CACHE_FLUSH 50200122e2d0: 0000: c0004600 00000006 50210122f1d8: 0000: c0013700 0122e000 000000b6 5022 nop 5023 write CP_SCRATCH_REG6 (057e) 5024 CP_SCRATCH_REG6: 90 5025 :0,0,90,86 50260122f1e8: 0000: 0000057e 0000005a 5027############################################################ 5028vertices: 0 5029cmd: deqp-gles2/185: fence=1261 5030############################################################ 5031cmdstream[11]: 124 dwords 5032 write RB_BC_CONTROL (0f01) 5033 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 50340110c000: 0000: 00000f01 1c004046 5035 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5036 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 50370110c008: 0000: c0012d00 00040293 00000020 5038 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5039 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 50400110c014: 0000: c0012d00 00040316 00000002 5041 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5042 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 50430110c020: 0000: c0012d00 00040317 00000002 5044 write CP_PERFMON_CNTL (0444) 5045 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 50460110c02c: 0000: 00000444 00000000 5047 write RBBM_PM_OVERRIDE1 (039c) 5048 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 5049 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 50500110c034: 0000: 0001039c ffffffff 00000fff 5051 write TP0_CHICKEN (0e1e) 5052 TP0_CHICKEN: 0x2 50530110c040: 0000: 00000e1e 00000002 5054 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 50550110c048: 0000: c0003b00 00007fff 5056 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5057 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 50580110c050: 0000: c0012d00 00040307 00100020 5059 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5060 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 50610110c05c: 0000: c0012d00 00040308 000e0120 5062 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5063 VGT_MAX_VTX_INDX: 0xffffffff 5064 VGT_MIN_VTX_INDX: 0 50650110c068: 0000: c0022d00 00040100 ffffffff 00000000 5066 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5067 VGT_INDX_OFFSET: 0 50680110c078: 0000: c0012d00 00040102 00000000 5069 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5070 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 50710110c084: 0000: c0012d00 00040181 00000004 5072 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5073 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 50740110c090: 0000: c0012d00 00040182 ffffffff 5075 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5076 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 50770110c09c: 0000: c0012d00 00040301 00000000 5078 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5079 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 50800110c0a8: 0000: c0012d00 00040300 00000000 5081 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5082 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 50830110c0b4: 0000: c0012d00 00040080 00000000 5084 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5085 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 50860110c0c0: 0000: c0012d00 00040208 00000004 5087 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5088 RB_SAMPLE_POS: 0x88888888 50890110c0cc: 0000: c0012d00 0004020a 88888888 5090 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5091 RB_COLOR_DEST_MASK: 0xffffffff 50920110c0d8: 0000: c0012d00 00040326 ffffffff 5093 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5094 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 50950110c0e4: 0000: c0012d00 0004031b 0003c000 5096 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5097 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 5098 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 50990110c0f0: 0000: c0022d00 00040183 00000000 00000000 5100 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 51010110c100: 0000: c0004b00 00000000 5102 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 51030110c108: 0000: c0035200 000005d0 00000000 5f601000 00000001 5104 write SQ_INST_STORE_MANAGMENT (0d02) 5105 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 51060110c11c: 0000: 00000d02 00000180 5107 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 51080110c124: 0000: c0003b00 00000300 5109 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 51100110c12c: 0000: c0004a00 80000180 5111 opcode: CP_SET_CONSTANT (2d) (14 dwords) 51120110c13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 51130110c15c: 2.000000 0.750000 0.375000 0.250000 51140110c134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 51150110c154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 5116 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5117 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 51180110c16c: 0000: c0012d00 00040104 0000000f 5119 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5120 RB_BLEND_RED: 0 5121 RB_BLEND_GREEN: 0 5122 RB_BLEND_BLUE: 0 5123 RB_BLEND_ALPHA: 0xff 51240110c178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 5125 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5126 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 51270110c190: 0000: c0012d00 00040206 0000043f 5128 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5129 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 } 51300110c19c: 0000: c0012d00 00040000 00000100 5131 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5132 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 } 51330110c1a8: 0000: c0012d00 00040001 0108a205 5134 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5135 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 5136 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 } 51370110c1b4: 0000: c0022d00 0004000e 80000000 01000100 5138 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5139 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 51400110c1c4: 0000: c0012d00 00040080 00000000 5141 write CP_SCRATCH_REG6 (057e) 5142 CP_SCRATCH_REG6: 95 5143 :0,0,95,86 51440110c1d0: 0000: 0000057e 0000005f 5145 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 5146 ibaddr:0110b000 5147 ibsize:000000b8 5148 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5149 set shader const 0078 51500110b000: 0000: c0042d00 00010078 0112d56f 00100000 0112d5af 00100000 5151 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5152 PA_SC_AA_MASK: 0xffff 51530110b018: 0000: c0012d00 00040312 0000ffff 5154 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5155 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 51560110b024: 0000: c0012d00 00040200 00000000 5157 opcode: CP_SET_CONSTANT (2d) (5 dwords) 5158 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5159 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5160 RB_ALPHA_REF: 0 51610110b030: 0000: c0032d00 0004010c 00000000 00000000 00000000 5162 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5163 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 5164 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 51650110b044: 0000: c0022d00 00040204 00000000 00090240 5166 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5167 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 5168 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 5169 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 5170 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 51710110b054: 0000: c0042d00 00040280 00080008 00080008 00000008 00000000 5172 opcode: CP_SET_CONSTANT (2d) (7 dwords) 5173 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 5174 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 5175 PA_CL_GB_VERT_DISC_ADJ: 1.000000 5176 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 5177 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 51780110b06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 5179 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5180 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 5181 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 51820110b088: 0000: c0022d00 00040081 00000000 01000100 5183 opcode: CP_SET_CONSTANT (2d) (8 dwords) 5184 PA_CL_VPORT_XSCALE: 128.000000 5185 PA_CL_VPORT_XOFFSET: 128.000000 5186 PA_CL_VPORT_YSCALE: -128.000000 5187 PA_CL_VPORT_YOFFSET: 128.000000 5188 PA_CL_VPORT_ZSCALE: 0.500000 5189 PA_CL_VPORT_ZOFFSET: 0.500000 51900110b098: 0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000 5191 opcode: CP_SET_CONSTANT (2d) (10 dwords) 51920110b0c0: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000 51930110b0b8: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000 51940110b0d8: 0020: 3f000000 00000000 5195 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 5196 vertex shader, start=0000, size=0015 5197 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 5198 03: 19481000 00262688 00000010 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0) 5199 04: 13480000 40252fc8 00000008 FETCH: VERTEX R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1) 5200 0000 0000 c200 ALLOC POSITION SIZE(0x0) 5201 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 5202 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 5203 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 5204 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 5205 06: 00038000 00000000 c2000000 ALU: MAXv export0.xy__ = R0, R0 5206 0000 0000 0000 NOP 52070110b0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 52080110b100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000 52090110b120: 0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000 5210 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 5211 fragment shader, start=0000, size=000c 5212 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 5213 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 5214 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 5215 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 5216 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 5217 0000 0000 0000 NOP 52180110b140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 52190110b160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 5220 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5221 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 52220110b17c: 0000: c0012d00 00040181 00000106 5223 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5224 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 52250110b188: 0000: c0012d00 00040180 10030002 5226 opcode: CP_SET_CONSTANT (2d) (6 dwords) 52270110b19c: 0.000000 0.000000 0.000000 0.000000 52280110b194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 5229 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5230 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 52310110b1ac: 0000: c0012d00 00040202 00001c20 5232 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5233 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 52340110b1b8: 0000: c0012d00 00040201 00000000 5235 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5236 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 52370110b1c4: 0000: c0012d00 00040104 0000000f 5238 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5239 RB_BLEND_RED: 0 5240 RB_BLEND_GREEN: 0 5241 RB_BLEND_BLUE: 0 5242 RB_BLEND_ALPHA: 0 52430110b1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 5244 opcode: CP_SET_CONSTANT (2d) (8 dwords) 5245 set texture const 0000 5246 clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap 5247 filter min/mag: point/point 5248 swizzle: xyzw 5249 addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE 5250 mipaddr=01240000 (flags=200) 52510110b1e8: 0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200 5252 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5253 VGT_INDX_OFFSET: 0 52540110b208: 0000: c0012d00 00040102 00000000 5255 write TC_CNTL_STATUS (0e00) 5256 TC_CNTL_STATUS: { L2_INVALIDATE } 52570110b214: 0000: 00000e00 00000001 5258 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 52590110b21c: 0000: c0035200 000005d0 00000000 00001000 00000001 5260 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 52610110b230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 5262 write CP_SCRATCH_REG7 (057f) 5263 CP_SCRATCH_REG7: 91 5264 :0,0,95,91 52650110b24c: 0000: 0000057f 0000005b 5266 opcode: CP_NOP (10) (2 dwords) 52670110b254: 0000: c0001000 00000000 5268 opcode: CP_DRAW_INDX (22) (5 dwords) 5269 { VIZ_QUERY = 0 } 5270 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 } 5271 { NUM_INDICES = 18011596 } 5272 { INDX_BASE = 0xc } 5273 draw: 0 5274 prim_type: DI_PT_TRILIST (4) 5275 source_select: DI_SRC_SEL_DMA (0) 5276 num_indices: 18011596 5277 draw[15] register values 5278 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 5279 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 5280 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 5281!+ 0000005f CP_SCRATCH_REG6: 95 5282 :0,0,95,91 5283!+ 0000005b CP_SCRATCH_REG7: 91 5284 :0,0,95,91 5285 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 5286 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 5287 + 00000002 TP0_CHICKEN: 0x2 5288 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 5289!+ 00000100 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 } 5290!+ 0108a205 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 } 5291 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 5292!+ 01000100 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 } 5293 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 5294 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 5295!+ 01000100 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 5296 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 5297 + 00000000 VGT_MIN_VTX_INDX: 0 5298 + 00000000 VGT_INDX_OFFSET: 0 5299 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 5300 + 00000000 RB_BLEND_RED: 0 5301 + 00000000 RB_BLEND_GREEN: 0 5302 + 00000000 RB_BLEND_BLUE: 0 5303 + 00000000 RB_BLEND_ALPHA: 0 5304 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5305 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5306 + 00000000 RB_ALPHA_REF: 0 5307!+ 43000000 PA_CL_VPORT_XSCALE: 128.000000 5308!+ 43000000 PA_CL_VPORT_XOFFSET: 128.000000 5309!+ c3000000 PA_CL_VPORT_YSCALE: -128.000000 5310!+ 43000000 PA_CL_VPORT_YOFFSET: 128.000000 5311!+ 3f000000 PA_CL_VPORT_ZSCALE: 0.500000 5312!+ 3f000000 PA_CL_VPORT_ZOFFSET: 0.500000 5313 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 5314 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 5315 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 5316 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 5317 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 5318 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 5319 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 5320!+ 00001c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 5321 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 5322!+ 00090240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 5323 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 5324 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 5325 + 88888888 RB_SAMPLE_POS: 0x88888888 5326!+ 00080008 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 5327!+ 00080008 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 5328!+ 00000008 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 5329 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 5330 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 5331 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 5332 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 5333 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 5334 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 5335 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 5336 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 5337 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 5338 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 5339 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 5340 + 0000ffff PA_SC_AA_MASK: 0xffff 5341 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 5342 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 5343 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 5344 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 53450110b25c: 0000: c0032200 00000000 00060004 0112d5cc 0000000c 5346 write CP_SCRATCH_REG7 (057f) 5347NEEDS WFI: CP_SCRATCH_REG7 (57f) 5348 CP_SCRATCH_REG7: 92 5349 :0,0,95,92 53500110b270: 0000: 0000057f 0000005c 5351 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 53520110b278: 0000: c0002600 00000000 5353 opcode: CP_EVENT_WRITE (46) (2 dwords) 5354 { EVENT = CACHE_FLUSH } 5355 event CACHE_FLUSH 53560110b280: 0000: c0004600 00000006 5357 opcode: CP_EVENT_WRITE (46) (2 dwords) 5358 { EVENT = CACHE_FLUSH } 5359 event CACHE_FLUSH 53600110b288: 0000: c0004600 00000006 5361 opcode: CP_EVENT_WRITE (46) (2 dwords) 5362 { EVENT = CACHE_FLUSH } 5363 event CACHE_FLUSH 53640110b290: 0000: c0004600 00000006 5365 opcode: CP_EVENT_WRITE (46) (2 dwords) 5366 { EVENT = CACHE_FLUSH } 5367 event CACHE_FLUSH 53680110b298: 0000: c0004600 00000006 5369 opcode: CP_EVENT_WRITE (46) (2 dwords) 5370 { EVENT = CACHE_FLUSH } 5371 event CACHE_FLUSH 53720110b2a0: 0000: c0004600 00000006 5373 opcode: CP_EVENT_WRITE (46) (2 dwords) 5374 { EVENT = CACHE_FLUSH } 5375 event CACHE_FLUSH 53760110b2a8: 0000: c0004600 00000006 5377 opcode: CP_EVENT_WRITE (46) (2 dwords) 5378 { EVENT = CACHE_FLUSH } 5379 event CACHE_FLUSH 53800110b2b0: 0000: c0004600 00000006 5381 opcode: CP_EVENT_WRITE (46) (2 dwords) 5382 { EVENT = CACHE_FLUSH } 5383 event CACHE_FLUSH 53840110b2b8: 0000: c0004600 00000006 5385 opcode: CP_EVENT_WRITE (46) (2 dwords) 5386 { EVENT = CACHE_FLUSH } 5387 event CACHE_FLUSH 53880110b2c0: 0000: c0004600 00000006 5389 opcode: CP_EVENT_WRITE (46) (2 dwords) 5390 { EVENT = CACHE_FLUSH } 5391 event CACHE_FLUSH 53920110b2c8: 0000: c0004600 00000006 5393 opcode: CP_EVENT_WRITE (46) (2 dwords) 5394 { EVENT = CACHE_FLUSH } 5395 event CACHE_FLUSH 53960110b2d0: 0000: c0004600 00000006 5397 opcode: CP_EVENT_WRITE (46) (2 dwords) 5398 { EVENT = CACHE_FLUSH } 5399 event CACHE_FLUSH 54000110b2d8: 0000: c0004600 00000006 54010110c1d8: 0000: c0013700 0110b000 000000b8 5402 nop 5403 write CP_SCRATCH_REG6 (057e) 5404 CP_SCRATCH_REG6: 96 5405 :0,0,96,92 54060110c1e8: 0000: 0000057e 00000060 5407############################################################ 5408vertices: 0 5409cmd: deqp-gles2/185: fence=1262 5410############################################################ 5411cmdstream[12]: 124 dwords 5412 write RB_BC_CONTROL (0f01) 5413 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 54140122d000: 0000: 00000f01 1c004046 5415 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5416 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 54170122d008: 0000: c0012d00 00040293 00000020 5418 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5419 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 54200122d014: 0000: c0012d00 00040316 00000002 5421 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5422 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 54230122d020: 0000: c0012d00 00040317 00000002 5424 write CP_PERFMON_CNTL (0444) 5425 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 54260122d02c: 0000: 00000444 00000000 5427 write RBBM_PM_OVERRIDE1 (039c) 5428 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 5429 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 54300122d034: 0000: 0001039c ffffffff 00000fff 5431 write TP0_CHICKEN (0e1e) 5432 TP0_CHICKEN: 0x2 54330122d040: 0000: 00000e1e 00000002 5434 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 54350122d048: 0000: c0003b00 00007fff 5436 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5437 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 54380122d050: 0000: c0012d00 00040307 00100020 5439 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5440 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 54410122d05c: 0000: c0012d00 00040308 000e0120 5442 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5443 VGT_MAX_VTX_INDX: 0xffffffff 5444 VGT_MIN_VTX_INDX: 0 54450122d068: 0000: c0022d00 00040100 ffffffff 00000000 5446 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5447 VGT_INDX_OFFSET: 0 54480122d078: 0000: c0012d00 00040102 00000000 5449 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5450 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 54510122d084: 0000: c0012d00 00040181 00000004 5452 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5453 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 54540122d090: 0000: c0012d00 00040182 ffffffff 5455 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5456 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 54570122d09c: 0000: c0012d00 00040301 00000000 5458 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5459 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 54600122d0a8: 0000: c0012d00 00040300 00000000 5461 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5462 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 54630122d0b4: 0000: c0012d00 00040080 00000000 5464 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5465 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 54660122d0c0: 0000: c0012d00 00040208 00000004 5467 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5468 RB_SAMPLE_POS: 0x88888888 54690122d0cc: 0000: c0012d00 0004020a 88888888 5470 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5471 RB_COLOR_DEST_MASK: 0xffffffff 54720122d0d8: 0000: c0012d00 00040326 ffffffff 5473 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5474 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 54750122d0e4: 0000: c0012d00 0004031b 0003c000 5476 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5477 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 5478 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 54790122d0f0: 0000: c0022d00 00040183 00000000 00000000 5480 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 54810122d100: 0000: c0004b00 00000000 5482 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 54830122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001 5484 write SQ_INST_STORE_MANAGMENT (0d02) 5485 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 54860122d11c: 0000: 00000d02 00000180 5487 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 54880122d124: 0000: c0003b00 00000300 5489 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 54900122d12c: 0000: c0004a00 80000180 5491 opcode: CP_SET_CONSTANT (2d) (14 dwords) 54920122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 54930122d15c: 2.000000 0.750000 0.375000 0.250000 54940122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 54950122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 5496 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5497 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 54980122d16c: 0000: c0012d00 00040104 0000000f 5499 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5500 RB_BLEND_RED: 0 5501 RB_BLEND_GREEN: 0 5502 RB_BLEND_BLUE: 0 5503 RB_BLEND_ALPHA: 0xff 55040122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 5505 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5506 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 55070122d190: 0000: c0012d00 00040206 0000043f 5508 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5509 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 55100122d19c: 0000: c0012d00 00040000 00000020 5511 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5512 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1254000 } 55130122d1a8: 0000: c0012d00 00040001 01254245 5514 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5515 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 5516 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 } 55170122d1b4: 0000: c0022d00 0004000e 80000000 00400020 5518 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5519 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 55200122d1c4: 0000: c0012d00 00040080 00000000 5521 write CP_SCRATCH_REG6 (057e) 5522 CP_SCRATCH_REG6: 101 5523 :0,0,101,92 55240122d1d0: 0000: 0000057e 00000065 5525 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 5526 ibaddr:0122e000 5527 ibsize:000000b6 5528 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5529 set shader const 0078 55300122e000: 0000: c0042d00 00010078 0112d5db 00100000 0112d5db 00100000 5531 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5532 PA_SC_AA_MASK: 0xffff 55330122e018: 0000: c0012d00 00040312 0000ffff 5534 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5535 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 55360122e024: 0000: c0012d00 00040200 00000000 5537 opcode: CP_SET_CONSTANT (2d) (5 dwords) 5538 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5539 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5540 RB_ALPHA_REF: 0 55410122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 5542 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5543 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 5544 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 55450122e044: 0000: c0022d00 00040204 00000000 00090244 5546 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5547 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 5548 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 5549 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 5550 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 55510122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 5552 opcode: CP_SET_CONSTANT (2d) (7 dwords) 5553 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 5554 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 5555 PA_CL_GB_VERT_DISC_ADJ: 1.000000 5556 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 5557 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 55580122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 5559 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5560 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 5561 PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 } 55620122e088: 0000: c0022d00 00040081 00000000 00400020 5563 opcode: CP_SET_CONSTANT (2d) (8 dwords) 5564 PA_CL_VPORT_XSCALE: 16.000000 5565 PA_CL_VPORT_XOFFSET: 16.000000 5566 PA_CL_VPORT_YSCALE: 32.000000 5567 PA_CL_VPORT_YOFFSET: 32.000000 5568 PA_CL_VPORT_ZSCALE: 0.000000 5569 PA_CL_VPORT_ZOFFSET: 0.000000 55700122e098: 0000: c0062d00 0004010f 41800000 41800000 42000000 42000000 00000000 00000000 5571 opcode: CP_SET_CONSTANT (2d) (10 dwords) 55720122e0c0: 16.000000 32.000000 0.000000 0.000000 16.000000 32.000000 0.000000 0.000000 55730122e0b8: 0000: c0082d00 00000184 41800000 42000000 00000000 00000000 41800000 42000000 5574* 5575 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 5576 vertex shader, start=0000, size=0015 5577 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 5578 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 5579 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 5580 0000 0000 c200 ALLOC POSITION SIZE(0x0) 5581 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 5582 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 5583 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 5584 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 5585 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 5586 0000 0000 0000 NOP 55870122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 55880122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 55890122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 5590 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 5591 fragment shader, start=0000, size=000c 5592 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 5593 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 5594 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 5595 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 5596 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 5597 0000 0000 0000 NOP 55980122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 55990122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 5600 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5601 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 56020122e17c: 0000: c0012d00 00040181 00000106 5603 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5604 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 56050122e188: 0000: c0012d00 00040180 10030002 5606 opcode: CP_SET_CONSTANT (2d) (6 dwords) 56070122e19c: 0.000000 0.000000 0.000000 0.000000 56080122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 5609 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5610 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 56110122e1ac: 0000: c0012d00 00040202 00000c20 5612 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5613 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 56140122e1b8: 0000: c0012d00 00040201 00000000 5615 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5616 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 56170122e1c4: 0000: c0012d00 00040104 0000000f 5618 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5619 RB_BLEND_RED: 0 5620 RB_BLEND_GREEN: 0 5621 RB_BLEND_BLUE: 0 5622 RB_BLEND_ALPHA: 0 56230122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 5624 opcode: CP_SET_CONSTANT (2d) (8 dwords) 5625 set texture const 0000 5626 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 5627 filter min/mag: point/point 5628 swizzle: zyxw 5629 addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8 5630 mipaddr=00000000 (flags=200) 56310122e1e8: 0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200 5632 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5633 VGT_INDX_OFFSET: 0 56340122e208: 0000: c0012d00 00040102 00000000 5635 write TC_CNTL_STATUS (0e00) 5636 TC_CNTL_STATUS: { L2_INVALIDATE } 56370122e214: 0000: 00000e00 00000001 5638 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 56390122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 5640 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 56410122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 5642 write CP_SCRATCH_REG7 (057f) 5643 CP_SCRATCH_REG7: 97 5644 :0,0,101,97 56450122e24c: 0000: 0000057f 00000061 5646 opcode: CP_NOP (10) (2 dwords) 56470122e254: 0000: c0001000 00000000 5648 opcode: CP_DRAW_INDX (22) (3 dwords) 5649 { VIZ_QUERY = 0 } 5650 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 5651 draw: 0 5652 prim_type: DI_PT_TRIFAN (5) 5653 source_select: DI_SRC_SEL_AUTO_INDEX (2) 5654 num_indices: 1407 5655 draw[16] register values 5656 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 5657 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 5658 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 5659!+ 00000065 CP_SCRATCH_REG6: 101 5660 :0,0,101,97 5661!+ 00000061 CP_SCRATCH_REG7: 97 5662 :0,0,101,97 5663 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 5664 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 5665 + 00000002 TP0_CHICKEN: 0x2 5666 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 5667!+ 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 5668!+ 01254245 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1254000 } 5669 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 5670!+ 00400020 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 } 5671 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 5672 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 5673!+ 00400020 PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 } 5674 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 5675 + 00000000 VGT_MIN_VTX_INDX: 0 5676 + 00000000 VGT_INDX_OFFSET: 0 5677 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 5678 + 00000000 RB_BLEND_RED: 0 5679 + 00000000 RB_BLEND_GREEN: 0 5680 + 00000000 RB_BLEND_BLUE: 0 5681 + 00000000 RB_BLEND_ALPHA: 0 5682 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5683 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5684 + 00000000 RB_ALPHA_REF: 0 5685!+ 41800000 PA_CL_VPORT_XSCALE: 16.000000 5686!+ 41800000 PA_CL_VPORT_XOFFSET: 16.000000 5687!+ 42000000 PA_CL_VPORT_YSCALE: 32.000000 5688!+ 42000000 PA_CL_VPORT_YOFFSET: 32.000000 5689!+ 00000000 PA_CL_VPORT_ZSCALE: 0.000000 5690!+ 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 5691 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 5692 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 5693 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 5694 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 5695 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 5696 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 5697 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 5698!+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 5699 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 5700!+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 5701 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 5702 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 5703 + 88888888 RB_SAMPLE_POS: 0x88888888 5704!+ 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 5705!+ 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 5706!+ 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 5707 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 5708 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 5709 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 5710 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 5711 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 5712 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 5713 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 5714 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 5715 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 5716 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 5717 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 5718 + 0000ffff PA_SC_AA_MASK: 0xffff 5719 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 5720 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 5721 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 5722 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 57230122e25c: 0000: c0012200 00000000 00040085 5724 write CP_SCRATCH_REG7 (057f) 5725NEEDS WFI: CP_SCRATCH_REG7 (57f) 5726 CP_SCRATCH_REG7: 98 5727 :0,0,101,98 57280122e268: 0000: 0000057f 00000062 5729 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 57300122e270: 0000: c0002600 00000000 5731 opcode: CP_EVENT_WRITE (46) (2 dwords) 5732 { EVENT = CACHE_FLUSH } 5733 event CACHE_FLUSH 57340122e278: 0000: c0004600 00000006 5735 opcode: CP_EVENT_WRITE (46) (2 dwords) 5736 { EVENT = CACHE_FLUSH } 5737 event CACHE_FLUSH 57380122e280: 0000: c0004600 00000006 5739 opcode: CP_EVENT_WRITE (46) (2 dwords) 5740 { EVENT = CACHE_FLUSH } 5741 event CACHE_FLUSH 57420122e288: 0000: c0004600 00000006 5743 opcode: CP_EVENT_WRITE (46) (2 dwords) 5744 { EVENT = CACHE_FLUSH } 5745 event CACHE_FLUSH 57460122e290: 0000: c0004600 00000006 5747 opcode: CP_EVENT_WRITE (46) (2 dwords) 5748 { EVENT = CACHE_FLUSH } 5749 event CACHE_FLUSH 57500122e298: 0000: c0004600 00000006 5751 opcode: CP_EVENT_WRITE (46) (2 dwords) 5752 { EVENT = CACHE_FLUSH } 5753 event CACHE_FLUSH 57540122e2a0: 0000: c0004600 00000006 5755 opcode: CP_EVENT_WRITE (46) (2 dwords) 5756 { EVENT = CACHE_FLUSH } 5757 event CACHE_FLUSH 57580122e2a8: 0000: c0004600 00000006 5759 opcode: CP_EVENT_WRITE (46) (2 dwords) 5760 { EVENT = CACHE_FLUSH } 5761 event CACHE_FLUSH 57620122e2b0: 0000: c0004600 00000006 5763 opcode: CP_EVENT_WRITE (46) (2 dwords) 5764 { EVENT = CACHE_FLUSH } 5765 event CACHE_FLUSH 57660122e2b8: 0000: c0004600 00000006 5767 opcode: CP_EVENT_WRITE (46) (2 dwords) 5768 { EVENT = CACHE_FLUSH } 5769 event CACHE_FLUSH 57700122e2c0: 0000: c0004600 00000006 5771 opcode: CP_EVENT_WRITE (46) (2 dwords) 5772 { EVENT = CACHE_FLUSH } 5773 event CACHE_FLUSH 57740122e2c8: 0000: c0004600 00000006 5775 opcode: CP_EVENT_WRITE (46) (2 dwords) 5776 { EVENT = CACHE_FLUSH } 5777 event CACHE_FLUSH 57780122e2d0: 0000: c0004600 00000006 57790122d1d8: 0000: c0013700 0122e000 000000b6 5780 nop 5781 write CP_SCRATCH_REG6 (057e) 5782 CP_SCRATCH_REG6: 102 5783 :0,0,102,98 57840122d1e8: 0000: 0000057e 00000066 5785############################################################ 5786vertices: 0 5787cmd: deqp-gles2/185: fence=1263 5788############################################################ 5789cmdstream[13]: 124 dwords 5790 write RB_BC_CONTROL (0f01) 5791 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 57920110a000: 0000: 00000f01 1c004046 5793 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5794 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 57950110a008: 0000: c0012d00 00040293 00000020 5796 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5797 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 57980110a014: 0000: c0012d00 00040316 00000002 5799 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5800 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 58010110a020: 0000: c0012d00 00040317 00000002 5802 write CP_PERFMON_CNTL (0444) 5803 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 58040110a02c: 0000: 00000444 00000000 5805 write RBBM_PM_OVERRIDE1 (039c) 5806 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 5807 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 58080110a034: 0000: 0001039c ffffffff 00000fff 5809 write TP0_CHICKEN (0e1e) 5810 TP0_CHICKEN: 0x2 58110110a040: 0000: 00000e1e 00000002 5812 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 58130110a048: 0000: c0003b00 00007fff 5814 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5815 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 58160110a050: 0000: c0012d00 00040307 00100020 5817 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5818 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 58190110a05c: 0000: c0012d00 00040308 000e0120 5820 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5821 VGT_MAX_VTX_INDX: 0xffffffff 5822 VGT_MIN_VTX_INDX: 0 58230110a068: 0000: c0022d00 00040100 ffffffff 00000000 5824 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5825 VGT_INDX_OFFSET: 0 58260110a078: 0000: c0012d00 00040102 00000000 5827 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5828 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 58290110a084: 0000: c0012d00 00040181 00000004 5830 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5831 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 58320110a090: 0000: c0012d00 00040182 ffffffff 5833 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5834 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 58350110a09c: 0000: c0012d00 00040301 00000000 5836 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5837 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 58380110a0a8: 0000: c0012d00 00040300 00000000 5839 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5840 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 58410110a0b4: 0000: c0012d00 00040080 00000000 5842 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5843 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 58440110a0c0: 0000: c0012d00 00040208 00000004 5845 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5846 RB_SAMPLE_POS: 0x88888888 58470110a0cc: 0000: c0012d00 0004020a 88888888 5848 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5849 RB_COLOR_DEST_MASK: 0xffffffff 58500110a0d8: 0000: c0012d00 00040326 ffffffff 5851 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5852 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 58530110a0e4: 0000: c0012d00 0004031b 0003c000 5854 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5855 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 5856 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 58570110a0f0: 0000: c0022d00 00040183 00000000 00000000 5858 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 58590110a100: 0000: c0004b00 00000000 5860 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 58610110a108: 0000: c0035200 000005d0 00000000 5f601000 00000001 5862 write SQ_INST_STORE_MANAGMENT (0d02) 5863 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 58640110a11c: 0000: 00000d02 00000180 5865 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 58660110a124: 0000: c0003b00 00000300 5867 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 58680110a12c: 0000: c0004a00 80000180 5869 opcode: CP_SET_CONSTANT (2d) (14 dwords) 58700110a13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 58710110a15c: 2.000000 0.750000 0.375000 0.250000 58720110a134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 58730110a154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 5874 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5875 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 58760110a16c: 0000: c0012d00 00040104 0000000f 5877 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5878 RB_BLEND_RED: 0 5879 RB_BLEND_GREEN: 0 5880 RB_BLEND_BLUE: 0 5881 RB_BLEND_ALPHA: 0xff 58820110a178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 5883 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5884 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 58850110a190: 0000: c0012d00 00040206 0000043f 5886 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5887 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 } 58880110a19c: 0000: c0012d00 00040000 00000100 5889 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5890 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 } 58910110a1a8: 0000: c0012d00 00040001 0108a205 5892 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5893 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 5894 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 } 58950110a1b4: 0000: c0022d00 0004000e 80000000 01000100 5896 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5897 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 58980110a1c4: 0000: c0012d00 00040080 00000000 5899 write CP_SCRATCH_REG6 (057e) 5900 CP_SCRATCH_REG6: 107 5901 :0,0,107,98 59020110a1d0: 0000: 0000057e 0000006b 5903 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 5904 ibaddr:0110b000 5905 ibsize:000000b8 5906 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5907 set shader const 0078 59080110b000: 0000: c0042d00 00010078 0112d65b 00100000 0112d69b 00100000 5909 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5910 PA_SC_AA_MASK: 0xffff 59110110b018: 0000: c0012d00 00040312 0000ffff 5912 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5913 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 59140110b024: 0000: c0012d00 00040200 00000000 5915 opcode: CP_SET_CONSTANT (2d) (5 dwords) 5916 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5917 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5918 RB_ALPHA_REF: 0 59190110b030: 0000: c0032d00 0004010c 00000000 00000000 00000000 5920 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5921 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 5922 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 59230110b044: 0000: c0022d00 00040204 00000000 00090240 5924 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5925 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 5926 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 5927 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 5928 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 59290110b054: 0000: c0042d00 00040280 00080008 00080008 00000008 00000000 5930 opcode: CP_SET_CONSTANT (2d) (7 dwords) 5931 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 5932 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 5933 PA_CL_GB_VERT_DISC_ADJ: 1.000000 5934 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 5935 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 59360110b06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 5937 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5938 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 5939 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 59400110b088: 0000: c0022d00 00040081 00000000 01000100 5941 opcode: CP_SET_CONSTANT (2d) (8 dwords) 5942 PA_CL_VPORT_XSCALE: 128.000000 5943 PA_CL_VPORT_XOFFSET: 128.000000 5944 PA_CL_VPORT_YSCALE: -128.000000 5945 PA_CL_VPORT_YOFFSET: 128.000000 5946 PA_CL_VPORT_ZSCALE: 0.500000 5947 PA_CL_VPORT_ZOFFSET: 0.500000 59480110b098: 0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000 5949 opcode: CP_SET_CONSTANT (2d) (10 dwords) 59500110b0c0: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000 59510110b0b8: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000 59520110b0d8: 0020: 3f000000 00000000 5953 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 5954 vertex shader, start=0000, size=0015 5955 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 5956 03: 19481000 00262688 00000010 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0) 5957 04: 13480000 40252fc8 00000008 FETCH: VERTEX R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1) 5958 0000 0000 c200 ALLOC POSITION SIZE(0x0) 5959 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 5960 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 5961 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 5962 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 5963 06: 00038000 00000000 c2000000 ALU: MAXv export0.xy__ = R0, R0 5964 0000 0000 0000 NOP 59650110b0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 59660110b100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000 59670110b120: 0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000 5968 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 5969 fragment shader, start=0000, size=000c 5970 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 5971 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 5972 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 5973 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 5974 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 5975 0000 0000 0000 NOP 59760110b140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 59770110b160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 5978 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5979 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 59800110b17c: 0000: c0012d00 00040181 00000106 5981 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5982 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 59830110b188: 0000: c0012d00 00040180 10030002 5984 opcode: CP_SET_CONSTANT (2d) (6 dwords) 59850110b19c: 0.000000 0.000000 0.000000 0.000000 59860110b194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 5987 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5988 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 59890110b1ac: 0000: c0012d00 00040202 00001c20 5990 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5991 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 59920110b1b8: 0000: c0012d00 00040201 00000000 5993 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5994 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 59950110b1c4: 0000: c0012d00 00040104 0000000f 5996 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5997 RB_BLEND_RED: 0 5998 RB_BLEND_GREEN: 0 5999 RB_BLEND_BLUE: 0 6000 RB_BLEND_ALPHA: 0 60010110b1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 6002 opcode: CP_SET_CONSTANT (2d) (8 dwords) 6003 set texture const 0000 6004 clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap 6005 filter min/mag: point/point 6006 swizzle: xyzw 6007 addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE 6008 mipaddr=01240000 (flags=200) 60090110b1e8: 0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200 6010 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6011 VGT_INDX_OFFSET: 0 60120110b208: 0000: c0012d00 00040102 00000000 6013 write TC_CNTL_STATUS (0e00) 6014 TC_CNTL_STATUS: { L2_INVALIDATE } 60150110b214: 0000: 00000e00 00000001 6016 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 60170110b21c: 0000: c0035200 000005d0 00000000 00001000 00000001 6018 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 60190110b230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 6020 write CP_SCRATCH_REG7 (057f) 6021 CP_SCRATCH_REG7: 103 6022 :0,0,107,103 60230110b24c: 0000: 0000057f 00000067 6024 opcode: CP_NOP (10) (2 dwords) 60250110b254: 0000: c0001000 00000000 6026 opcode: CP_DRAW_INDX (22) (5 dwords) 6027 { VIZ_QUERY = 0 } 6028 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 } 6029 { NUM_INDICES = 18011832 } 6030 { INDX_BASE = 0xc } 6031 draw: 0 6032 prim_type: DI_PT_TRILIST (4) 6033 source_select: DI_SRC_SEL_DMA (0) 6034 num_indices: 18011832 6035 draw[17] register values 6036 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 6037 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 6038 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 6039!+ 0000006b CP_SCRATCH_REG6: 107 6040 :0,0,107,103 6041!+ 00000067 CP_SCRATCH_REG7: 103 6042 :0,0,107,103 6043 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 6044 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 6045 + 00000002 TP0_CHICKEN: 0x2 6046 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 6047!+ 00000100 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 } 6048!+ 0108a205 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 } 6049 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 6050!+ 01000100 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 } 6051 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 6052 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 6053!+ 01000100 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 6054 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 6055 + 00000000 VGT_MIN_VTX_INDX: 0 6056 + 00000000 VGT_INDX_OFFSET: 0 6057 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 6058 + 00000000 RB_BLEND_RED: 0 6059 + 00000000 RB_BLEND_GREEN: 0 6060 + 00000000 RB_BLEND_BLUE: 0 6061 + 00000000 RB_BLEND_ALPHA: 0 6062 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6063 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6064 + 00000000 RB_ALPHA_REF: 0 6065!+ 43000000 PA_CL_VPORT_XSCALE: 128.000000 6066!+ 43000000 PA_CL_VPORT_XOFFSET: 128.000000 6067!+ c3000000 PA_CL_VPORT_YSCALE: -128.000000 6068!+ 43000000 PA_CL_VPORT_YOFFSET: 128.000000 6069!+ 3f000000 PA_CL_VPORT_ZSCALE: 0.500000 6070!+ 3f000000 PA_CL_VPORT_ZOFFSET: 0.500000 6071 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 6072 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 6073 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 6074 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 6075 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 6076 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 6077 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 6078!+ 00001c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 6079 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 6080!+ 00090240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 6081 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 6082 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 6083 + 88888888 RB_SAMPLE_POS: 0x88888888 6084!+ 00080008 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 6085!+ 00080008 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 6086!+ 00000008 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 6087 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 6088 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 6089 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 6090 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 6091 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 6092 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 6093 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 6094 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 6095 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 6096 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 6097 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 6098 + 0000ffff PA_SC_AA_MASK: 0xffff 6099 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 6100 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 6101 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 6102 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 61030110b25c: 0000: c0032200 00000000 00060004 0112d6b8 0000000c 6104 write CP_SCRATCH_REG7 (057f) 6105NEEDS WFI: CP_SCRATCH_REG7 (57f) 6106 CP_SCRATCH_REG7: 104 6107 :0,0,107,104 61080110b270: 0000: 0000057f 00000068 6109 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 61100110b278: 0000: c0002600 00000000 6111 opcode: CP_EVENT_WRITE (46) (2 dwords) 6112 { EVENT = CACHE_FLUSH } 6113 event CACHE_FLUSH 61140110b280: 0000: c0004600 00000006 6115 opcode: CP_EVENT_WRITE (46) (2 dwords) 6116 { EVENT = CACHE_FLUSH } 6117 event CACHE_FLUSH 61180110b288: 0000: c0004600 00000006 6119 opcode: CP_EVENT_WRITE (46) (2 dwords) 6120 { EVENT = CACHE_FLUSH } 6121 event CACHE_FLUSH 61220110b290: 0000: c0004600 00000006 6123 opcode: CP_EVENT_WRITE (46) (2 dwords) 6124 { EVENT = CACHE_FLUSH } 6125 event CACHE_FLUSH 61260110b298: 0000: c0004600 00000006 6127 opcode: CP_EVENT_WRITE (46) (2 dwords) 6128 { EVENT = CACHE_FLUSH } 6129 event CACHE_FLUSH 61300110b2a0: 0000: c0004600 00000006 6131 opcode: CP_EVENT_WRITE (46) (2 dwords) 6132 { EVENT = CACHE_FLUSH } 6133 event CACHE_FLUSH 61340110b2a8: 0000: c0004600 00000006 6135 opcode: CP_EVENT_WRITE (46) (2 dwords) 6136 { EVENT = CACHE_FLUSH } 6137 event CACHE_FLUSH 61380110b2b0: 0000: c0004600 00000006 6139 opcode: CP_EVENT_WRITE (46) (2 dwords) 6140 { EVENT = CACHE_FLUSH } 6141 event CACHE_FLUSH 61420110b2b8: 0000: c0004600 00000006 6143 opcode: CP_EVENT_WRITE (46) (2 dwords) 6144 { EVENT = CACHE_FLUSH } 6145 event CACHE_FLUSH 61460110b2c0: 0000: c0004600 00000006 6147 opcode: CP_EVENT_WRITE (46) (2 dwords) 6148 { EVENT = CACHE_FLUSH } 6149 event CACHE_FLUSH 61500110b2c8: 0000: c0004600 00000006 6151 opcode: CP_EVENT_WRITE (46) (2 dwords) 6152 { EVENT = CACHE_FLUSH } 6153 event CACHE_FLUSH 61540110b2d0: 0000: c0004600 00000006 6155 opcode: CP_EVENT_WRITE (46) (2 dwords) 6156 { EVENT = CACHE_FLUSH } 6157 event CACHE_FLUSH 61580110b2d8: 0000: c0004600 00000006 61590110a1d8: 0000: c0013700 0110b000 000000b8 6160 nop 6161 write CP_SCRATCH_REG6 (057e) 6162 CP_SCRATCH_REG6: 108 6163 :0,0,108,104 61640110a1e8: 0000: 0000057e 0000006c 6165############################################################ 6166vertices: 0 6167cmd: deqp-gles2/185: fence=1264 6168############################################################ 6169cmdstream[14]: 124 dwords 6170 write RB_BC_CONTROL (0f01) 6171 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 61720122f000: 0000: 00000f01 1c004046 6173 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6174 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 61750122f008: 0000: c0012d00 00040293 00000020 6176 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6177 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 61780122f014: 0000: c0012d00 00040316 00000002 6179 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6180 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 61810122f020: 0000: c0012d00 00040317 00000002 6182 write CP_PERFMON_CNTL (0444) 6183 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 61840122f02c: 0000: 00000444 00000000 6185 write RBBM_PM_OVERRIDE1 (039c) 6186 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 6187 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 61880122f034: 0000: 0001039c ffffffff 00000fff 6189 write TP0_CHICKEN (0e1e) 6190 TP0_CHICKEN: 0x2 61910122f040: 0000: 00000e1e 00000002 6192 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 61930122f048: 0000: c0003b00 00007fff 6194 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6195 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 61960122f050: 0000: c0012d00 00040307 00100020 6197 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6198 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 61990122f05c: 0000: c0012d00 00040308 000e0120 6200 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6201 VGT_MAX_VTX_INDX: 0xffffffff 6202 VGT_MIN_VTX_INDX: 0 62030122f068: 0000: c0022d00 00040100 ffffffff 00000000 6204 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6205 VGT_INDX_OFFSET: 0 62060122f078: 0000: c0012d00 00040102 00000000 6207 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6208 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 62090122f084: 0000: c0012d00 00040181 00000004 6210 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6211 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 62120122f090: 0000: c0012d00 00040182 ffffffff 6213 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6214 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 62150122f09c: 0000: c0012d00 00040301 00000000 6216 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6217 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 62180122f0a8: 0000: c0012d00 00040300 00000000 6219 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6220 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 62210122f0b4: 0000: c0012d00 00040080 00000000 6222 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6223 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 62240122f0c0: 0000: c0012d00 00040208 00000004 6225 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6226 RB_SAMPLE_POS: 0x88888888 62270122f0cc: 0000: c0012d00 0004020a 88888888 6228 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6229 RB_COLOR_DEST_MASK: 0xffffffff 62300122f0d8: 0000: c0012d00 00040326 ffffffff 6231 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6232 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 62330122f0e4: 0000: c0012d00 0004031b 0003c000 6234 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6235 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 6236 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 62370122f0f0: 0000: c0022d00 00040183 00000000 00000000 6238 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 62390122f100: 0000: c0004b00 00000000 6240 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 62410122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001 6242 write SQ_INST_STORE_MANAGMENT (0d02) 6243 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 62440122f11c: 0000: 00000d02 00000180 6245 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 62460122f124: 0000: c0003b00 00000300 6247 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 62480122f12c: 0000: c0004a00 80000180 6249 opcode: CP_SET_CONSTANT (2d) (14 dwords) 62500122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 62510122f15c: 2.000000 0.750000 0.375000 0.250000 62520122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 62530122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 6254 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6255 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 62560122f16c: 0000: c0012d00 00040104 0000000f 6257 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6258 RB_BLEND_RED: 0 6259 RB_BLEND_GREEN: 0 6260 RB_BLEND_BLUE: 0 6261 RB_BLEND_ALPHA: 0xff 62620122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 6263 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6264 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 62650122f190: 0000: c0012d00 00040206 0000043f 6266 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6267 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 62680122f19c: 0000: c0012d00 00040000 00000020 6269 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6270 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 } 62710122f1a8: 0000: c0012d00 00040001 01266245 6272 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6273 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 6274 PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 } 62750122f1b4: 0000: c0022d00 0004000e 80000000 00200010 6276 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6277 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 62780122f1c4: 0000: c0012d00 00040080 00000000 6279 write CP_SCRATCH_REG6 (057e) 6280 CP_SCRATCH_REG6: 113 6281 :0,0,113,104 62820122f1d0: 0000: 0000057e 00000071 6283 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 6284 ibaddr:0122e000 6285 ibsize:000000b6 6286 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6287 set shader const 0078 62880122e000: 0000: c0042d00 00010078 0112d6c7 00100000 0112d6c7 00100000 6289 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6290 PA_SC_AA_MASK: 0xffff 62910122e018: 0000: c0012d00 00040312 0000ffff 6292 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6293 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 62940122e024: 0000: c0012d00 00040200 00000000 6295 opcode: CP_SET_CONSTANT (2d) (5 dwords) 6296 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6297 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6298 RB_ALPHA_REF: 0 62990122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 6300 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6301 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 6302 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 63030122e044: 0000: c0022d00 00040204 00000000 00090244 6304 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6305 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 6306 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 6307 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 6308 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 63090122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 6310 opcode: CP_SET_CONSTANT (2d) (7 dwords) 6311 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 6312 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 6313 PA_CL_GB_VERT_DISC_ADJ: 1.000000 6314 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 6315 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 63160122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 6317 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6318 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 6319 PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 } 63200122e088: 0000: c0022d00 00040081 00000000 00200010 6321 opcode: CP_SET_CONSTANT (2d) (8 dwords) 6322 PA_CL_VPORT_XSCALE: 8.000000 6323 PA_CL_VPORT_XOFFSET: 8.000000 6324 PA_CL_VPORT_YSCALE: 16.000000 6325 PA_CL_VPORT_YOFFSET: 16.000000 6326 PA_CL_VPORT_ZSCALE: 0.000000 6327 PA_CL_VPORT_ZOFFSET: 0.000000 63280122e098: 0000: c0062d00 0004010f 41000000 41000000 41800000 41800000 00000000 00000000 6329 opcode: CP_SET_CONSTANT (2d) (10 dwords) 63300122e0c0: 8.000000 16.000000 0.000000 0.000000 8.000000 16.000000 0.000000 0.000000 63310122e0b8: 0000: c0082d00 00000184 41000000 41800000 00000000 00000000 41000000 41800000 6332* 6333 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 6334 vertex shader, start=0000, size=0015 6335 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 6336 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 6337 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 6338 0000 0000 c200 ALLOC POSITION SIZE(0x0) 6339 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 6340 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 6341 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 6342 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 6343 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 6344 0000 0000 0000 NOP 63450122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 63460122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 63470122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 6348 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 6349 fragment shader, start=0000, size=000c 6350 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 6351 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 6352 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 6353 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 6354 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 6355 0000 0000 0000 NOP 63560122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 63570122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 6358 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6359 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 63600122e17c: 0000: c0012d00 00040181 00000106 6361 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6362 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 63630122e188: 0000: c0012d00 00040180 10030002 6364 opcode: CP_SET_CONSTANT (2d) (6 dwords) 63650122e19c: 0.000000 0.000000 0.000000 0.000000 63660122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 6367 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6368 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 63690122e1ac: 0000: c0012d00 00040202 00000c20 6370 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6371 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 63720122e1b8: 0000: c0012d00 00040201 00000000 6373 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6374 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 63750122e1c4: 0000: c0012d00 00040104 0000000f 6376 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6377 RB_BLEND_RED: 0 6378 RB_BLEND_GREEN: 0 6379 RB_BLEND_BLUE: 0 6380 RB_BLEND_ALPHA: 0 63810122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 6382 opcode: CP_SET_CONSTANT (2d) (8 dwords) 6383 set texture const 0000 6384 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 6385 filter min/mag: point/point 6386 swizzle: zyxw 6387 addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8 6388 mipaddr=00000000 (flags=200) 63890122e1e8: 0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200 6390 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6391 VGT_INDX_OFFSET: 0 63920122e208: 0000: c0012d00 00040102 00000000 6393 write TC_CNTL_STATUS (0e00) 6394 TC_CNTL_STATUS: { L2_INVALIDATE } 63950122e214: 0000: 00000e00 00000001 6396 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 63970122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 6398 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 63990122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 6400 write CP_SCRATCH_REG7 (057f) 6401 CP_SCRATCH_REG7: 109 6402 :0,0,113,109 64030122e24c: 0000: 0000057f 0000006d 6404 opcode: CP_NOP (10) (2 dwords) 64050122e254: 0000: c0001000 00000000 6406 opcode: CP_DRAW_INDX (22) (3 dwords) 6407 { VIZ_QUERY = 0 } 6408 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 6409 draw: 0 6410 prim_type: DI_PT_TRIFAN (5) 6411 source_select: DI_SRC_SEL_AUTO_INDEX (2) 6412 num_indices: 1407 6413 draw[18] register values 6414 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 6415 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 6416 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 6417!+ 00000071 CP_SCRATCH_REG6: 113 6418 :0,0,113,109 6419!+ 0000006d CP_SCRATCH_REG7: 109 6420 :0,0,113,109 6421 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 6422 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 6423 + 00000002 TP0_CHICKEN: 0x2 6424 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 6425!+ 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 6426!+ 01266245 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 } 6427 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 6428!+ 00200010 PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 } 6429 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 6430 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 6431!+ 00200010 PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 } 6432 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 6433 + 00000000 VGT_MIN_VTX_INDX: 0 6434 + 00000000 VGT_INDX_OFFSET: 0 6435 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 6436 + 00000000 RB_BLEND_RED: 0 6437 + 00000000 RB_BLEND_GREEN: 0 6438 + 00000000 RB_BLEND_BLUE: 0 6439 + 00000000 RB_BLEND_ALPHA: 0 6440 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6441 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6442 + 00000000 RB_ALPHA_REF: 0 6443!+ 41000000 PA_CL_VPORT_XSCALE: 8.000000 6444!+ 41000000 PA_CL_VPORT_XOFFSET: 8.000000 6445!+ 41800000 PA_CL_VPORT_YSCALE: 16.000000 6446!+ 41800000 PA_CL_VPORT_YOFFSET: 16.000000 6447!+ 00000000 PA_CL_VPORT_ZSCALE: 0.000000 6448!+ 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 6449 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 6450 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 6451 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 6452 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 6453 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 6454 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 6455 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 6456!+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 6457 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 6458!+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 6459 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 6460 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 6461 + 88888888 RB_SAMPLE_POS: 0x88888888 6462!+ 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 6463!+ 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 6464!+ 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 6465 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 6466 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 6467 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 6468 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 6469 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 6470 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 6471 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 6472 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 6473 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 6474 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 6475 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 6476 + 0000ffff PA_SC_AA_MASK: 0xffff 6477 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 6478 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 6479 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 6480 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 64810122e25c: 0000: c0012200 00000000 00040085 6482 write CP_SCRATCH_REG7 (057f) 6483NEEDS WFI: CP_SCRATCH_REG7 (57f) 6484 CP_SCRATCH_REG7: 110 6485 :0,0,113,110 64860122e268: 0000: 0000057f 0000006e 6487 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 64880122e270: 0000: c0002600 00000000 6489 opcode: CP_EVENT_WRITE (46) (2 dwords) 6490 { EVENT = CACHE_FLUSH } 6491 event CACHE_FLUSH 64920122e278: 0000: c0004600 00000006 6493 opcode: CP_EVENT_WRITE (46) (2 dwords) 6494 { EVENT = CACHE_FLUSH } 6495 event CACHE_FLUSH 64960122e280: 0000: c0004600 00000006 6497 opcode: CP_EVENT_WRITE (46) (2 dwords) 6498 { EVENT = CACHE_FLUSH } 6499 event CACHE_FLUSH 65000122e288: 0000: c0004600 00000006 6501 opcode: CP_EVENT_WRITE (46) (2 dwords) 6502 { EVENT = CACHE_FLUSH } 6503 event CACHE_FLUSH 65040122e290: 0000: c0004600 00000006 6505 opcode: CP_EVENT_WRITE (46) (2 dwords) 6506 { EVENT = CACHE_FLUSH } 6507 event CACHE_FLUSH 65080122e298: 0000: c0004600 00000006 6509 opcode: CP_EVENT_WRITE (46) (2 dwords) 6510 { EVENT = CACHE_FLUSH } 6511 event CACHE_FLUSH 65120122e2a0: 0000: c0004600 00000006 6513 opcode: CP_EVENT_WRITE (46) (2 dwords) 6514 { EVENT = CACHE_FLUSH } 6515 event CACHE_FLUSH 65160122e2a8: 0000: c0004600 00000006 6517 opcode: CP_EVENT_WRITE (46) (2 dwords) 6518 { EVENT = CACHE_FLUSH } 6519 event CACHE_FLUSH 65200122e2b0: 0000: c0004600 00000006 6521 opcode: CP_EVENT_WRITE (46) (2 dwords) 6522 { EVENT = CACHE_FLUSH } 6523 event CACHE_FLUSH 65240122e2b8: 0000: c0004600 00000006 6525 opcode: CP_EVENT_WRITE (46) (2 dwords) 6526 { EVENT = CACHE_FLUSH } 6527 event CACHE_FLUSH 65280122e2c0: 0000: c0004600 00000006 6529 opcode: CP_EVENT_WRITE (46) (2 dwords) 6530 { EVENT = CACHE_FLUSH } 6531 event CACHE_FLUSH 65320122e2c8: 0000: c0004600 00000006 6533 opcode: CP_EVENT_WRITE (46) (2 dwords) 6534 { EVENT = CACHE_FLUSH } 6535 event CACHE_FLUSH 65360122e2d0: 0000: c0004600 00000006 65370122f1d8: 0000: c0013700 0122e000 000000b6 6538 nop 6539 write CP_SCRATCH_REG6 (057e) 6540 CP_SCRATCH_REG6: 114 6541 :0,0,114,110 65420122f1e8: 0000: 0000057e 00000072 6543############################################################ 6544vertices: 0 6545cmd: deqp-gles2/185: fence=1265 6546############################################################ 6547cmdstream[15]: 124 dwords 6548 write RB_BC_CONTROL (0f01) 6549 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 65500110c000: 0000: 00000f01 1c004046 6551 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6552 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 65530110c008: 0000: c0012d00 00040293 00000020 6554 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6555 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 65560110c014: 0000: c0012d00 00040316 00000002 6557 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6558 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 65590110c020: 0000: c0012d00 00040317 00000002 6560 write CP_PERFMON_CNTL (0444) 6561 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 65620110c02c: 0000: 00000444 00000000 6563 write RBBM_PM_OVERRIDE1 (039c) 6564 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 6565 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 65660110c034: 0000: 0001039c ffffffff 00000fff 6567 write TP0_CHICKEN (0e1e) 6568 TP0_CHICKEN: 0x2 65690110c040: 0000: 00000e1e 00000002 6570 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 65710110c048: 0000: c0003b00 00007fff 6572 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6573 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 65740110c050: 0000: c0012d00 00040307 00100020 6575 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6576 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 65770110c05c: 0000: c0012d00 00040308 000e0120 6578 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6579 VGT_MAX_VTX_INDX: 0xffffffff 6580 VGT_MIN_VTX_INDX: 0 65810110c068: 0000: c0022d00 00040100 ffffffff 00000000 6582 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6583 VGT_INDX_OFFSET: 0 65840110c078: 0000: c0012d00 00040102 00000000 6585 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6586 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 65870110c084: 0000: c0012d00 00040181 00000004 6588 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6589 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 65900110c090: 0000: c0012d00 00040182 ffffffff 6591 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6592 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 65930110c09c: 0000: c0012d00 00040301 00000000 6594 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6595 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 65960110c0a8: 0000: c0012d00 00040300 00000000 6597 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6598 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 65990110c0b4: 0000: c0012d00 00040080 00000000 6600 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6601 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 66020110c0c0: 0000: c0012d00 00040208 00000004 6603 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6604 RB_SAMPLE_POS: 0x88888888 66050110c0cc: 0000: c0012d00 0004020a 88888888 6606 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6607 RB_COLOR_DEST_MASK: 0xffffffff 66080110c0d8: 0000: c0012d00 00040326 ffffffff 6609 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6610 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 66110110c0e4: 0000: c0012d00 0004031b 0003c000 6612 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6613 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 6614 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 66150110c0f0: 0000: c0022d00 00040183 00000000 00000000 6616 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 66170110c100: 0000: c0004b00 00000000 6618 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 66190110c108: 0000: c0035200 000005d0 00000000 5f601000 00000001 6620 write SQ_INST_STORE_MANAGMENT (0d02) 6621 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 66220110c11c: 0000: 00000d02 00000180 6623 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 66240110c124: 0000: c0003b00 00000300 6625 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 66260110c12c: 0000: c0004a00 80000180 6627 opcode: CP_SET_CONSTANT (2d) (14 dwords) 66280110c13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 66290110c15c: 2.000000 0.750000 0.375000 0.250000 66300110c134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 66310110c154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 6632 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6633 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 66340110c16c: 0000: c0012d00 00040104 0000000f 6635 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6636 RB_BLEND_RED: 0 6637 RB_BLEND_GREEN: 0 6638 RB_BLEND_BLUE: 0 6639 RB_BLEND_ALPHA: 0xff 66400110c178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 6641 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6642 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 66430110c190: 0000: c0012d00 00040206 0000043f 6644 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6645 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 } 66460110c19c: 0000: c0012d00 00040000 00000100 6647 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6648 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 } 66490110c1a8: 0000: c0012d00 00040001 0108a205 6650 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6651 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 6652 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 } 66530110c1b4: 0000: c0022d00 0004000e 80000000 01000100 6654 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6655 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 66560110c1c4: 0000: c0012d00 00040080 00000000 6657 write CP_SCRATCH_REG6 (057e) 6658 CP_SCRATCH_REG6: 119 6659 :0,0,119,110 66600110c1d0: 0000: 0000057e 00000077 6661 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 6662 ibaddr:0110b000 6663 ibsize:000000b8 6664 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6665 set shader const 0078 66660110b000: 0000: c0042d00 00010078 0112d747 00100000 0112d787 00100000 6667 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6668 PA_SC_AA_MASK: 0xffff 66690110b018: 0000: c0012d00 00040312 0000ffff 6670 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6671 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 66720110b024: 0000: c0012d00 00040200 00000000 6673 opcode: CP_SET_CONSTANT (2d) (5 dwords) 6674 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6675 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6676 RB_ALPHA_REF: 0 66770110b030: 0000: c0032d00 0004010c 00000000 00000000 00000000 6678 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6679 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 6680 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 66810110b044: 0000: c0022d00 00040204 00000000 00090240 6682 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6683 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 6684 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 6685 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 6686 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 66870110b054: 0000: c0042d00 00040280 00080008 00080008 00000008 00000000 6688 opcode: CP_SET_CONSTANT (2d) (7 dwords) 6689 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 6690 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 6691 PA_CL_GB_VERT_DISC_ADJ: 1.000000 6692 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 6693 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 66940110b06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 6695 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6696 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 6697 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 66980110b088: 0000: c0022d00 00040081 00000000 01000100 6699 opcode: CP_SET_CONSTANT (2d) (8 dwords) 6700 PA_CL_VPORT_XSCALE: 128.000000 6701 PA_CL_VPORT_XOFFSET: 128.000000 6702 PA_CL_VPORT_YSCALE: -128.000000 6703 PA_CL_VPORT_YOFFSET: 128.000000 6704 PA_CL_VPORT_ZSCALE: 0.500000 6705 PA_CL_VPORT_ZOFFSET: 0.500000 67060110b098: 0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000 6707 opcode: CP_SET_CONSTANT (2d) (10 dwords) 67080110b0c0: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000 67090110b0b8: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000 67100110b0d8: 0020: 3f000000 00000000 6711 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 6712 vertex shader, start=0000, size=0015 6713 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 6714 03: 19481000 00262688 00000010 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0) 6715 04: 13480000 40252fc8 00000008 FETCH: VERTEX R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1) 6716 0000 0000 c200 ALLOC POSITION SIZE(0x0) 6717 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 6718 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 6719 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 6720 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 6721 06: 00038000 00000000 c2000000 ALU: MAXv export0.xy__ = R0, R0 6722 0000 0000 0000 NOP 67230110b0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 67240110b100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000 67250110b120: 0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000 6726 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 6727 fragment shader, start=0000, size=000c 6728 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 6729 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 6730 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 6731 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 6732 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 6733 0000 0000 0000 NOP 67340110b140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 67350110b160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 6736 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6737 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 67380110b17c: 0000: c0012d00 00040181 00000106 6739 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6740 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 67410110b188: 0000: c0012d00 00040180 10030002 6742 opcode: CP_SET_CONSTANT (2d) (6 dwords) 67430110b19c: 0.000000 0.000000 0.000000 0.000000 67440110b194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 6745 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6746 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 67470110b1ac: 0000: c0012d00 00040202 00001c20 6748 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6749 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 67500110b1b8: 0000: c0012d00 00040201 00000000 6751 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6752 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 67530110b1c4: 0000: c0012d00 00040104 0000000f 6754 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6755 RB_BLEND_RED: 0 6756 RB_BLEND_GREEN: 0 6757 RB_BLEND_BLUE: 0 6758 RB_BLEND_ALPHA: 0 67590110b1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 6760 opcode: CP_SET_CONSTANT (2d) (8 dwords) 6761 set texture const 0000 6762 clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap 6763 filter min/mag: point/point 6764 swizzle: xyzw 6765 addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE 6766 mipaddr=01240000 (flags=200) 67670110b1e8: 0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200 6768 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6769 VGT_INDX_OFFSET: 0 67700110b208: 0000: c0012d00 00040102 00000000 6771 write TC_CNTL_STATUS (0e00) 6772 TC_CNTL_STATUS: { L2_INVALIDATE } 67730110b214: 0000: 00000e00 00000001 6774 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 67750110b21c: 0000: c0035200 000005d0 00000000 00001000 00000001 6776 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 67770110b230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 6778 write CP_SCRATCH_REG7 (057f) 6779 CP_SCRATCH_REG7: 115 6780 :0,0,119,115 67810110b24c: 0000: 0000057f 00000073 6782 opcode: CP_NOP (10) (2 dwords) 67830110b254: 0000: c0001000 00000000 6784 opcode: CP_DRAW_INDX (22) (5 dwords) 6785 { VIZ_QUERY = 0 } 6786 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 } 6787 { NUM_INDICES = 18012068 } 6788 { INDX_BASE = 0xc } 6789 draw: 0 6790 prim_type: DI_PT_TRILIST (4) 6791 source_select: DI_SRC_SEL_DMA (0) 6792 num_indices: 18012068 6793 draw[19] register values 6794 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 6795 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 6796 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 6797!+ 00000077 CP_SCRATCH_REG6: 119 6798 :0,0,119,115 6799!+ 00000073 CP_SCRATCH_REG7: 115 6800 :0,0,119,115 6801 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 6802 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 6803 + 00000002 TP0_CHICKEN: 0x2 6804 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 6805!+ 00000100 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 } 6806!+ 0108a205 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 } 6807 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 6808!+ 01000100 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 } 6809 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 6810 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 6811!+ 01000100 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 6812 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 6813 + 00000000 VGT_MIN_VTX_INDX: 0 6814 + 00000000 VGT_INDX_OFFSET: 0 6815 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 6816 + 00000000 RB_BLEND_RED: 0 6817 + 00000000 RB_BLEND_GREEN: 0 6818 + 00000000 RB_BLEND_BLUE: 0 6819 + 00000000 RB_BLEND_ALPHA: 0 6820 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6821 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6822 + 00000000 RB_ALPHA_REF: 0 6823!+ 43000000 PA_CL_VPORT_XSCALE: 128.000000 6824!+ 43000000 PA_CL_VPORT_XOFFSET: 128.000000 6825!+ c3000000 PA_CL_VPORT_YSCALE: -128.000000 6826!+ 43000000 PA_CL_VPORT_YOFFSET: 128.000000 6827!+ 3f000000 PA_CL_VPORT_ZSCALE: 0.500000 6828!+ 3f000000 PA_CL_VPORT_ZOFFSET: 0.500000 6829 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 6830 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 6831 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 6832 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 6833 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 6834 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 6835 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 6836!+ 00001c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 6837 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 6838!+ 00090240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 6839 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 6840 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 6841 + 88888888 RB_SAMPLE_POS: 0x88888888 6842!+ 00080008 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 6843!+ 00080008 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 6844!+ 00000008 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 6845 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 6846 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 6847 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 6848 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 6849 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 6850 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 6851 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 6852 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 6853 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 6854 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 6855 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 6856 + 0000ffff PA_SC_AA_MASK: 0xffff 6857 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 6858 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 6859 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 6860 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 68610110b25c: 0000: c0032200 00000000 00060004 0112d7a4 0000000c 6862 write CP_SCRATCH_REG7 (057f) 6863NEEDS WFI: CP_SCRATCH_REG7 (57f) 6864 CP_SCRATCH_REG7: 116 6865 :0,0,119,116 68660110b270: 0000: 0000057f 00000074 6867 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 68680110b278: 0000: c0002600 00000000 6869 opcode: CP_EVENT_WRITE (46) (2 dwords) 6870 { EVENT = CACHE_FLUSH } 6871 event CACHE_FLUSH 68720110b280: 0000: c0004600 00000006 6873 opcode: CP_EVENT_WRITE (46) (2 dwords) 6874 { EVENT = CACHE_FLUSH } 6875 event CACHE_FLUSH 68760110b288: 0000: c0004600 00000006 6877 opcode: CP_EVENT_WRITE (46) (2 dwords) 6878 { EVENT = CACHE_FLUSH } 6879 event CACHE_FLUSH 68800110b290: 0000: c0004600 00000006 6881 opcode: CP_EVENT_WRITE (46) (2 dwords) 6882 { EVENT = CACHE_FLUSH } 6883 event CACHE_FLUSH 68840110b298: 0000: c0004600 00000006 6885 opcode: CP_EVENT_WRITE (46) (2 dwords) 6886 { EVENT = CACHE_FLUSH } 6887 event CACHE_FLUSH 68880110b2a0: 0000: c0004600 00000006 6889 opcode: CP_EVENT_WRITE (46) (2 dwords) 6890 { EVENT = CACHE_FLUSH } 6891 event CACHE_FLUSH 68920110b2a8: 0000: c0004600 00000006 6893 opcode: CP_EVENT_WRITE (46) (2 dwords) 6894 { EVENT = CACHE_FLUSH } 6895 event CACHE_FLUSH 68960110b2b0: 0000: c0004600 00000006 6897 opcode: CP_EVENT_WRITE (46) (2 dwords) 6898 { EVENT = CACHE_FLUSH } 6899 event CACHE_FLUSH 69000110b2b8: 0000: c0004600 00000006 6901 opcode: CP_EVENT_WRITE (46) (2 dwords) 6902 { EVENT = CACHE_FLUSH } 6903 event CACHE_FLUSH 69040110b2c0: 0000: c0004600 00000006 6905 opcode: CP_EVENT_WRITE (46) (2 dwords) 6906 { EVENT = CACHE_FLUSH } 6907 event CACHE_FLUSH 69080110b2c8: 0000: c0004600 00000006 6909 opcode: CP_EVENT_WRITE (46) (2 dwords) 6910 { EVENT = CACHE_FLUSH } 6911 event CACHE_FLUSH 69120110b2d0: 0000: c0004600 00000006 6913 opcode: CP_EVENT_WRITE (46) (2 dwords) 6914 { EVENT = CACHE_FLUSH } 6915 event CACHE_FLUSH 69160110b2d8: 0000: c0004600 00000006 69170110c1d8: 0000: c0013700 0110b000 000000b8 6918 nop 6919 write CP_SCRATCH_REG6 (057e) 6920 CP_SCRATCH_REG6: 120 6921 :0,0,120,116 69220110c1e8: 0000: 0000057e 00000078 6923############################################################ 6924vertices: 0 6925cmd: deqp-gles2/185: fence=1266 6926############################################################ 6927cmdstream[16]: 124 dwords 6928 write RB_BC_CONTROL (0f01) 6929 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 69300122d000: 0000: 00000f01 1c004046 6931 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6932 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 69330122d008: 0000: c0012d00 00040293 00000020 6934 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6935 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 69360122d014: 0000: c0012d00 00040316 00000002 6937 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6938 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 69390122d020: 0000: c0012d00 00040317 00000002 6940 write CP_PERFMON_CNTL (0444) 6941 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 69420122d02c: 0000: 00000444 00000000 6943 write RBBM_PM_OVERRIDE1 (039c) 6944 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 6945 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 69460122d034: 0000: 0001039c ffffffff 00000fff 6947 write TP0_CHICKEN (0e1e) 6948 TP0_CHICKEN: 0x2 69490122d040: 0000: 00000e1e 00000002 6950 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 69510122d048: 0000: c0003b00 00007fff 6952 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6953 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 69540122d050: 0000: c0012d00 00040307 00100020 6955 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6956 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 69570122d05c: 0000: c0012d00 00040308 000e0120 6958 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6959 VGT_MAX_VTX_INDX: 0xffffffff 6960 VGT_MIN_VTX_INDX: 0 69610122d068: 0000: c0022d00 00040100 ffffffff 00000000 6962 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6963 VGT_INDX_OFFSET: 0 69640122d078: 0000: c0012d00 00040102 00000000 6965 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6966 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 69670122d084: 0000: c0012d00 00040181 00000004 6968 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6969 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 69700122d090: 0000: c0012d00 00040182 ffffffff 6971 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6972 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 69730122d09c: 0000: c0012d00 00040301 00000000 6974 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6975 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 69760122d0a8: 0000: c0012d00 00040300 00000000 6977 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6978 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 69790122d0b4: 0000: c0012d00 00040080 00000000 6980 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6981 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 69820122d0c0: 0000: c0012d00 00040208 00000004 6983 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6984 RB_SAMPLE_POS: 0x88888888 69850122d0cc: 0000: c0012d00 0004020a 88888888 6986 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6987 RB_COLOR_DEST_MASK: 0xffffffff 69880122d0d8: 0000: c0012d00 00040326 ffffffff 6989 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6990 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 69910122d0e4: 0000: c0012d00 0004031b 0003c000 6992 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6993 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 6994 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 69950122d0f0: 0000: c0022d00 00040183 00000000 00000000 6996 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 69970122d100: 0000: c0004b00 00000000 6998 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 69990122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001 7000 write SQ_INST_STORE_MANAGMENT (0d02) 7001 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 70020122d11c: 0000: 00000d02 00000180 7003 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 70040122d124: 0000: c0003b00 00000300 7005 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 70060122d12c: 0000: c0004a00 80000180 7007 opcode: CP_SET_CONSTANT (2d) (14 dwords) 70080122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 70090122d15c: 2.000000 0.750000 0.375000 0.250000 70100122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 70110122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 7012 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7013 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 70140122d16c: 0000: c0012d00 00040104 0000000f 7015 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7016 RB_BLEND_RED: 0 7017 RB_BLEND_GREEN: 0 7018 RB_BLEND_BLUE: 0 7019 RB_BLEND_ALPHA: 0xff 70200122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 7021 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7022 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 70230122d190: 0000: c0012d00 00040206 0000043f 7024 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7025 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 70260122d19c: 0000: c0012d00 00040000 00000020 7027 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7028 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 } 70290122d1a8: 0000: c0012d00 00040001 01266245 7030 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7031 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 7032 PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 } 70330122d1b4: 0000: c0022d00 0004000e 80000000 00100008 7034 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7035 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 70360122d1c4: 0000: c0012d00 00040080 00000000 7037 write CP_SCRATCH_REG6 (057e) 7038 CP_SCRATCH_REG6: 125 7039 :0,0,125,116 70400122d1d0: 0000: 0000057e 0000007d 7041 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 7042 ibaddr:0122e000 7043 ibsize:000000b6 7044 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7045 set shader const 0078 70460122e000: 0000: c0042d00 00010078 0112d7b3 00100000 0112d7b3 00100000 7047 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7048 PA_SC_AA_MASK: 0xffff 70490122e018: 0000: c0012d00 00040312 0000ffff 7050 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7051 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 70520122e024: 0000: c0012d00 00040200 00000000 7053 opcode: CP_SET_CONSTANT (2d) (5 dwords) 7054 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7055 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7056 RB_ALPHA_REF: 0 70570122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 7058 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7059 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 7060 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 70610122e044: 0000: c0022d00 00040204 00000000 00090244 7062 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7063 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 7064 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 7065 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 7066 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 70670122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 7068 opcode: CP_SET_CONSTANT (2d) (7 dwords) 7069 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 7070 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 7071 PA_CL_GB_VERT_DISC_ADJ: 1.000000 7072 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 7073 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 70740122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 7075 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7076 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 7077 PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 } 70780122e088: 0000: c0022d00 00040081 00000000 00100008 7079 opcode: CP_SET_CONSTANT (2d) (8 dwords) 7080 PA_CL_VPORT_XSCALE: 4.000000 7081 PA_CL_VPORT_XOFFSET: 4.000000 7082 PA_CL_VPORT_YSCALE: 8.000000 7083 PA_CL_VPORT_YOFFSET: 8.000000 7084 PA_CL_VPORT_ZSCALE: 0.000000 7085 PA_CL_VPORT_ZOFFSET: 0.000000 70860122e098: 0000: c0062d00 0004010f 40800000 40800000 41000000 41000000 00000000 00000000 7087 opcode: CP_SET_CONSTANT (2d) (10 dwords) 70880122e0c0: 4.000000 8.000000 0.000000 0.000000 4.000000 8.000000 0.000000 0.000000 70890122e0b8: 0000: c0082d00 00000184 40800000 41000000 00000000 00000000 40800000 41000000 7090* 7091 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 7092 vertex shader, start=0000, size=0015 7093 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 7094 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 7095 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 7096 0000 0000 c200 ALLOC POSITION SIZE(0x0) 7097 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 7098 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 7099 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 7100 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 7101 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 7102 0000 0000 0000 NOP 71030122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 71040122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 71050122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 7106 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 7107 fragment shader, start=0000, size=000c 7108 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 7109 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 7110 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 7111 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 7112 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 7113 0000 0000 0000 NOP 71140122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 71150122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 7116 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7117 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 71180122e17c: 0000: c0012d00 00040181 00000106 7119 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7120 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 71210122e188: 0000: c0012d00 00040180 10030002 7122 opcode: CP_SET_CONSTANT (2d) (6 dwords) 71230122e19c: 0.000000 0.000000 0.000000 0.000000 71240122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 7125 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7126 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 71270122e1ac: 0000: c0012d00 00040202 00000c20 7128 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7129 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 71300122e1b8: 0000: c0012d00 00040201 00000000 7131 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7132 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 71330122e1c4: 0000: c0012d00 00040104 0000000f 7134 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7135 RB_BLEND_RED: 0 7136 RB_BLEND_GREEN: 0 7137 RB_BLEND_BLUE: 0 7138 RB_BLEND_ALPHA: 0 71390122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 7140 opcode: CP_SET_CONSTANT (2d) (8 dwords) 7141 set texture const 0000 7142 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 7143 filter min/mag: point/point 7144 swizzle: zyxw 7145 addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8 7146 mipaddr=00000000 (flags=200) 71470122e1e8: 0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200 7148 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7149 VGT_INDX_OFFSET: 0 71500122e208: 0000: c0012d00 00040102 00000000 7151 write TC_CNTL_STATUS (0e00) 7152 TC_CNTL_STATUS: { L2_INVALIDATE } 71530122e214: 0000: 00000e00 00000001 7154 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 71550122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 7156 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 71570122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 7158 write CP_SCRATCH_REG7 (057f) 7159 CP_SCRATCH_REG7: 121 7160 :0,0,125,121 71610122e24c: 0000: 0000057f 00000079 7162 opcode: CP_NOP (10) (2 dwords) 71630122e254: 0000: c0001000 00000000 7164 opcode: CP_DRAW_INDX (22) (3 dwords) 7165 { VIZ_QUERY = 0 } 7166 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 7167 draw: 0 7168 prim_type: DI_PT_TRIFAN (5) 7169 source_select: DI_SRC_SEL_AUTO_INDEX (2) 7170 num_indices: 1407 7171 draw[20] register values 7172 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 7173 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 7174 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 7175!+ 0000007d CP_SCRATCH_REG6: 125 7176 :0,0,125,121 7177!+ 00000079 CP_SCRATCH_REG7: 121 7178 :0,0,125,121 7179 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 7180 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 7181 + 00000002 TP0_CHICKEN: 0x2 7182 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 7183!+ 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 7184!+ 01266245 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 } 7185 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 7186!+ 00100008 PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 } 7187 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 7188 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 7189!+ 00100008 PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 } 7190 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 7191 + 00000000 VGT_MIN_VTX_INDX: 0 7192 + 00000000 VGT_INDX_OFFSET: 0 7193 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 7194 + 00000000 RB_BLEND_RED: 0 7195 + 00000000 RB_BLEND_GREEN: 0 7196 + 00000000 RB_BLEND_BLUE: 0 7197 + 00000000 RB_BLEND_ALPHA: 0 7198 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7199 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7200 + 00000000 RB_ALPHA_REF: 0 7201!+ 40800000 PA_CL_VPORT_XSCALE: 4.000000 7202!+ 40800000 PA_CL_VPORT_XOFFSET: 4.000000 7203!+ 41000000 PA_CL_VPORT_YSCALE: 8.000000 7204!+ 41000000 PA_CL_VPORT_YOFFSET: 8.000000 7205!+ 00000000 PA_CL_VPORT_ZSCALE: 0.000000 7206!+ 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 7207 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 7208 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 7209 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 7210 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 7211 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 7212 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 7213 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 7214!+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 7215 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 7216!+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 7217 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 7218 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 7219 + 88888888 RB_SAMPLE_POS: 0x88888888 7220!+ 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 7221!+ 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 7222!+ 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 7223 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 7224 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 7225 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 7226 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 7227 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 7228 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 7229 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 7230 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 7231 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 7232 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 7233 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 7234 + 0000ffff PA_SC_AA_MASK: 0xffff 7235 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 7236 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 7237 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 7238 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 72390122e25c: 0000: c0012200 00000000 00040085 7240 write CP_SCRATCH_REG7 (057f) 7241NEEDS WFI: CP_SCRATCH_REG7 (57f) 7242 CP_SCRATCH_REG7: 122 7243 :0,0,125,122 72440122e268: 0000: 0000057f 0000007a 7245 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 72460122e270: 0000: c0002600 00000000 7247 opcode: CP_EVENT_WRITE (46) (2 dwords) 7248 { EVENT = CACHE_FLUSH } 7249 event CACHE_FLUSH 72500122e278: 0000: c0004600 00000006 7251 opcode: CP_EVENT_WRITE (46) (2 dwords) 7252 { EVENT = CACHE_FLUSH } 7253 event CACHE_FLUSH 72540122e280: 0000: c0004600 00000006 7255 opcode: CP_EVENT_WRITE (46) (2 dwords) 7256 { EVENT = CACHE_FLUSH } 7257 event CACHE_FLUSH 72580122e288: 0000: c0004600 00000006 7259 opcode: CP_EVENT_WRITE (46) (2 dwords) 7260 { EVENT = CACHE_FLUSH } 7261 event CACHE_FLUSH 72620122e290: 0000: c0004600 00000006 7263 opcode: CP_EVENT_WRITE (46) (2 dwords) 7264 { EVENT = CACHE_FLUSH } 7265 event CACHE_FLUSH 72660122e298: 0000: c0004600 00000006 7267 opcode: CP_EVENT_WRITE (46) (2 dwords) 7268 { EVENT = CACHE_FLUSH } 7269 event CACHE_FLUSH 72700122e2a0: 0000: c0004600 00000006 7271 opcode: CP_EVENT_WRITE (46) (2 dwords) 7272 { EVENT = CACHE_FLUSH } 7273 event CACHE_FLUSH 72740122e2a8: 0000: c0004600 00000006 7275 opcode: CP_EVENT_WRITE (46) (2 dwords) 7276 { EVENT = CACHE_FLUSH } 7277 event CACHE_FLUSH 72780122e2b0: 0000: c0004600 00000006 7279 opcode: CP_EVENT_WRITE (46) (2 dwords) 7280 { EVENT = CACHE_FLUSH } 7281 event CACHE_FLUSH 72820122e2b8: 0000: c0004600 00000006 7283 opcode: CP_EVENT_WRITE (46) (2 dwords) 7284 { EVENT = CACHE_FLUSH } 7285 event CACHE_FLUSH 72860122e2c0: 0000: c0004600 00000006 7287 opcode: CP_EVENT_WRITE (46) (2 dwords) 7288 { EVENT = CACHE_FLUSH } 7289 event CACHE_FLUSH 72900122e2c8: 0000: c0004600 00000006 7291 opcode: CP_EVENT_WRITE (46) (2 dwords) 7292 { EVENT = CACHE_FLUSH } 7293 event CACHE_FLUSH 72940122e2d0: 0000: c0004600 00000006 72950122d1d8: 0000: c0013700 0122e000 000000b6 7296 nop 7297 write CP_SCRATCH_REG6 (057e) 7298 CP_SCRATCH_REG6: 126 7299 :0,0,126,122 73000122d1e8: 0000: 0000057e 0000007e 7301############################################################ 7302vertices: 0 7303cmd: deqp-gles2/185: fence=1267 7304############################################################ 7305cmdstream[17]: 124 dwords 7306 write RB_BC_CONTROL (0f01) 7307 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 73080110a000: 0000: 00000f01 1c004046 7309 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7310 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 73110110a008: 0000: c0012d00 00040293 00000020 7312 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7313 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 73140110a014: 0000: c0012d00 00040316 00000002 7315 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7316 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 73170110a020: 0000: c0012d00 00040317 00000002 7318 write CP_PERFMON_CNTL (0444) 7319 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 73200110a02c: 0000: 00000444 00000000 7321 write RBBM_PM_OVERRIDE1 (039c) 7322 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 7323 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 73240110a034: 0000: 0001039c ffffffff 00000fff 7325 write TP0_CHICKEN (0e1e) 7326 TP0_CHICKEN: 0x2 73270110a040: 0000: 00000e1e 00000002 7328 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 73290110a048: 0000: c0003b00 00007fff 7330 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7331 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 73320110a050: 0000: c0012d00 00040307 00100020 7333 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7334 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 73350110a05c: 0000: c0012d00 00040308 000e0120 7336 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7337 VGT_MAX_VTX_INDX: 0xffffffff 7338 VGT_MIN_VTX_INDX: 0 73390110a068: 0000: c0022d00 00040100 ffffffff 00000000 7340 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7341 VGT_INDX_OFFSET: 0 73420110a078: 0000: c0012d00 00040102 00000000 7343 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7344 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 73450110a084: 0000: c0012d00 00040181 00000004 7346 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7347 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 73480110a090: 0000: c0012d00 00040182 ffffffff 7349 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7350 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 73510110a09c: 0000: c0012d00 00040301 00000000 7352 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7353 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 73540110a0a8: 0000: c0012d00 00040300 00000000 7355 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7356 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 73570110a0b4: 0000: c0012d00 00040080 00000000 7358 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7359 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 73600110a0c0: 0000: c0012d00 00040208 00000004 7361 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7362 RB_SAMPLE_POS: 0x88888888 73630110a0cc: 0000: c0012d00 0004020a 88888888 7364 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7365 RB_COLOR_DEST_MASK: 0xffffffff 73660110a0d8: 0000: c0012d00 00040326 ffffffff 7367 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7368 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 73690110a0e4: 0000: c0012d00 0004031b 0003c000 7370 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7371 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 7372 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 73730110a0f0: 0000: c0022d00 00040183 00000000 00000000 7374 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 73750110a100: 0000: c0004b00 00000000 7376 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 73770110a108: 0000: c0035200 000005d0 00000000 5f601000 00000001 7378 write SQ_INST_STORE_MANAGMENT (0d02) 7379 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 73800110a11c: 0000: 00000d02 00000180 7381 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 73820110a124: 0000: c0003b00 00000300 7383 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 73840110a12c: 0000: c0004a00 80000180 7385 opcode: CP_SET_CONSTANT (2d) (14 dwords) 73860110a13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 73870110a15c: 2.000000 0.750000 0.375000 0.250000 73880110a134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 73890110a154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 7390 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7391 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 73920110a16c: 0000: c0012d00 00040104 0000000f 7393 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7394 RB_BLEND_RED: 0 7395 RB_BLEND_GREEN: 0 7396 RB_BLEND_BLUE: 0 7397 RB_BLEND_ALPHA: 0xff 73980110a178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 7399 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7400 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 74010110a190: 0000: c0012d00 00040206 0000043f 7402 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7403 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 } 74040110a19c: 0000: c0012d00 00040000 00000100 7405 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7406 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 } 74070110a1a8: 0000: c0012d00 00040001 0108a205 7408 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7409 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 7410 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 } 74110110a1b4: 0000: c0022d00 0004000e 80000000 01000100 7412 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7413 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 74140110a1c4: 0000: c0012d00 00040080 00000000 7415 write CP_SCRATCH_REG6 (057e) 7416 CP_SCRATCH_REG6: 131 7417 :0,0,131,122 74180110a1d0: 0000: 0000057e 00000083 7419 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 7420 ibaddr:0110b000 7421 ibsize:000000b8 7422 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7423 set shader const 0078 74240110b000: 0000: c0042d00 00010078 0112d833 00100000 0112d873 00100000 7425 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7426 PA_SC_AA_MASK: 0xffff 74270110b018: 0000: c0012d00 00040312 0000ffff 7428 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7429 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 74300110b024: 0000: c0012d00 00040200 00000000 7431 opcode: CP_SET_CONSTANT (2d) (5 dwords) 7432 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7433 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7434 RB_ALPHA_REF: 0 74350110b030: 0000: c0032d00 0004010c 00000000 00000000 00000000 7436 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7437 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 7438 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 74390110b044: 0000: c0022d00 00040204 00000000 00090240 7440 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7441 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 7442 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 7443 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 7444 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 74450110b054: 0000: c0042d00 00040280 00080008 00080008 00000008 00000000 7446 opcode: CP_SET_CONSTANT (2d) (7 dwords) 7447 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 7448 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 7449 PA_CL_GB_VERT_DISC_ADJ: 1.000000 7450 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 7451 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 74520110b06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 7453 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7454 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 7455 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 74560110b088: 0000: c0022d00 00040081 00000000 01000100 7457 opcode: CP_SET_CONSTANT (2d) (8 dwords) 7458 PA_CL_VPORT_XSCALE: 128.000000 7459 PA_CL_VPORT_XOFFSET: 128.000000 7460 PA_CL_VPORT_YSCALE: -128.000000 7461 PA_CL_VPORT_YOFFSET: 128.000000 7462 PA_CL_VPORT_ZSCALE: 0.500000 7463 PA_CL_VPORT_ZOFFSET: 0.500000 74640110b098: 0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000 7465 opcode: CP_SET_CONSTANT (2d) (10 dwords) 74660110b0c0: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000 74670110b0b8: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000 74680110b0d8: 0020: 3f000000 00000000 7469 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 7470 vertex shader, start=0000, size=0015 7471 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 7472 03: 19481000 00262688 00000010 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0) 7473 04: 13480000 40252fc8 00000008 FETCH: VERTEX R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1) 7474 0000 0000 c200 ALLOC POSITION SIZE(0x0) 7475 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 7476 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 7477 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 7478 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 7479 06: 00038000 00000000 c2000000 ALU: MAXv export0.xy__ = R0, R0 7480 0000 0000 0000 NOP 74810110b0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 74820110b100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000 74830110b120: 0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000 7484 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 7485 fragment shader, start=0000, size=000c 7486 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 7487 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 7488 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 7489 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 7490 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 7491 0000 0000 0000 NOP 74920110b140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 74930110b160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 7494 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7495 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 74960110b17c: 0000: c0012d00 00040181 00000106 7497 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7498 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 74990110b188: 0000: c0012d00 00040180 10030002 7500 opcode: CP_SET_CONSTANT (2d) (6 dwords) 75010110b19c: 0.000000 0.000000 0.000000 0.000000 75020110b194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 7503 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7504 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 75050110b1ac: 0000: c0012d00 00040202 00001c20 7506 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7507 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 75080110b1b8: 0000: c0012d00 00040201 00000000 7509 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7510 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 75110110b1c4: 0000: c0012d00 00040104 0000000f 7512 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7513 RB_BLEND_RED: 0 7514 RB_BLEND_GREEN: 0 7515 RB_BLEND_BLUE: 0 7516 RB_BLEND_ALPHA: 0 75170110b1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 7518 opcode: CP_SET_CONSTANT (2d) (8 dwords) 7519 set texture const 0000 7520 clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap 7521 filter min/mag: point/point 7522 swizzle: xyzw 7523 addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE 7524 mipaddr=01240000 (flags=200) 75250110b1e8: 0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200 7526 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7527 VGT_INDX_OFFSET: 0 75280110b208: 0000: c0012d00 00040102 00000000 7529 write TC_CNTL_STATUS (0e00) 7530 TC_CNTL_STATUS: { L2_INVALIDATE } 75310110b214: 0000: 00000e00 00000001 7532 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 75330110b21c: 0000: c0035200 000005d0 00000000 00001000 00000001 7534 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 75350110b230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 7536 write CP_SCRATCH_REG7 (057f) 7537 CP_SCRATCH_REG7: 127 7538 :0,0,131,127 75390110b24c: 0000: 0000057f 0000007f 7540 opcode: CP_NOP (10) (2 dwords) 75410110b254: 0000: c0001000 00000000 7542 opcode: CP_DRAW_INDX (22) (5 dwords) 7543 { VIZ_QUERY = 0 } 7544 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 } 7545 { NUM_INDICES = 18012304 } 7546 { INDX_BASE = 0xc } 7547 draw: 0 7548 prim_type: DI_PT_TRILIST (4) 7549 source_select: DI_SRC_SEL_DMA (0) 7550 num_indices: 18012304 7551 draw[21] register values 7552 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 7553 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 7554 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 7555!+ 00000083 CP_SCRATCH_REG6: 131 7556 :0,0,131,127 7557!+ 0000007f CP_SCRATCH_REG7: 127 7558 :0,0,131,127 7559 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 7560 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 7561 + 00000002 TP0_CHICKEN: 0x2 7562 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 7563!+ 00000100 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 } 7564!+ 0108a205 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 } 7565 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 7566!+ 01000100 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 } 7567 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 7568 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 7569!+ 01000100 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 7570 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 7571 + 00000000 VGT_MIN_VTX_INDX: 0 7572 + 00000000 VGT_INDX_OFFSET: 0 7573 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 7574 + 00000000 RB_BLEND_RED: 0 7575 + 00000000 RB_BLEND_GREEN: 0 7576 + 00000000 RB_BLEND_BLUE: 0 7577 + 00000000 RB_BLEND_ALPHA: 0 7578 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7579 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7580 + 00000000 RB_ALPHA_REF: 0 7581!+ 43000000 PA_CL_VPORT_XSCALE: 128.000000 7582!+ 43000000 PA_CL_VPORT_XOFFSET: 128.000000 7583!+ c3000000 PA_CL_VPORT_YSCALE: -128.000000 7584!+ 43000000 PA_CL_VPORT_YOFFSET: 128.000000 7585!+ 3f000000 PA_CL_VPORT_ZSCALE: 0.500000 7586!+ 3f000000 PA_CL_VPORT_ZOFFSET: 0.500000 7587 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 7588 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 7589 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 7590 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 7591 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 7592 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 7593 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 7594!+ 00001c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 7595 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 7596!+ 00090240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 7597 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 7598 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 7599 + 88888888 RB_SAMPLE_POS: 0x88888888 7600!+ 00080008 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 7601!+ 00080008 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 7602!+ 00000008 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 7603 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 7604 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 7605 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 7606 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 7607 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 7608 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 7609 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 7610 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 7611 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 7612 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 7613 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 7614 + 0000ffff PA_SC_AA_MASK: 0xffff 7615 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 7616 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 7617 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 7618 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 76190110b25c: 0000: c0032200 00000000 00060004 0112d890 0000000c 7620 write CP_SCRATCH_REG7 (057f) 7621NEEDS WFI: CP_SCRATCH_REG7 (57f) 7622 CP_SCRATCH_REG7: 128 7623 :0,0,131,128 76240110b270: 0000: 0000057f 00000080 7625 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 76260110b278: 0000: c0002600 00000000 7627 opcode: CP_EVENT_WRITE (46) (2 dwords) 7628 { EVENT = CACHE_FLUSH } 7629 event CACHE_FLUSH 76300110b280: 0000: c0004600 00000006 7631 opcode: CP_EVENT_WRITE (46) (2 dwords) 7632 { EVENT = CACHE_FLUSH } 7633 event CACHE_FLUSH 76340110b288: 0000: c0004600 00000006 7635 opcode: CP_EVENT_WRITE (46) (2 dwords) 7636 { EVENT = CACHE_FLUSH } 7637 event CACHE_FLUSH 76380110b290: 0000: c0004600 00000006 7639 opcode: CP_EVENT_WRITE (46) (2 dwords) 7640 { EVENT = CACHE_FLUSH } 7641 event CACHE_FLUSH 76420110b298: 0000: c0004600 00000006 7643 opcode: CP_EVENT_WRITE (46) (2 dwords) 7644 { EVENT = CACHE_FLUSH } 7645 event CACHE_FLUSH 76460110b2a0: 0000: c0004600 00000006 7647 opcode: CP_EVENT_WRITE (46) (2 dwords) 7648 { EVENT = CACHE_FLUSH } 7649 event CACHE_FLUSH 76500110b2a8: 0000: c0004600 00000006 7651 opcode: CP_EVENT_WRITE (46) (2 dwords) 7652 { EVENT = CACHE_FLUSH } 7653 event CACHE_FLUSH 76540110b2b0: 0000: c0004600 00000006 7655 opcode: CP_EVENT_WRITE (46) (2 dwords) 7656 { EVENT = CACHE_FLUSH } 7657 event CACHE_FLUSH 76580110b2b8: 0000: c0004600 00000006 7659 opcode: CP_EVENT_WRITE (46) (2 dwords) 7660 { EVENT = CACHE_FLUSH } 7661 event CACHE_FLUSH 76620110b2c0: 0000: c0004600 00000006 7663 opcode: CP_EVENT_WRITE (46) (2 dwords) 7664 { EVENT = CACHE_FLUSH } 7665 event CACHE_FLUSH 76660110b2c8: 0000: c0004600 00000006 7667 opcode: CP_EVENT_WRITE (46) (2 dwords) 7668 { EVENT = CACHE_FLUSH } 7669 event CACHE_FLUSH 76700110b2d0: 0000: c0004600 00000006 7671 opcode: CP_EVENT_WRITE (46) (2 dwords) 7672 { EVENT = CACHE_FLUSH } 7673 event CACHE_FLUSH 76740110b2d8: 0000: c0004600 00000006 76750110a1d8: 0000: c0013700 0110b000 000000b8 7676 nop 7677 write CP_SCRATCH_REG6 (057e) 7678 CP_SCRATCH_REG6: 132 7679 :0,0,132,128 76800110a1e8: 0000: 0000057e 00000084 7681############################################################ 7682vertices: 0 7683cmd: deqp-gles2/185: fence=1268 7684############################################################ 7685cmdstream[18]: 124 dwords 7686 write RB_BC_CONTROL (0f01) 7687 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 76880122f000: 0000: 00000f01 1c004046 7689 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7690 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 76910122f008: 0000: c0012d00 00040293 00000020 7692 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7693 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 76940122f014: 0000: c0012d00 00040316 00000002 7695 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7696 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 76970122f020: 0000: c0012d00 00040317 00000002 7698 write CP_PERFMON_CNTL (0444) 7699 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 77000122f02c: 0000: 00000444 00000000 7701 write RBBM_PM_OVERRIDE1 (039c) 7702 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 7703 RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 77040122f034: 0000: 0001039c ffffffff 00000fff 7705 write TP0_CHICKEN (0e1e) 7706 TP0_CHICKEN: 0x2 77070122f040: 0000: 00000e1e 00000002 7708 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 77090122f048: 0000: c0003b00 00007fff 7710 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7711 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 77120122f050: 0000: c0012d00 00040307 00100020 7713 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7714 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 77150122f05c: 0000: c0012d00 00040308 000e0120 7716 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7717 VGT_MAX_VTX_INDX: 0xffffffff 7718 VGT_MIN_VTX_INDX: 0 77190122f068: 0000: c0022d00 00040100 ffffffff 00000000 7720 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7721 VGT_INDX_OFFSET: 0 77220122f078: 0000: c0012d00 00040102 00000000 7723 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7724 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 77250122f084: 0000: c0012d00 00040181 00000004 7726 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7727 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 77280122f090: 0000: c0012d00 00040182 ffffffff 7729 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7730 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 77310122f09c: 0000: c0012d00 00040301 00000000 7732 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7733 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 77340122f0a8: 0000: c0012d00 00040300 00000000 7735 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7736 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 77370122f0b4: 0000: c0012d00 00040080 00000000 7738 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7739 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 77400122f0c0: 0000: c0012d00 00040208 00000004 7741 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7742 RB_SAMPLE_POS: 0x88888888 77430122f0cc: 0000: c0012d00 0004020a 88888888 7744 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7745 RB_COLOR_DEST_MASK: 0xffffffff 77460122f0d8: 0000: c0012d00 00040326 ffffffff 7747 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7748 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 77490122f0e4: 0000: c0012d00 0004031b 0003c000 7750 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7751 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 7752 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 77530122f0f0: 0000: c0022d00 00040183 00000000 00000000 7754 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 77550122f100: 0000: c0004b00 00000000 7756 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 77570122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001 7758 write SQ_INST_STORE_MANAGMENT (0d02) 7759 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 77600122f11c: 0000: 00000d02 00000180 7761 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 77620122f124: 0000: c0003b00 00000300 7763 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 77640122f12c: 0000: c0004a00 80000180 7765 opcode: CP_SET_CONSTANT (2d) (14 dwords) 77660122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 77670122f15c: 2.000000 0.750000 0.375000 0.250000 77680122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 77690122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 7770 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7771 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 77720122f16c: 0000: c0012d00 00040104 0000000f 7773 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7774 RB_BLEND_RED: 0 7775 RB_BLEND_GREEN: 0 7776 RB_BLEND_BLUE: 0 7777 RB_BLEND_ALPHA: 0xff 77780122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 7779 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7780 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 77810122f190: 0000: c0012d00 00040206 0000043f 7782 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7783 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 77840122f19c: 0000: c0012d00 00040000 00000020 7785 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7786 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 } 77870122f1a8: 0000: c0012d00 00040001 01266245 7788 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7789 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 7790 PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 } 77910122f1b4: 0000: c0022d00 0004000e 80000000 00080004 7792 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7793 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 77940122f1c4: 0000: c0012d00 00040080 00000000 7795 write CP_SCRATCH_REG6 (057e) 7796 CP_SCRATCH_REG6: 137 7797 :0,0,137,128 77980122f1d0: 0000: 0000057e 00000089 7799 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 7800 ibaddr:0122e000 7801 ibsize:000000b6 7802 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7803 set shader const 0078 78040122e000: 0000: c0042d00 00010078 0112d89f 00100000 0112d89f 00100000 7805 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7806 PA_SC_AA_MASK: 0xffff 78070122e018: 0000: c0012d00 00040312 0000ffff 7808 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7809 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 78100122e024: 0000: c0012d00 00040200 00000000 7811 opcode: CP_SET_CONSTANT (2d) (5 dwords) 7812 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7813 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7814 RB_ALPHA_REF: 0 78150122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 7816 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7817 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 7818 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 78190122e044: 0000: c0022d00 00040204 00000000 00090244 7820 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7821 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 7822 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 7823 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 7824 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 78250122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 7826 opcode: CP_SET_CONSTANT (2d) (7 dwords) 7827 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 7828 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 7829 PA_CL_GB_VERT_DISC_ADJ: 1.000000 7830 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 7831 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 78320122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 7833 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7834 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 7835 PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 } 78360122e088: 0000: c0022d00 00040081 00000000 00080004 7837 opcode: CP_SET_CONSTANT (2d) (8 dwords) 7838 PA_CL_VPORT_XSCALE: 2.000000 7839 PA_CL_VPORT_XOFFSET: 2.000000 7840 PA_CL_VPORT_YSCALE: 4.000000 7841 PA_CL_VPORT_YOFFSET: 4.000000 7842 PA_CL_VPORT_ZSCALE: 0.000000 7843 PA_CL_VPORT_ZOFFSET: 0.000000 78440122e098: 0000: c0062d00 0004010f 40000000 40000000 40800000 40800000 00000000 00000000 7845 opcode: CP_SET_CONSTANT (2d) (10 dwords) 78460122e0c0: 2.000000 4.000000 0.000000 0.000000 2.000000 4.000000 0.000000 0.000000 78470122e0b8: 0000: c0082d00 00000184 40000000 40800000 00000000 00000000 40000000 40800000 7848* 7849 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 7850 vertex shader, start=0000, size=0015 7851 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 7852 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 7853 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 7854 0000 0000 c200 ALLOC POSITION SIZE(0x0) 7855 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 7856 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 7857 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 7858 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 7859 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 7860 0000 0000 0000 NOP 78610122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 78620122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 78630122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 7864 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 7865 fragment shader, start=0000, size=000c 7866 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 7867 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 7868 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 7869 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 7870 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 7871 0000 0000 0000 NOP 78720122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 78730122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 7874 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7875 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 78760122e17c: 0000: c0012d00 00040181 00000106 7877 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7878 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 78790122e188: 0000: c0012d00 00040180 10030002 7880 opcode: CP_SET_CONSTANT (2d) (6 dwords) 78810122e19c: 0.000000 0.000000 0.000000 0.000000 78820122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 7883 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7884 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 78850122e1ac: 0000: c0012d00 00040202 00000c20 7886 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7887 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 78880122e1b8: 0000: c0012d00 00040201 00000000 7889 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7890 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 78910122e1c4: 0000: c0012d00 00040104 0000000f 7892 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7893 RB_BLEND_RED: 0 7894 RB_BLEND_GREEN: 0 7895 RB_BLEND_BLUE: 0 7896 RB_BLEND_ALPHA: 0 78970122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 7898 opcode: CP_SET_CONSTANT (2d) (8 dwords) 7899 set texture const 0000 7900 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 7901 filter min/mag: point/point 7902 swizzle: zyxw 7903 addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8 7904 mipaddr=00000000 (flags=200) 79050122e1e8: 0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200 7906 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7907 VGT_INDX_OFFSET: 0 79080122e208: 0000: c0012d00 00040102 00000000 7909 write TC_CNTL_STATUS (0e00) 7910 TC_CNTL_STATUS: { L2_INVALIDATE } 79110122e214: 0000: 00000e00 00000001 7912 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 79130122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 7914 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 79150122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 7916 write CP_SCRATCH_REG7 (057f) 7917 CP_SCRATCH_REG7: 133 7918 :0,0,137,133 79190122e24c: 0000: 0000057f 00000085 7920 opcode: CP_NOP (10) (2 dwords) 79210122e254: 0000: c0001000 00000000 7922 opcode: CP_DRAW_INDX (22) (3 dwords) 7923 { VIZ_QUERY = 0 } 7924 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 7925 draw: 0 7926 prim_type: DI_PT_TRIFAN (5) 7927 source_select: DI_SRC_SEL_AUTO_INDEX (2) 7928 num_indices: 1407 7929 draw[22] register values 7930 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 7931 + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 7932 + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } 7933!+ 00000089 CP_SCRATCH_REG6: 137 7934 :0,0,137,133 7935!+ 00000085 CP_SCRATCH_REG7: 133 7936 :0,0,137,133 7937 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 7938 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 7939 + 00000002 TP0_CHICKEN: 0x2 7940 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 7941!+ 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 7942!+ 01266245 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 } 7943 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 7944!+ 00080004 PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 } 7945 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 7946 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 7947!+ 00080004 PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 } 7948 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 7949 + 00000000 VGT_MIN_VTX_INDX: 0 7950 + 00000000 VGT_INDX_OFFSET: 0 7951 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 7952 + 00000000 RB_BLEND_RED: 0 7953 + 00000000 RB_BLEND_GREEN: 0 7954 + 00000000 RB_BLEND_BLUE: 0 7955 + 00000000 RB_BLEND_ALPHA: 0 7956 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7957 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7958 + 00000000 RB_ALPHA_REF: 0 7959!+ 40000000 PA_CL_VPORT_XSCALE: 2.000000 7960!+ 40000000 PA_CL_VPORT_XOFFSET: 2.000000 7961!+ 40800000 PA_CL_VPORT_YSCALE: 4.000000 7962!+ 40800000 PA_CL_VPORT_YOFFSET: 4.000000 7963!+ 00000000 PA_CL_VPORT_ZSCALE: 0.000000 7964!+ 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 7965 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 7966 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 7967 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 7968 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 7969 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 7970 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 7971 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 7972!+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 7973 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 7974!+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 7975 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 7976 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 7977 + 88888888 RB_SAMPLE_POS: 0x88888888 7978!+ 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 7979!+ 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 7980!+ 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 7981 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 7982 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 7983 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 7984 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 7985 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 7986 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 7987 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 7988 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 7989 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 7990 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 7991 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 7992 + 0000ffff PA_SC_AA_MASK: 0xffff 7993 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 7994 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 7995 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 7996 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 79970122e25c: 0000: c0012200 00000000 00040085 7998 write CP_SCRATCH_REG7 (057f) 7999NEEDS WFI: CP_SCRATCH_REG7 (57f) 8000 CP_SCRATCH_REG7: 134 8001 :0,0,137,134 80020122e268: 0000: 0000057f 00000086 8003 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 80040122e270: 0000: c0002600 00000000 8005 opcode: CP_EVENT_WRITE (46) (2 dwords) 8006 { EVENT = CACHE_FLUSH } 8007 event CACHE_FLUSH 80080122e278: 0000: c0004600 00000006 8009 opcode: CP_EVENT_WRITE (46) (2 dwords) 8010 { EVENT = CACHE_FLUSH } 8011 event CACHE_FLUSH 80120122e280: 0000: c0004600 00000006 8013 opcode: CP_EVENT_WRITE (46) (2 dwords) 8014 { EVENT = CACHE_FLUSH } 8015 event CACHE_FLUSH 80160122e288: 0000: c0004600 00000006 8017 opcode: CP_EVENT_WRITE (46) (2 dwords) 8018 { EVENT = CACHE_FLUSH } 8019 event CACHE_FLUSH 80200122e290: 0000: c0004600 00000006 8021 opcode: CP_EVENT_WRITE (46) (2 dwords) 8022 { EVENT = CACHE_FLUSH } 8023 event CACHE_FLUSH 80240122e298: 0000: c0004600 00000006 8025 opcode: CP_EVENT_WRITE (46) (2 dwords) 8026 { EVENT = CACHE_FLUSH } 8027 event CACHE_FLUSH 80280122e2a0: 0000: c0004600 00000006 8029 opcode: CP_EVENT_WRITE (46) (2 dwords) 8030 { EVENT = CACHE_FLUSH } 8031 event CACHE_FLUSH 80320122e2a8: 0000: c0004600 00000006 8033 opcode: CP_EVENT_WRITE (46) (2 dwords) 8034 { EVENT = CACHE_FLUSH } 8035 event CACHE_FLUSH 80360122e2b0: 0000: c0004600 00000006 8037 opcode: CP_EVENT_WRITE (46) (2 dwords) 8038 { EVENT = CACHE_FLUSH } 8039 event CACHE_FLUSH 80400122e2b8: 0000: c0004600 00000006 8041 opcode: CP_EVENT_WRITE (46) (2 dwords) 8042 { EVENT = CACHE_FLUSH } 8043 event CACHE_FLUSH 80440122e2c0: 0000: c0004600 00000006 8045 opcode: CP_EVENT_WRITE (46) (2 dwords) 8046 { EVENT = CACHE_FLUSH } 8047 event CACHE_FLUSH 80480122e2c8: 0000: c0004600 00000006 8049 opcode: CP_EVENT_WRITE (46) (2 dwords) 8050 { EVENT = CACHE_FLUSH } 8051 event CACHE_FLUSH 80520122e2d0: 0000: c0004600 00000006 80530122f1d8: 0000: c0013700 0122e000 000000b6 8054 nop 8055 write CP_SCRATCH_REG6 (057e) 8056 CP_SCRATCH_REG6: 138 8057 :0,0,138,134 80580122f1e8: 0000: 0000057e 0000008a 8059############################################################ 8060vertices: 0 8061