1 /*
2 * Copyright © 2015 Rob Clark <robclark@freedesktop.org>
3 * SPDX-License-Identifier: MIT
4 *
5 * Authors:
6 * Rob Clark <robclark@freedesktop.org>
7 */
8
9 #ifndef IR3_NIR_H_
10 #define IR3_NIR_H_
11
12 #include "compiler/nir/nir.h"
13 #include "compiler/nir/nir_builder.h"
14 #include "compiler/shader_enums.h"
15
16 #include "ir3_shader.h"
17
18 BEGINC;
19
20 bool ir3_nir_apply_trig_workarounds(nir_shader *shader);
21 bool ir3_nir_lower_imul(nir_shader *shader);
22 bool ir3_nir_lower_io_offsets(nir_shader *shader);
23 bool ir3_nir_lower_load_barycentric_at_sample(nir_shader *shader);
24 bool ir3_nir_lower_load_barycentric_at_offset(nir_shader *shader);
25 bool ir3_nir_lower_push_consts_to_preamble(nir_shader *nir,
26 struct ir3_shader_variant *v);
27 bool ir3_nir_lower_driver_params_to_ubo(nir_shader *nir,
28 struct ir3_shader_variant *v);
29 bool ir3_nir_move_varying_inputs(nir_shader *shader);
30 int ir3_nir_coord_offset(nir_def *ssa);
31 bool ir3_nir_lower_tex_prefetch(nir_shader *shader);
32 bool ir3_nir_lower_layer_id(nir_shader *shader);
33 bool ir3_nir_lower_frag_shading_rate(nir_shader *shader);
34 bool ir3_nir_lower_primitive_shading_rate(nir_shader *shader);
35
36 void ir3_nir_lower_to_explicit_output(nir_shader *shader,
37 struct ir3_shader_variant *v,
38 unsigned topology);
39 void ir3_nir_lower_to_explicit_input(nir_shader *shader,
40 struct ir3_shader_variant *v);
41 void ir3_nir_lower_tess_ctrl(nir_shader *shader, struct ir3_shader_variant *v,
42 unsigned topology);
43 void ir3_nir_lower_tess_eval(nir_shader *shader, struct ir3_shader_variant *v,
44 unsigned topology);
45 void ir3_nir_lower_gs(nir_shader *shader);
46
47 bool ir3_supports_vectorized_nir_op(nir_op op);
48 uint8_t ir3_nir_vectorize_filter(const nir_instr *instr, const void *data);
49
50 /*
51 * 64b related lowering:
52 */
53 bool ir3_nir_lower_64b_intrinsics(nir_shader *shader);
54 bool ir3_nir_lower_64b_undef(nir_shader *shader);
55 bool ir3_nir_lower_64b_global(nir_shader *shader);
56 bool ir3_nir_lower_64b_regs(nir_shader *shader);
57
58 nir_mem_access_size_align ir3_mem_access_size_align(
59 nir_intrinsic_op intrin, uint8_t bytes, uint8_t bit_size, uint32_t align,
60 uint32_t align_offset, bool offset_is_const, enum gl_access_qualifier access,
61 const void *cb_data);
62
63 bool ir3_nir_opt_branch_and_or_not(nir_shader *nir);
64 bool ir3_nir_opt_triops_bitwise(nir_shader *nir);
65 bool ir3_optimize_loop(struct ir3_compiler *compiler,
66 const struct ir3_shader_nir_options *options,
67 nir_shader *s);
68 void ir3_nir_lower_io_to_temporaries(nir_shader *s);
69 void ir3_finalize_nir(struct ir3_compiler *compiler,
70 const struct ir3_shader_nir_options *options,
71 nir_shader *s);
72 void ir3_nir_post_finalize(struct ir3_shader *shader);
73 void ir3_nir_lower_variant(struct ir3_shader_variant *so,
74 const struct ir3_shader_nir_options *options,
75 nir_shader *s);
76
77 void ir3_setup_const_state(nir_shader *nir, struct ir3_shader_variant *v,
78 struct ir3_const_state *const_state);
79 uint32_t ir3_const_state_get_free_space(const struct ir3_shader_variant *v,
80 const struct ir3_const_state *const_state,
81 uint32_t align_vec4);
82 void ir3_const_alloc(struct ir3_const_allocations *const_alloc,
83 enum ir3_const_alloc_type type, uint32_t size_vec4,
84 uint32_t align_vec4);
85 void ir3_const_reserve_space(struct ir3_const_allocations *const_alloc,
86 enum ir3_const_alloc_type type,
87 uint32_t size_vec4, uint32_t align_vec4);
88 void ir3_const_free_reserved_space(struct ir3_const_allocations *const_alloc,
89 enum ir3_const_alloc_type type);
90 void ir3_const_alloc_all_reserved_space(struct ir3_const_allocations *const_alloc);
91
92 uint32_t ir3_nir_scan_driver_consts(struct ir3_compiler *compiler,
93 nir_shader *shader,
94 struct ir3_const_image_dims *image_dims);
95 void ir3_alloc_driver_params(struct ir3_const_allocations *const_alloc,
96 uint32_t *num_driver_params,
97 struct ir3_compiler *compiler,
98 enum pipe_shader_type shader_type);
99 bool ir3_nir_lower_load_constant(nir_shader *nir, struct ir3_shader_variant *v);
100 void ir3_nir_analyze_ubo_ranges(nir_shader *nir, struct ir3_shader_variant *v);
101 bool ir3_nir_lower_ubo_loads(nir_shader *nir, struct ir3_shader_variant *v);
102 bool ir3_nir_lower_const_global_loads(nir_shader *nir, struct ir3_shader_variant *v);
103 bool ir3_nir_fixup_load_const_ir3(nir_shader *nir);
104 bool ir3_nir_opt_preamble(nir_shader *nir, struct ir3_shader_variant *v);
105 bool ir3_nir_opt_prefetch_descriptors(nir_shader *nir, struct ir3_shader_variant *v);
106 bool ir3_nir_lower_preamble(nir_shader *nir, struct ir3_shader_variant *v);
107
108 nir_def *ir3_nir_try_propagate_bit_shift(nir_builder *b,
109 nir_def *offset,
110 int32_t shift);
111
112 bool ir3_nir_lower_subgroups_filter(const nir_instr *instr, const void *data);
113 bool ir3_nir_lower_shuffle(nir_shader *nir, struct ir3_shader *shader);
114 bool ir3_nir_opt_subgroups(nir_shader *nir, struct ir3_shader_variant *v);
115
116 nir_def *ir3_get_shared_driver_ubo(nir_builder *b,
117 const struct ir3_driver_ubo *ubo);
118 nir_def *ir3_get_driver_ubo(nir_builder *b, struct ir3_driver_ubo *ubo);
119 nir_def *ir3_get_driver_consts_ubo(nir_builder *b,
120 struct ir3_shader_variant *v);
121 void ir3_update_driver_ubo(nir_shader *nir, const struct ir3_driver_ubo *ubo, const char *name);
122 nir_def *ir3_load_shared_driver_ubo(nir_builder *b, unsigned components,
123 const struct ir3_driver_ubo *ubo,
124 unsigned offset);
125 nir_def *ir3_load_driver_ubo(nir_builder *b, unsigned components,
126 struct ir3_driver_ubo *ubo,
127 unsigned offset);
128 nir_def *ir3_load_driver_ubo_indirect(nir_builder *b, unsigned components,
129 struct ir3_driver_ubo *ubo,
130 unsigned base, nir_def *offset,
131 unsigned range);
132
133 bool ir3_def_is_rematerializable_for_preamble(nir_def *def,
134 nir_def **preamble_defs);
135
136 nir_def *ir3_rematerialize_def_for_preamble(nir_builder *b, nir_def *def,
137 struct set *instr_set,
138 nir_def **preamble_defs);
139
140 struct driver_param_info {
141 uint32_t offset;
142 };
143
144 bool ir3_get_driver_param_info(const nir_shader *shader,
145 nir_intrinsic_instr *intr,
146 struct driver_param_info *param_info);
147
148 static inline nir_intrinsic_instr *
ir3_bindless_resource(nir_src src)149 ir3_bindless_resource(nir_src src)
150 {
151 if (src.ssa->parent_instr->type != nir_instr_type_intrinsic)
152 return NULL;
153
154 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(src.ssa->parent_instr);
155 if (intrin->intrinsic != nir_intrinsic_bindless_resource_ir3)
156 return NULL;
157
158 return intrin;
159 }
160
161 static inline bool
is_intrinsic_store(nir_intrinsic_op op)162 is_intrinsic_store(nir_intrinsic_op op)
163 {
164 switch (op) {
165 case nir_intrinsic_store_output:
166 case nir_intrinsic_store_per_view_output:
167 case nir_intrinsic_store_scratch:
168 case nir_intrinsic_store_ssbo:
169 case nir_intrinsic_store_shared:
170 case nir_intrinsic_store_global:
171 case nir_intrinsic_store_global_ir3:
172 return true;
173 default:
174 return false;
175 }
176 }
177
178 static inline bool
is_intrinsic_load(nir_intrinsic_op op)179 is_intrinsic_load(nir_intrinsic_op op)
180 {
181 switch (op) {
182 case nir_intrinsic_load_input:
183 case nir_intrinsic_load_scratch:
184 case nir_intrinsic_load_ssbo:
185 case nir_intrinsic_load_ubo:
186 case nir_intrinsic_load_shared:
187 case nir_intrinsic_load_global:
188 case nir_intrinsic_load_global_ir3:
189 case nir_intrinsic_load_const_ir3:
190 return true;
191 default:
192 return false;
193 }
194 }
195
196 uint32_t ir3_nir_max_imm_offset(nir_intrinsic_instr *intrin, const void *data);
197
198 ENDC;
199
200 #endif /* IR3_NIR_H_ */
201