1<?xml version="1.0" encoding="UTF-8"?> 2<!-- 3Copyright © 2020 Google, Inc. 4 5Permission is hereby granted, free of charge, to any person obtaining a 6copy of this software and associated documentation files (the "Software"), 7to deal in the Software without restriction, including without limitation 8the rights to use, copy, modify, merge, publish, distribute, sublicense, 9and/or sell copies of the Software, and to permit persons to whom the 10Software is furnished to do so, subject to the following conditions: 11 12The above copyright notice and this permission notice (including the next 13paragraph) shall be included in all copies or substantial portions of the 14Software. 15 16THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22SOFTWARE. 23 --> 24 25<isa> 26 27<!-- 28 Cat0 Instructions: 29 --> 30 31<bitset name="#instruction-cat0" extends="#instruction"> 32 <!-- 33 TODO immed size is 16b for a3xx, 20b for a4xx, 32b for a5xx+.. should we 34 try to express this? Also, not all cat0 take an immed, so maybe push 35 this further down the hierarchy? 36 --> 37 <field name="IMMED" low="0" high="31" type="branch"/> 38 39 <field name="REPEAT" low="40" high="42" type="#rptN"/> 40 <pattern pos="43">x</pattern> 41 <field name="SS" pos="44" type="bool" display="(ss)"/> 42 <field name="EQ" pos="48" type="bool" display="(eq)"/> 43 <field name="JP" pos="59" type="bool" display="(jp)"/> 44 <field name="SY" pos="60" type="bool" display="(sy)"/> 45 <pattern low="61" high="63">000</pattern> <!-- cat0 --> 46 <encode> 47 <map name="IMMED">src->cat0.immed</map> 48 <map name="COMP1">reg_comp(src->srcs[0])</map> 49 <map name="COMP2">reg_comp(src->srcs[1])</map> 50 <map name="INV1">src->cat0.inv1</map> 51 <map name="INV2">src->cat0.inv2</map> 52 <map name="EQ">!!(src->flags & IR3_INSTR_EQ)</map> 53 </encode> 54</bitset> 55 56 57<bitset name="#instruction-cat0-0src" extends="#instruction-cat0"> 58 <display> 59 {SY}{SS}{EQ}{JP}{REPEAT}{NAME} 60 </display> 61 <pattern low="32" high="36">xxxxx</pattern> 62 <pattern low="37" high="39">000</pattern> <!-- BRTYPE --> 63 <pattern low="45" high="47">000</pattern> <!-- src1 --> 64 <pattern low="52" high="54">000</pattern> <!-- src0 --> 65</bitset> 66 67<bitset name="nop" extends="#instruction-cat0-0src"> 68 <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 69 <pattern low="55" high="58">0000</pattern> <!-- OPC --> 70</bitset> 71 72<bitset name="end" extends="#instruction-cat0-0src"> 73 <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 74 <pattern low="55" high="58">0110</pattern> <!-- OPC --> 75</bitset> 76 77<bitset name="ret" extends="#instruction-cat0-0src"> 78 <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 79 <pattern low="55" high="58">0100</pattern> <!-- OPC --> 80</bitset> 81 82<bitset name="emit" extends="#instruction-cat0-0src"> 83 <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 84 <pattern low="55" high="58">0111</pattern> <!-- OPC --> 85</bitset> 86 87<bitset name="cut" extends="#instruction-cat0-0src"> 88 <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 89 <pattern low="55" high="58">1000</pattern> <!-- OPC --> 90</bitset> 91 92<bitset name="chmask" extends="#instruction-cat0-0src"> 93 <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 94 <pattern low="55" high="58">1001</pattern> <!-- OPC --> 95</bitset> 96 97<bitset name="chsh" extends="#instruction-cat0-0src"> 98 <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 99 <pattern low="55" high="58">1010</pattern> <!-- OPC --> 100</bitset> 101 102<bitset name="flow_rev" extends="#instruction-cat0-0src"> 103 <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 104 <pattern low="55" high="58">1011</pattern> <!-- OPC --> 105</bitset> 106 107<bitset name="shpe" extends="#instruction-cat0-0src"> 108 <doc>SHader Prologue End</doc> 109 <pattern low="49" high="51">xx1</pattern> <!-- OPC_HI --> 110 <pattern low="55" high="58">1000</pattern> <!-- OPC --> 111</bitset> 112 113<bitset name="predt" extends="#instruction-cat0-0src"> 114 <doc> 115 The predt, predf, and prede instructions are used to enable 116 "predicated execution" for a region of code. During predicated 117 execution, the execution mask is combined with the "predication 118 mask" to determine the active fibers. So this is similar to 119 branching with the exception that inactive fibers keep executing 120 instead of being parked; the instructions they execute simply 121 have no effect. Since no branch stack is necessary to support 122 predication, it is more performant for divergent branches. 123 124 More concretely, the hardware seems to keep track of a 125 predication mask and a predication mode. The mode can be "none" 126 (no predication, the default, and set by prede), "true" (set by 127 predt), or "false" (set by predf). The final execution mask is 128 determined by and'ing with ~0 (none mode), the predication mask 129 (true mode), or its negation (false mode). 130 131 Predication is enabled by predt or predf which take the value of 132 p0.x of all fibers (not only the active ones) and store them in 133 the predication mask. Then the mode is set to true or false. 134 Executing prede disables predication by setting the mode to 135 none. 136 137 One peculiarity, and the reason the execution mode state is 138 necessary, is that any instruction marked with (jp) will also 139 update the execution mask. The current mode will be kept in that 140 case. 141 </doc> 142 <pattern low="49" high="51">xx1</pattern> <!-- OPC_HI --> 143 <pattern low="55" high="58">1101</pattern> <!-- OPC --> 144</bitset> 145 146<bitset name="predf" extends="#instruction-cat0-0src"> 147 <pattern low="49" high="51">xx1</pattern> <!-- OPC_HI --> 148 <pattern low="55" high="58">1110</pattern> <!-- OPC --> 149</bitset> 150 151<bitset name="prede" extends="#instruction-cat0-0src"> 152 <pattern low="49" high="51">xx1</pattern> <!-- OPC_HI --> 153 <pattern low="55" high="58">1111</pattern> <!-- OPC --> 154</bitset> 155 156 157<bitset name="#instruction-cat0-1src" extends="#instruction-cat0"> 158 <display> 159 {SY}{SS}{EQ}{JP}{NAME} {INV1}p0.{COMP1} 160 </display> 161 <pattern low="32" high="36">00000</pattern> 162 <pattern low="37" high="39">000</pattern> <!-- BRTYPE --> 163 <pattern low="45" high="47">000</pattern> <!-- src1 --> 164 <field name="INV1" pos="52" type="bool" display="!"> 165 <doc>Invert source condition</doc> 166 </field> 167 <field name="COMP1" low="53" high="54" type="#swiz"> 168 <doc>Predicate register (p0.c) component for source</doc> 169 </field> 170</bitset> 171 172<bitset name="kill" extends="#instruction-cat0-1src"> 173 <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 174 <pattern low="55" high="58">0101</pattern> <!-- OPC --> 175</bitset> 176 177 178<bitset name="#instruction-cat0-immed" extends="#instruction-cat0"> 179 <display> 180 {SY}{SS}{JP}{NAME} #{IMMED} 181 </display> 182 <pattern low="32" high="36">xxxxx</pattern> <!-- INDEX --> 183 <pattern low="37" high="39">xxx</pattern> <!-- BRTYPE --> 184 <pattern low="45" high="47">xxx</pattern> <!-- src1 --> 185 <pattern low="52" high="54">xxx</pattern> <!-- src0 --> 186</bitset> 187 188<bitset name="jump" extends="#instruction-cat0-immed"> 189 <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 190 <pattern low="55" high="58">0010</pattern> <!-- OPC --> 191</bitset> 192 193<bitset name="call" extends="#instruction-cat0-immed"> 194 <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 195 <pattern low="55" high="58">0011</pattern> <!-- OPC --> 196</bitset> 197 198<bitset name="bkt" extends="#instruction-cat0-immed"> 199 <pattern low="49" high="51">xx1</pattern> <!-- OPC_HI --> 200 <pattern low="55" high="58">0000</pattern> <!-- OPC --> 201</bitset> 202 203<bitset name="getlast" extends="#instruction-cat0"> 204 <doc> 205 Perform a jump for all fibers in the first cluster with any active 206 fibers, except for the last fiber in the cluster. 207 While there is a separate field for CLUSTER_SIZE its value does 208 not change the behaviour in any observable way, it behaves as if 209 CLUSTER_SIZE is always 8. 210 </doc> 211 212 <gen min="600"/> 213 214 <display> 215 {SY}{SS}{JP}{NAME}.w{CLUSTER_SIZE} #{IMMED} 216 </display> 217 <derived name="CLUSTER_SIZE" type="uint"> 218 <expr> 219 2ULL << {W} 220 </expr> 221 </derived> 222 <pattern low="32" high="36">xxxxx</pattern> <!-- INDEX --> 223 <pattern low="37" high="39">xxx</pattern> <!-- BRTYPE --> 224 <pattern low="45" high="47">xxx</pattern> <!-- src1 --> 225 <pattern low="49" high="51">xx1</pattern> <!-- OPC_HI --> 226 <pattern low="55" high="58">0100</pattern> <!-- OPC --> 227 228 <field name="W" low="52" high="54" type="uint"/> 229 230 <encode> 231 <map name="W">util_logbase2(8) - 1</map> 232 </encode> 233</bitset> 234 235<bitset name="getone" extends="#instruction-cat0-immed"> 236 <pattern low="49" high="51">xx1</pattern> <!-- OPC_HI --> 237 <pattern low="55" high="58">0101</pattern> <!-- OPC --> 238</bitset> 239 240<bitset name="shps" extends="#instruction-cat0-immed"> 241 <doc>SHader Prologue Start</doc> 242 <pattern low="49" high="51">xx1</pattern> <!-- OPC_HI --> 243 <pattern low="55" high="58">0111</pattern> <!-- OPC --> 244</bitset> 245 246<bitset name="#instruction-cat0-branch" extends="#instruction-cat0"> 247 <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 248 <pattern low="55" high="58">0001</pattern> <!-- OPC --> 249</bitset> 250 251<bitset name="brac" extends="#instruction-cat0-branch"> 252 <display> 253 {SY}{SS}{EQ}{JP}{NAME}.{INDEX} #{IMMED} 254 </display> 255 <field name="INDEX" low="32" high="36" type="uint"/> 256 <pattern low="37" high="39">011</pattern> <!-- BRTYPE --> 257 <pattern low="45" high="47">xxx</pattern> <!-- src1 --> 258 <pattern low="52" high="54">xxx</pattern> <!-- src0 --> 259 <encode> 260 <map name="INDEX">src->cat0.idx</map> 261 </encode> 262</bitset> 263 264<bitset name="brax" extends="#instruction-cat0-branch"> 265 <pattern low="32" high="36">xxxxx</pattern> 266 <pattern low="37" high="39">110</pattern> <!-- BRTYPE --> 267 <pattern low="45" high="47">xxx</pattern> <!-- src1 --> 268 <pattern low="52" high="54">xxx</pattern> <!-- src0 --> 269</bitset> 270 271<bitset name="#instruction-cat0-branch-1src" extends="#instruction-cat0-branch"> 272 <display> 273 {SY}{SS}{EQ}{JP}{NAME} {INV1}p0.{COMP1}, #{IMMED} 274 </display> 275 <pattern low="32" high="36">xxxxx</pattern> 276 <pattern low="45" high="47">xxx</pattern> <!-- src1 --> 277 <field name="INV1" pos="52" type="bool" display="!"> 278 <doc>Invert source condition</doc> 279 </field> 280 <field name="COMP1" low="53" high="54" type="#swiz"> 281 <doc>Predicate register (p0.c) component for source</doc> 282 </field> 283</bitset> 284 285<bitset name="br" extends="#instruction-cat0-branch-1src"> 286 <pattern low="37" high="39">000</pattern> <!-- BRTYPE --> 287</bitset> 288 289<bitset name="bany" extends="#instruction-cat0-branch-1src"> 290 <pattern low="37" high="39">100</pattern> <!-- BRTYPE --> 291</bitset> 292 293<bitset name="ball" extends="#instruction-cat0-branch-1src"> 294 <pattern low="37" high="39">101</pattern> <!-- BRTYPE --> 295</bitset> 296 297<bitset name="#instruction-cat0-branch-2src" extends="#instruction-cat0-branch"> 298 <display> 299 {SY}{SS}{EQ}{JP}{NAME} {INV1}p0.{COMP1}, {INV2}p0.{COMP2}, #{IMMED} 300 </display> 301 <pattern low="32" high="36">xxxxx</pattern> 302 <!-- src1: --> 303 <field name="INV2" pos="45" type="bool" display="!"> 304 <doc>Invert source 2 condition</doc> 305 </field> 306 <field name="COMP2" low="46" high="47" type="#swiz"> 307 <doc>Predicate register (p0.c) component for source 2</doc> 308 </field> 309 <!-- src0: --> 310 <field name="INV1" pos="52" type="bool" display="!"> 311 <doc>Invert source 1 condition</doc> 312 </field> 313 <field name="COMP1" low="53" high="54" type="#swiz"> 314 <doc>Predicate register (p0.c) component for source 1</doc> 315 </field> 316</bitset> 317 318<bitset name="brao" extends="#instruction-cat0-branch-2src"> 319 <pattern low="37" high="39">001</pattern> <!-- BRTYPE --> 320</bitset> 321 322<bitset name="braa" extends="#instruction-cat0-branch-2src"> 323 <pattern low="37" high="39">010</pattern> <!-- BRTYPE --> 324</bitset> 325 326<!-- TODO rest of cat0 --> 327 328</isa> 329