1<?xml version="1.0" encoding="UTF-8"?> 2<!-- 3Copyright © 2020 Google, Inc. 4 5Permission is hereby granted, free of charge, to any person obtaining a 6copy of this software and associated documentation files (the "Software"), 7to deal in the Software without restriction, including without limitation 8the rights to use, copy, modify, merge, publish, distribute, sublicense, 9and/or sell copies of the Software, and to permit persons to whom the 10Software is furnished to do so, subject to the following conditions: 11 12The above copyright notice and this permission notice (including the next 13paragraph) shall be included in all copies or substantial portions of the 14Software. 15 16THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22SOFTWARE. 23 --> 24 25<isa> 26 27<!-- 28 Cat3 Instructions: three-source ALU instructions 29 --> 30 31<bitset name="#cat3-src" size="13"> 32 <doc> 33 cat3 src1 and src2, some parts are similar to cat2/cat4 src 34 encoding, but a few extra bits trimmed out to squeeze in the 35 3rd src register (dropping (abs), immed encoding, and moving 36 a few other bits elsewhere) 37 </doc> 38 <encode type="struct ir3_register *" case-prefix="REG_"/> 39</bitset> 40 41<bitset name="#cat3-src-gpr" extends="#cat3-src"> 42 <display> 43 {LAST}{HALF}{SRC} 44 </display> 45 <field name="SRC" low="0" high="7" type="#reg-gpr"/> 46 <pattern low="8" high="9">00</pattern> 47 <field name="LAST" pos="10" type="bool" display="(last)"/> 48 <pattern low="11" high="12">00</pattern> 49 <encode> 50 <map name="SRC">src</map> 51 <map name="LAST">!!(src->flags & IR3_REG_LAST_USE)</map> 52 </encode> 53</bitset> 54 55 56<bitset name="#cat3-src-const-or-immed" extends="#cat3-src"> 57 <override> 58 <expr>{IMMED_ENCODING}</expr> 59 <display> 60 {IMMED} 61 </display> 62 <field name="IMMED" low="0" high="11" type="uint"/> 63 </override> 64 65 <display> 66 {HALF}c{CONST}.{SWIZ} 67 </display> 68 <field name="SWIZ" low="0" high="1" type="#swiz"/> 69 <field name="CONST" low="2" high="10" type="uint"/> 70 <pattern pos="12">1</pattern> 71 <assert pos="11">0</assert> 72 <encode> 73 <map name="CONST">src->num >> 2</map> 74 <map name="SWIZ">src->num & 0x3</map> 75 <map name="IMMED">extract_reg_uim(src)</map> 76 </encode> 77</bitset> 78 79<bitset name="#cat3-src-relative" extends="#cat3-src"> 80 <pattern low="11" high="12">01</pattern> 81 <encode> 82 <map name="OFFSET">src->array.offset</map> 83 </encode> 84</bitset> 85 86<bitset name="#cat3-src-relative-gpr" extends="#cat3-src-relative"> 87 <display> 88 {HALF}r<a0.x + {OFFSET}> 89 </display> 90 <field name="OFFSET" low="0" high="9" type="int"/> 91 <pattern pos="10">0</pattern> 92</bitset> 93 94<bitset name="#cat3-src-relative-const" extends="#cat3-src-relative"> 95 <display> 96 {HALF}c<a0.x + {OFFSET}> 97 </display> 98 <field name="OFFSET" low="0" high="9" type="int"/> 99 <pattern pos="10">1</pattern> 100</bitset> 101 102<bitset name="#instruction-cat3-base" extends="#instruction"> 103 <override expr="#cat2-cat3-nop-encoding"> 104 <display> 105 {SY}{SS}{JP}{SAT}(nop{NOP}) {UL}{NAME} {DST_HALF}{DST}, {SRC1_NEG}{SRC1}, {SRC2_NEG}{HALF}{SRC2}, {SRC3_NEG}{SRC3} 106 </display> 107 <derived name="NOP" expr="#cat2-cat3-nop-value" type="uint"/> 108 </override> 109 <display> 110 {SY}{SS}{JP}{SAT}{REPEAT}{UL}{NAME} {DST_HALF}{DST}, {SRC1_NEG}{SRC1_R}{SRC1}, {SRC2_NEG}{SRC2_R}{HALF}{SRC2}, {SRC3_NEG}{SRC3_R}{SRC3} 111 </display> 112 <field name="SRC2_R" pos="15" type="bool" display="(r)"/> 113 <field name="SRC3_R" pos="29" type="bool" display="(r)"/> 114 <field name="DST" low="32" high="39" type="#reg-gpr"/> 115 <field name="REPEAT" low="40" high="41" type="#rptN"/> 116 <field name="SRC1_R" pos="43" type="bool" display="(r)"/> 117 <field name="SS" pos="44" type="bool" display="(ss)"/> 118 <field name="UL" pos="45" type="bool" display="(ul)"/> 119 <field name="SRC2" low="47" high="54" type="#reg-gpr"/> 120 <!-- opcode, 4 bits --> 121 <field name="JP" pos="59" type="bool" display="(jp)"/> 122 <field name="SY" pos="60" type="bool" display="(sy)"/> 123 <pattern low="61" high="63">011</pattern> <!-- cat3 --> 124 <derived name="HALF" expr="#multisrc-half" type="bool" display="h"/> 125 <derived name="DST_HALF" expr="#dest-half" type="bool" display="h"/> 126 <encode> 127 <map name="SRC1_NEG">!!(src->srcs[0]->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map> 128 <map name="SRC1_R">extract_SRC1_R(src)</map> 129 <map name="SRC2_R">extract_SRC2_R(src)</map> 130 <map name="SRC3_R">!!(src->srcs[2]->flags & IR3_REG_R)</map> 131 <map name="SRC2_NEG">!!(src->srcs[1]->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map> 132 <map name="SRC3_NEG">!!(src->srcs[2]->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map> 133 <map name="SRC1">src->srcs[0]</map> 134 </encode> 135</bitset> 136 137<bitset name="#instruction-cat3" extends="#instruction-cat3-base"> 138 <derived name="IMMED_ENCODING" expr="#false" type="bool" display="h"/> 139 140 <field name="SRC1" low="0" high="12" type="#cat3-src"> 141 <param name="HALF"/> 142 <param name="IMMED_ENCODING"/> 143 </field> 144 <field name="SRC1_NEG" pos="14" type="bool" display="(neg)"/> 145 146 <pattern pos="13">0</pattern> 147 148 <field name="SRC3" low="16" high="28" type="#cat3-src"> 149 <param name="HALF"/> 150 <param name="IMMED_ENCODING"/> 151 </field> 152 153 <field name="SRC2_NEG" pos="30" type="bool" display="(neg)"/> 154 <field name="SRC3_NEG" pos="31" type="bool" display="(neg)"/> 155 <field name="SAT" pos="42" type="bool" display="(sat)"/> 156 157 <field name="DST_CONV" pos="46" type="bool"> 158 <doc> 159 The source precision is determined by the instruction 160 opcode. If {DST_CONV} the result is widened/narrowed 161 to the opposite precision. 162 </doc> 163 </field> 164 165 <encode> 166 <map name="DST_CONV"> 167 ((src->dsts[0]->num >> 2) == 62) ? 0 : 168 !!((src->srcs[0]->flags ^ src->dsts[0]->flags) & IR3_REG_HALF) 169 </map> 170 </encode> 171</bitset> 172 173<!-- TODO check on pre a6xx gens --> 174<bitset name="#instruction-cat3-alt" extends="#instruction-cat3-base"> 175 <doc> 176 The difference is that this cat3 version does not support plain 177 const registers as src1/src3 but does support inmidiate values. 178 On the other hand it still supports relative gpr and consts. 179 </doc> 180 181 <gen min="600"/> 182 183 <derived name="IMMED_ENCODING" expr="#true" type="bool" display="h"/> 184 <derived name="SAT" expr="#false" type="bool" display=""/> 185 186 <field name="SRC1" low="0" high="12" type="#cat3-src"> 187 <param name="HALF"/> 188 <param name="IMMED_ENCODING"/> 189 </field> 190 <field name="SRC1_NEG" pos="14" type="bool" display="(neg)"/> 191 192 <pattern pos="13">1</pattern> 193 194 <field name="SRC3" low="16" high="28" type="#cat3-src"> 195 <param name="HALF"/> 196 <param name="IMMED_ENCODING"/> 197 </field> 198 199 <field name="SRC2_NEG" pos="30" type="bool" display="(neg)"/> 200 <field name="SRC3_NEG" pos="31" type="bool" display="(neg)"/> 201 <field name="FULL" pos="42" type="bool"/> 202 <field name="DST_CONV" pos="46" type="bool"/> 203 204 <encode> 205 <map name="SRC3">src->srcs[2]</map> 206 <map name="FULL">!(src->srcs[1]->flags & IR3_REG_HALF)</map> 207 <map name="DST_CONV"> 208 ((src->dsts[0]->num >> 2) == 62) ? 0 : 209 !!((src->srcs[1]->flags ^ src->dsts[0]->flags) & IR3_REG_HALF) 210 </map> 211 </encode> 212</bitset> 213 214<bitset name="mad.u16" extends="#instruction-cat3"> 215 <pattern low="55" high="58">0000</pattern> <!-- OPC --> 216 <derived name="FULL" expr="#false" type="bool"/> 217</bitset> 218 219<bitset name="madsh.u16" extends="#instruction-cat3"> 220 <pattern low="55" high="58">0001</pattern> <!-- OPC --> 221 <derived name="FULL" expr="#true" type="bool"/> 222</bitset> 223 224<bitset name="mad.s16" extends="#instruction-cat3"> 225 <pattern low="55" high="58">0010</pattern> <!-- OPC --> 226 <derived name="FULL" expr="#false" type="bool"/> 227</bitset> 228 229<bitset name="madsh.m16" extends="#instruction-cat3"> 230 <pattern low="55" high="58">0011</pattern> <!-- OPC --> 231 <derived name="FULL" expr="#true" type="bool"/> 232</bitset> 233 234<bitset name="mad.u24" extends="#instruction-cat3"> 235 <pattern low="55" high="58">0100</pattern> <!-- OPC --> 236 <derived name="FULL" expr="#true" type="bool"/> 237</bitset> 238 239<bitset name="mad.s24" extends="#instruction-cat3"> 240 <pattern low="55" high="58">0101</pattern> <!-- OPC --> 241 <derived name="FULL" expr="#true" type="bool"/> 242</bitset> 243 244<bitset name="mad.f16" extends="#instruction-cat3"> 245 <pattern low="55" high="58">0110</pattern> <!-- OPC --> 246 <derived name="FULL" expr="#false" type="bool"/> 247</bitset> 248 249<bitset name="mad.f32" extends="#instruction-cat3"> 250 <pattern low="55" high="58">0111</pattern> <!-- OPC --> 251 <derived name="FULL" expr="#true" type="bool"/> 252</bitset> 253 254<bitset name="sel.b16" extends="#instruction-cat3"> 255 <pattern low="55" high="58">1000</pattern> <!-- OPC --> 256 <derived name="FULL" expr="#false" type="bool"/> 257</bitset> 258 259<bitset name="sel.b32" extends="#instruction-cat3"> 260 <pattern low="55" high="58">1001</pattern> <!-- OPC --> 261 <derived name="FULL" expr="#true" type="bool"/> 262</bitset> 263 264<bitset name="sel.s16" extends="#instruction-cat3"> 265 <pattern low="55" high="58">1010</pattern> <!-- OPC --> 266 <derived name="FULL" expr="#false" type="bool"/> 267</bitset> 268 269<bitset name="sel.s32" extends="#instruction-cat3"> 270 <pattern low="55" high="58">1011</pattern> <!-- OPC --> 271 <derived name="FULL" expr="#true" type="bool"/> 272</bitset> 273 274<bitset name="sel.f16" extends="#instruction-cat3"> 275 <pattern low="55" high="58">1100</pattern> <!-- OPC --> 276 <derived name="FULL" expr="#false" type="bool"/> 277</bitset> 278 279<bitset name="sel.f32" extends="#instruction-cat3"> 280 <pattern low="55" high="58">1101</pattern> <!-- OPC --> 281 <derived name="FULL" expr="#true" type="bool"/> 282</bitset> 283 284<bitset name="sad.s16" extends="#instruction-cat3"> 285 <pattern low="55" high="58">1110</pattern> <!-- OPC --> 286 <derived name="FULL" expr="#false" type="bool"/> 287</bitset> 288 289<bitset name="sad.s32" extends="#instruction-cat3"> 290 <pattern low="55" high="58">1111</pattern> <!-- OPC --> 291 <derived name="FULL" expr="#true" type="bool"/> 292</bitset> 293 294<bitset name="shrm" extends="#instruction-cat3-alt"> 295 <doc> 296 (src2 >> src1) & src3 297 </doc> 298 299 <pattern low="55" high="58">1000</pattern> <!-- OPC --> 300</bitset> 301 302<bitset name="shlm" extends="#instruction-cat3-alt"> 303 <doc> 304 (src2 << src1) & src3 305 </doc> 306 307 <pattern low="55" high="58">1001</pattern> <!-- OPC --> 308</bitset> 309 310<bitset name="shrg" extends="#instruction-cat3-alt"> 311 <doc> 312 (src2 >> src1) | src3 313 </doc> 314 315 <pattern low="55" high="58">1010</pattern> <!-- OPC --> 316</bitset> 317 318<bitset name="shlg" extends="#instruction-cat3-alt"> 319 <doc> 320 (src2 << src1) | src3 321 </doc> 322 323 <pattern low="55" high="58">1011</pattern> <!-- OPC --> 324</bitset> 325 326<bitset name="andg" extends="#instruction-cat3-alt"> 327 <doc> 328 (src2 & src1) | src3 329 </doc> 330 331 <pattern low="55" high="58">1100</pattern> <!-- OPC --> 332</bitset> 333 334<enum name="#signedness"> 335 <value val="0" display=".unsigned"/> 336 <value val="1" display=".mixed"/> 337</enum> 338 339<enum name="#8bitvec2pack"> 340 <value val="0" display=".low"/> 341 <value val="1" display=".high"/> 342</enum> 343 344<bitset name="#instruction-cat3-dp" extends="#instruction-cat3-base"> 345 <gen min="600"/> 346 347 <display> 348 {SY}{SS}{JP}{SAT}(nop{NOP}) {UL}{NAME}{SRC_SIGN}{SRC_PACK} {DST}, {SRC1}, {SRC2}, {SRC3_NEG}{SRC3} 349 </display> 350 351 <derived name="FULL" expr="#true" type="bool"/> 352 353 <field name="SRC1" low="0" high="12" type="#cat3-src"> 354 <param name="HALF"/> 355 </field> 356 <field name="SRC_SIGN" pos="14" type="#signedness"/> 357 358 <pattern pos="13">1</pattern> 359 360 <field name="SRC3" low="16" high="28" type="#cat3-src"> 361 <param name="HALF"/> 362 </field> 363 <field name="SRC_PACK" pos="30" type="#8bitvec2pack"/> 364 <field name="SRC3_NEG" pos="31" type="bool" display="(neg)"/> 365 <field name="SAT" pos="42" type="bool" display="(sat)"/> 366 367 <encode> 368 <map name="SRC3">src->srcs[2]</map> 369 <map name="SRC_SIGN">src->cat3.signedness</map> 370 <map name="SRC_PACK">src->cat3.packed</map> 371 </encode> 372</bitset> 373 374<bitset name="dp2acc" extends="#instruction-cat3-dp"> 375 <doc> 376 Given: 377 SRC1 is a i8vec2 or u8vec2 378 SRC2 is a u8vec2 379 SRC1 and SRC2 are packed into low or high halves of the registers. 380 SRC3 is a int32_t or uint32_t 381 Do: 382 DST = dot(SRC1, SRC2) + SRC3 383 </doc> 384 385 <pattern pos="46">0</pattern> 386 <pattern low="55" high="58">1101</pattern> <!-- OPC --> 387</bitset> 388 389<bitset name="dp4acc" extends="#instruction-cat3-dp"> 390 <doc> 391 Same a dp2acc but for vec4 instead of vec2. 392 Corresponds to packed variantes of OpUDotKHR and OpSUDotKHR. 393 </doc> 394 395 <pattern pos="46">1</pattern> 396 <pattern low="55" high="58">1101</pattern> <!-- OPC --> 397</bitset> 398 399<expr name="#wmm-dest-half"> 400 (!{DST_FULL}) 401</expr> 402 403<bitset name="#instruction-cat3-wmm" extends="#instruction-cat3-base"> 404 <gen min="600"/> 405 406 <derived name="IMMED_ENCODING" expr="#true" type="bool" display="h"/> 407 <derived name="SAT" expr="#false" type="bool" display=""/> 408 <derived name="SRC3_NEG" expr="#false" type="bool" display=""/> 409 <derived name="DST_HALF" expr="#wmm-dest-half" type="bool" display="h"/> 410 411 <field name="SRC1" low="0" high="12" type="#cat3-src"> 412 <param name="HALF"/> 413 </field> 414 415 <pattern pos="13">1</pattern> 416 <field name="SRC1_NEG" pos="14" type="bool" display="(neg)"/> 417 418 <field name="SRC3" low="16" high="28" type="#cat3-src"> 419 <param name="HALF"/> 420 <param name="IMMED_ENCODING"/> 421 </field> 422 423 <field name="SRC2_NEG" pos="30" type="bool" display="(neg)"/> 424 <field name="FULL" pos="31" type="bool" display=""/> 425 <field name="DST_FULL" pos="46" type="bool"/> 426 427 <encode> 428 <map name="SRC3">src->srcs[2]</map> 429 <map name="FULL">!(src->srcs[0]->flags & IR3_REG_HALF)</map> 430 <map name="DST_FULL"> 431 ((src->dsts[0]->num >> 2) == 62) ? 1 : 432 !(src->dsts[0]->flags & IR3_REG_HALF) 433 </map> 434 </encode> 435</bitset> 436 437<bitset name="wmm" extends="#instruction-cat3-wmm"> 438 <doc> 439 Given: 440 SRC1 = (x_1, x_2, x_3, x_4) - 4 consecutive registers 441 SRC2 = (y_1, y_2, y_3, y_4) - 4 consecutive registers 442 SRC3 is an immediate in range of [0, 160] 443 444 Do: 445 float y_sum = y_1 + y_2 + y_3 + y_4 446 vec4 result = (x_1 * y_sum, x_2 * y_sum, x_3 * y_sum, x_4 * y_sum) 447 448 Starting from DST reg duplicate *result* into consecutive registers 449 (1 << (SRC3 / 32)) times. 450 </doc> 451 452 <pattern pos="42">0</pattern> 453 <pattern low="55" high="58">1110</pattern> <!-- OPC --> 454</bitset> 455 456<bitset name="wmm.accu" extends="#instruction-cat3-wmm"> 457 <doc> 458 Same as wmm but instead of overwriting DST - the result is 459 added to DST registers, however the first reg of the result 460 is always overwritten. 461 </doc> 462 463 <pattern pos="42">1</pattern> 464 <pattern low="55" high="58">1110</pattern> <!-- OPC --> 465</bitset> 466 467</isa> 468