1<?xml version="1.0" encoding="UTF-8"?> 2<!-- 3Copyright © 2020 Google, Inc. 4 5Permission is hereby granted, free of charge, to any person obtaining a 6copy of this software and associated documentation files (the "Software"), 7to deal in the Software without restriction, including without limitation 8the rights to use, copy, modify, merge, publish, distribute, sublicense, 9and/or sell copies of the Software, and to permit persons to whom the 10Software is furnished to do so, subject to the following conditions: 11 12The above copyright notice and this permission notice (including the next 13paragraph) shall be included in all copies or substantial portions of the 14Software. 15 16THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22SOFTWARE. 23 --> 24 25<isa> 26 27<!-- 28 Cat5 Instructions: texture instructions 29 --> 30 31<bitset name="#cat5-s2en-bindless-base" size="1"> 32 <doc> 33 The BASE field is actually split across BASE_LO and BASE_HI, 34 but '.baseN' should only appear in the bindless case.. the 35 easiest way to accomplish that is by splitting it out into a 36 bitset. We just arbitrarily map this to BASE_LO 37 </doc> 38 <override> 39 <expr>{BINDLESS}</expr> 40 <display> 41 .base{BASE} 42 </display> 43 </override> 44 <display/> 45 <field name="BASE_LO" pos="0" type="uint"/> 46 <derived name="BASE" type="uint"> 47 <expr>({BASE_HI} * 2) | {BASE_LO}</expr> 48 </derived> 49 <encode type="struct ir3_instruction *"> 50 <map name="BASE_LO">src->cat5.tex_base & 0x1</map> 51 </encode> 52</bitset> 53 54<bitset name="#instruction-cat5" extends="#instruction"> 55 <doc> 56 The "normal" case, ie. not s2en (indirect) and/or bindless 57 </doc> 58 <display> 59 {SY}{JP}{NAME}{3D}{A}{O}{P}{SV}{1D} {TYPE}({WRMASK}){DST_HALF}{DST}{SRC1}{SRC2}{SAMP}{TEX} 60 </display> 61 <derived name="DST_HALF" expr="#type-half" type="bool" display="h"/> 62 <field name="FULL" pos="0" type="bool"/> 63 <derived name="HALF" expr="#multisrc-half" type="bool" display="h"/> 64 <field name="SRC1" low="1" high="8" type="#cat5-src1"> 65 <param name="NUM_SRC"/> 66 <param name="HALF"/> 67 </field> 68 <field name="SRC2" low="9" high="16" type="#cat5-src2"> 69 <param name="NUM_SRC"/> 70 <param name="HALF"/> 71 <param name="O"/> 72 <param name="SRC2_IMM_OFFSET"/> 73 </field> 74 <!-- 75 TODO remainder of first 32b differ depending on s2en/bindless.. 76 possibly use overrides? Need to sort-out how to display.. 77 78 Note b17 seems to show up in some blob traces (samgpN), need 79 to figure out what this bit does 80 --> 81 <pattern pos="17">x</pattern> 82 83 <field name="SAMP" low="21" high="24" type="#cat5-samp"> 84 <param name="HAS_SAMP"/> 85 </field> 86 <field name="TEX" low="25" high="31" type="#cat5-tex"> 87 <param name="HAS_TEX"/> 88 </field> 89 90 <field name="DST" low="32" high="39" type="#reg-gpr"/> 91 <field name="WRMASK" low="40" high="43" type="#wrmask"/> 92 <field name="TYPE" low="44" high="46" type="#cat5-type"> 93 <param name="HAS_TYPE"/> 94 </field> 95 <assert pos="47">0</assert> <!-- BASE_LO --> 96 <field name="3D" pos="48" type="bool" display=".3d"/> 97 <field name="A" pos="49" type="bool" display=".a"/> 98 <field name="S2EN_BINDLESS" pos="51" type="bool"/> 99 <field name="O" pos="52" type="bool" display=".o"/> 100 <!-- OPC --> 101 <field name="JP" pos="59" type="bool" display="(jp)"/> 102 <field name="SY" pos="60" type="bool" display="(sy)"/> 103 <pattern low="61" high="63">101</pattern> <!-- cat5 --> 104 <encode> 105 <map name="FULL">extract_cat5_FULL(src)</map> 106 <map name="TEX">src</map> 107 <map name="SAMP">src</map> 108 <map name="WRMASK">src->dsts[0]->wrmask</map> 109 <map name="BASE">src</map> 110 <map name="TYPE">src</map> 111 <map name="BASE_HI">src->cat5.tex_base >> 1</map> 112 <map name="3D">!!(src->flags & IR3_INSTR_3D)</map> 113 <map name="A">!!(src->flags & IR3_INSTR_A)</map> 114 <map name="S2EN_BINDLESS">!!(src->flags & (IR3_INSTR_S2EN | IR3_INSTR_B))</map> 115 <map name="O">!!(src->flags & IR3_INSTR_O)</map> 116 <map name="DESC_MODE">extract_cat5_DESC_MODE(src)</map> 117 <!-- 118 TODO the src order is currently a bit messy due to ir3 using srcs[0] 119 for s2en src in the s2en case 120 --> 121 <map name="SRC1">extract_cat5_SRC(src, 0)</map> 122 <map name="SRC2">extract_cat5_SRC(src, 1)</map> 123 <map name="SRC3">(src->srcs_count > 0) ? src->srcs[0] : NULL</map> 124 </encode> 125 126 <derived name="SRC2_IMM_OFFSET" expr="#false" type="bool"/> 127 <derived name="P" expr="#false" type="bool" display=""/> 128 <derived name="1D" expr="#false" type="bool" display=""/> 129</bitset> 130 131<bitset name="#instruction-cat5-tex-base" extends="#instruction-cat5"> 132 <override> 133 <expr>{S2EN_BINDLESS}</expr> 134 <doc> 135 The s2en (indirect) or bindless case 136 </doc> 137 <display> 138 {SY}{JP}{NAME}{3D}{A}{O}{P}{SV}{S2EN}{UNIFORM}{NONUNIFORM}{BASE}{1D} {TYPE}({WRMASK}){DST_HALF}{DST}{SRC1}{SRC2}{SRC3}{A1} 139 </display> 140 <field name="BASE_HI" low="19" high="20" type="uint"/> 141 <field name="SRC3" low="21" high="28" type="#cat5-src3"> 142 <param name="BINDLESS"/> 143 <param name="DESC_MODE"/> 144 <param name="HAS_SAMP"/> 145 <param name="HAS_TEX"/> 146 </field> 147 <field name="DESC_MODE" low="29" high="31" type="#cat5-s2en-bindless-desc-mode"/> 148 <field name="BASE" pos="47" type="#cat5-s2en-bindless-base"> 149 <param name="BINDLESS"/> 150 <param name="BASE_HI"/> 151 </field> 152 <derived name="BINDLESS" expr="#cat5-s2enb-is-bindless" type="bool"/> 153 <derived name="S2EN" expr="#cat5-s2enb-is-indirect" type="bool" display=".s2en"/> 154 <derived name="UNIFORM" expr="#cat5-s2enb-is-uniform" type="bool" display=".uniform"/> 155 <derived name="NONUNIFORM" expr="#cat5-s2enb-is-nonuniform" type="bool" display=".nonuniform"/> 156 <derived name="A1" expr="#cat5-s2enb-uses_a1" type="bool" display=", a1.x"/> 157 </override> 158 159 <assert low="19" high="20">00</assert> <!-- BASE_HI --> 160</bitset> 161 162<bitset name="#instruction-cat5-tex" extends="#instruction-cat5-tex-base"> 163 <pattern pos="18">0</pattern> 164 <field name="SV" pos="50" type="bool" display=".s"/> 165 <field name="P" pos="53" type="bool" display=".p"/> 166 167 <encode> 168 <map name="SV">!!(src->flags & IR3_INSTR_S)</map> 169 <map name="P">!!(src->flags & IR3_INSTR_P)</map> 170 </encode> 171</bitset> 172 173<bitset name="isam" extends="#instruction-cat5-tex-base"> 174 <pattern low="54" high="58">00000</pattern> 175 <derived name="NUM_SRC" expr="#one" type="uint"/> 176 <derived name="HAS_SAMP" expr="#true" type="bool"/> 177 <derived name="HAS_TEX" expr="#true" type="bool"/> 178 <derived name="HAS_TYPE" expr="#true" type="bool"/> 179 180 <!-- Not sure what this field does exactly but isam.v does not work 181 without it set. The blob disassembles it as .1d when not set. --> 182 <field name="1D" pos="18" type="bool_inv" display=".1d"/> 183 <field name="SV" pos="50" type="bool" display=".v"/> 184 <field name="SRC2_IMM_OFFSET" pos="53" type="bool"/> 185 186 <encode> 187 <map name="SV">!!(src->flags & IR3_INSTR_V)</map> 188 <map name="1D">!!(src->flags & IR3_INSTR_INV_1D)</map> 189 <map name="SRC2_IMM_OFFSET">!!(src->flags & IR3_INSTR_IMM_OFFSET)</map> 190 </encode> 191</bitset> 192 193<bitset name="isaml" extends="#instruction-cat5-tex"> 194 <pattern low="54" high="58">00001</pattern> 195 <derived name="NUM_SRC" expr="#two" type="uint"/> 196 <derived name="HAS_SAMP" expr="#true" type="bool"/> 197 <derived name="HAS_TEX" expr="#true" type="bool"/> 198 <derived name="HAS_TYPE" expr="#true" type="bool"/> 199</bitset> 200 201<bitset name="isamm" extends="#instruction-cat5-tex"> 202 <pattern low="54" high="58">00010</pattern> 203 <derived name="NUM_SRC" expr="#one" type="uint"/> 204 <derived name="HAS_SAMP" expr="#true" type="bool"/> 205 <derived name="HAS_TEX" expr="#true" type="bool"/> 206 <derived name="HAS_TYPE" expr="#true" type="bool"/> 207</bitset> 208 209<bitset name="sam" extends="#instruction-cat5-tex"> 210 <pattern low="54" high="58">00011</pattern> 211 <derived name="NUM_SRC" expr="#one" type="uint"/> 212 <derived name="HAS_SAMP" expr="#true" type="bool"/> 213 <derived name="HAS_TEX" expr="#true" type="bool"/> 214 <derived name="HAS_TYPE" expr="#true" type="bool"/> 215</bitset> 216 217<bitset name="samb" extends="#instruction-cat5-tex"> 218 <pattern low="54" high="58">00100</pattern> 219 <derived name="NUM_SRC" expr="#two" type="uint"/> 220 <derived name="HAS_SAMP" expr="#true" type="bool"/> 221 <derived name="HAS_TEX" expr="#true" type="bool"/> 222 <derived name="HAS_TYPE" expr="#true" type="bool"/> 223</bitset> 224 225<bitset name="saml" extends="#instruction-cat5-tex"> 226 <pattern low="54" high="58">00101</pattern> 227 <derived name="NUM_SRC" expr="#two" type="uint"/> 228 <derived name="HAS_SAMP" expr="#true" type="bool"/> 229 <derived name="HAS_TEX" expr="#true" type="bool"/> 230 <derived name="HAS_TYPE" expr="#true" type="bool"/> 231</bitset> 232 233<bitset name="samgq" extends="#instruction-cat5-tex"> 234 <pattern low="54" high="58">00110</pattern> 235 <derived name="NUM_SRC" expr="#one" type="uint"/> 236 <derived name="HAS_SAMP" expr="#true" type="bool"/> 237 <derived name="HAS_TEX" expr="#true" type="bool"/> 238 <derived name="HAS_TYPE" expr="#true" type="bool"/> 239</bitset> 240 241<bitset name="getlod" extends="#instruction-cat5-tex"> 242 <pattern low="54" high="58">00111</pattern> 243 <derived name="NUM_SRC" expr="#one" type="uint"/> 244 <derived name="HAS_SAMP" expr="#true" type="bool"/> 245 <derived name="HAS_TEX" expr="#true" type="bool"/> 246 <derived name="HAS_TYPE" expr="#true" type="bool"/> 247</bitset> 248 249<bitset name="conv" extends="#instruction-cat5-tex"> 250 <pattern low="54" high="58">01000</pattern> 251 <derived name="NUM_SRC" expr="#two" type="uint"/> 252 <derived name="HAS_SAMP" expr="#true" type="bool"/> 253 <derived name="HAS_TEX" expr="#true" type="bool"/> 254 <derived name="HAS_TYPE" expr="#true" type="bool"/> 255</bitset> 256 257<bitset name="convm" extends="#instruction-cat5-tex"> 258 <pattern low="54" high="58">01001</pattern> 259 <derived name="NUM_SRC" expr="#two" type="uint"/> 260 <derived name="HAS_SAMP" expr="#true" type="bool"/> 261 <derived name="HAS_TEX" expr="#true" type="bool"/> 262 <derived name="HAS_TYPE" expr="#true" type="bool"/> 263</bitset> 264 265<bitset name="getsize" extends="#instruction-cat5-tex"> 266 <pattern low="54" high="58">01010</pattern> 267 <derived name="NUM_SRC" expr="#one" type="uint"/> 268 <derived name="HAS_SAMP" expr="#false" type="bool"/> 269 <derived name="HAS_TEX" expr="#true" type="bool"/> 270 <derived name="HAS_TYPE" expr="#true" type="bool"/> 271</bitset> 272 273<bitset name="getbuf" extends="#instruction-cat5-tex"> 274 <pattern low="54" high="58">01011</pattern> 275 <derived name="NUM_SRC" expr="#zero" type="uint"/> 276 <derived name="HAS_SAMP" expr="#false" type="bool"/> 277 <derived name="HAS_TEX" expr="#true" type="bool"/> 278 <derived name="HAS_TYPE" expr="#true" type="bool"/> 279</bitset> 280 281<bitset name="getpos" extends="#instruction-cat5-tex"> 282 <pattern low="54" high="58">01100</pattern> 283 <derived name="NUM_SRC" expr="#one" type="uint"/> 284 <derived name="HAS_SAMP" expr="#false" type="bool"/> 285 <derived name="HAS_TEX" expr="#true" type="bool"/> 286 <derived name="HAS_TYPE" expr="#true" type="bool"/> 287</bitset> 288 289<bitset name="getinfo" extends="#instruction-cat5-tex"> 290 <doc> 291 GETINFO returns 4 values, in .xyzw: 292 293 x: A value associated with the channel type, i.e. OpenCL's 294 get_image_channel_data_type: 295 296 The below was RE'd on A420 and confirmed with the 297 blob's headers. 298 299 8_SNORM: 0 (CLK_SNORM_INT8) 300 16_SNORM: 1 (CLK_SNORM_INT16) 301 8_UNORM: 2 (CLK_UNORM_INT8) 302 16_UNORM: 3 (CLK_UNORM_INT16) 303 5_6_5_UNORM: 4 (CLK_UNORM_SHORT_565) 304 5_5_5_1_UNORM: 5 (CLK_UNORM_SHORT_555) 305 10_10_10_2_UNORM: 6 (CLK_UNORM_INT_101010, CLK_UNORM_SHORT_101010) 306 8_SINT: 7 (CLK_SIGNED_INT8) 307 16_SINT: 8 (CLK_SIGNED_INT16) 308 32_SINT: 9 (CLK_SIGNED_INT32) 309 8_UINT: 10 (CLK_UNSIGNED_INT8) 310 16_UINT: 11 (CLK_UNSIGNED_INT16) 311 32_UINT: 12 (CLK_UNSIGNED_INT32) 312 16_FLOAT: 13 (CLK_HALF_FLOAT) 313 32_FLOAT: 14 (CLK_FLOAT) 314 9_9_9_E5_FLOAT: 15 (CLK_FLOAT_10F_11F_11F) 315 11_11_10_FLOAT: 15 (CLK_FLOAT_10F_11F_11F) 316 10_10_10_2_UINT: 16 (CLK_UNSIGNED_SHORT_101010) 317 4_4_4_4_UNORM: 17 (CLK_UNORM_INT4) 318 X8Z24_UNORM: 18 (CLK_UNORM_INT32) 319 320 y: A value associated with the number of components 321 and swizzle, i.e. OpenCL's get_image_channel_order: 322 323 The below was largely taken from the blob's headers. 324 325 A3xx/A4xx: 326 327 0: CLK_A 328 1: CLK_R 329 2: CLK_Rx 330 3: CLK_RG 331 4: CLK_RGx 332 5: CLK_RA 333 6: CLK_RGB 334 7: CLK_RGBx 335 8: CLK_RGBA 336 9: CLK_ARGB 337 10: CLK_BGRA 338 11: CLK_LUMINANCE 339 12: CLK_INTENSITY 340 13: CLK_ABGR 341 14: CLK_BGR 342 15: CLK_sRGB 343 16: CLK_sRGBA 344 17: CLK_DEPTH 345 346 A5xx/A6xx: 347 348 0: CLK_A 349 1: CLK_R 350 2: CLK_RX 351 3: CLK_RG 352 4: CLK_RGX 353 5: CLK_RA 354 6: CLK_RGB 355 7: CLK_RGBX 356 8: CLK_RGBA 357 9: CLK_ARGB 358 10: CLK_BGRA 359 11: CLK_INTENSITY 360 12: CLK_LUMINANCE 361 13: CLK_ABGR 362 14: CLK_DEPTH 363 15: CLK_sRGB 364 16: CLK_sRGBx 365 17: CLK_sRGBA 366 18: CLK_sBGRA 367 19: CLK_sARGB 368 20: CLK_sABGR 369 21: CLK_BGR 370 371 z: Number of levels 372 373 w: Number of samples 374 </doc> 375 <pattern low="54" high="58">01101</pattern> 376 <derived name="NUM_SRC" expr="#zero" type="uint"/> 377 <derived name="HAS_SAMP" expr="#false" type="bool"/> 378 <derived name="HAS_TEX" expr="#true" type="bool"/> 379 <derived name="HAS_TYPE" expr="#true" type="bool"/> 380</bitset> 381 382<bitset name="dsx" extends="#instruction-cat5-tex"> 383 <pattern low="54" high="58">01110</pattern> 384 <derived name="NUM_SRC" expr="#one" type="uint"/> 385 <derived name="HAS_SAMP" expr="#false" type="bool"/> 386 <derived name="HAS_TEX" expr="#false" type="bool"/> 387 <derived name="HAS_TYPE" expr="#true" type="bool"/> 388</bitset> 389 390<bitset name="dsy" extends="#instruction-cat5-tex"> 391 <pattern low="54" high="58">01111</pattern> 392 <derived name="NUM_SRC" expr="#one" type="uint"/> 393 <derived name="HAS_SAMP" expr="#false" type="bool"/> 394 <derived name="HAS_TEX" expr="#false" type="bool"/> 395 <derived name="HAS_TYPE" expr="#true" type="bool"/> 396</bitset> 397 398<bitset name="gather4r" extends="#instruction-cat5-tex"> 399 <pattern low="54" high="58">10000</pattern> 400 <derived name="NUM_SRC" expr="#one" type="uint"/> 401 <derived name="HAS_SAMP" expr="#true" type="bool"/> 402 <derived name="HAS_TEX" expr="#true" type="bool"/> 403 <derived name="HAS_TYPE" expr="#true" type="bool"/> 404</bitset> 405 406<bitset name="gather4g" extends="#instruction-cat5-tex"> 407 <pattern low="54" high="58">10001</pattern> 408 <derived name="NUM_SRC" expr="#one" type="uint"/> 409 <derived name="HAS_SAMP" expr="#true" type="bool"/> 410 <derived name="HAS_TEX" expr="#true" type="bool"/> 411 <derived name="HAS_TYPE" expr="#true" type="bool"/> 412</bitset> 413 414<bitset name="gather4b" extends="#instruction-cat5-tex"> 415 <pattern low="54" high="58">10010</pattern> 416 <derived name="NUM_SRC" expr="#one" type="uint"/> 417 <derived name="HAS_SAMP" expr="#true" type="bool"/> 418 <derived name="HAS_TEX" expr="#true" type="bool"/> 419 <derived name="HAS_TYPE" expr="#true" type="bool"/> 420</bitset> 421 422<bitset name="gather4a" extends="#instruction-cat5-tex"> 423 <pattern low="54" high="58">10011</pattern> 424 <derived name="NUM_SRC" expr="#one" type="uint"/> 425 <derived name="HAS_SAMP" expr="#true" type="bool"/> 426 <derived name="HAS_TEX" expr="#true" type="bool"/> 427 <derived name="HAS_TYPE" expr="#true" type="bool"/> 428</bitset> 429 430<bitset name="samgp0" extends="#instruction-cat5-tex"> 431 <pattern low="54" high="58">10100</pattern> 432 <derived name="NUM_SRC" expr="#one" type="uint"/> 433 <derived name="HAS_SAMP" expr="#true" type="bool"/> 434 <derived name="HAS_TEX" expr="#true" type="bool"/> 435 <derived name="HAS_TYPE" expr="#true" type="bool"/> 436</bitset> 437 438<bitset name="samgp1" extends="#instruction-cat5-tex"> 439 <pattern low="54" high="58">10101</pattern> 440 <derived name="NUM_SRC" expr="#one" type="uint"/> 441 <derived name="HAS_SAMP" expr="#true" type="bool"/> 442 <derived name="HAS_TEX" expr="#true" type="bool"/> 443 <derived name="HAS_TYPE" expr="#true" type="bool"/> 444</bitset> 445 446<bitset name="samgp2" extends="#instruction-cat5-tex"> 447 <pattern low="54" high="58">10110</pattern> 448 <derived name="NUM_SRC" expr="#one" type="uint"/> 449 <derived name="HAS_SAMP" expr="#true" type="bool"/> 450 <derived name="HAS_TEX" expr="#true" type="bool"/> 451 <derived name="HAS_TYPE" expr="#true" type="bool"/> 452</bitset> 453 454<bitset name="samgp3" extends="#instruction-cat5-tex"> 455 <pattern low="54" high="58">10111</pattern> 456 <derived name="NUM_SRC" expr="#one" type="uint"/> 457 <derived name="HAS_SAMP" expr="#true" type="bool"/> 458 <derived name="HAS_TEX" expr="#true" type="bool"/> 459 <derived name="HAS_TYPE" expr="#true" type="bool"/> 460</bitset> 461 462<bitset name="dsxpp.1" extends="#instruction-cat5-tex"> 463 <pattern low="54" high="58">11000</pattern> 464 <derived name="NUM_SRC" expr="#one" type="uint"/> 465 <derived name="HAS_SAMP" expr="#false" type="bool"/> 466 <derived name="HAS_TEX" expr="#false" type="bool"/> 467 <derived name="HAS_TYPE" expr="#false" type="bool"/> 468</bitset> 469 470<bitset name="dsypp.1" extends="#instruction-cat5-tex"> 471 <pattern low="54" high="58">11001</pattern> 472 <derived name="NUM_SRC" expr="#one" type="uint"/> 473 <derived name="HAS_SAMP" expr="#false" type="bool"/> 474 <derived name="HAS_TEX" expr="#false" type="bool"/> 475 <derived name="HAS_TYPE" expr="#false" type="bool"/> 476</bitset> 477 478<bitset name="rgetpos" extends="#instruction-cat5-tex"> 479 <pattern low="54" high="58">11010</pattern> 480 <derived name="NUM_SRC" expr="#one" type="uint"/> 481 <derived name="HAS_SAMP" expr="#false" type="bool"/> 482 <derived name="HAS_TEX" expr="#false" type="bool"/> 483 <derived name="HAS_TYPE" expr="#true" type="bool"/> 484</bitset> 485 486<bitset name="rgetinfo" extends="#instruction-cat5-tex"> 487 <pattern low="54" high="58">11011</pattern> 488 <derived name="NUM_SRC" expr="#zero" type="uint"/> 489 <derived name="HAS_SAMP" expr="#false" type="bool"/> 490 <derived name="HAS_TEX" expr="#false" type="bool"/> 491 <derived name="HAS_TYPE" expr="#true" type="bool"/> 492</bitset> 493 494<bitset name="tcinv" extends="#instruction"> 495 <doc> 496 Texture Cache Invalidate ? 497 </doc> 498 <display> 499 {SY}{JP}{NAME} 500 </display> 501 <pattern low="0" high="31">xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx</pattern> 502 <pattern low="32" high="53">xxxxxxxxxxxxxxxxxxxxxx</pattern> 503 <pattern low="54" high="58">11100</pattern> 504 <field name="JP" pos="59" type="bool" display="(jp)"/> 505 <field name="SY" pos="60" type="bool" display="(sy)"/> 506 <pattern low="61" high="63">101</pattern> <!-- cat5 --> 507</bitset> 508 509<bitset name="#instruction-cat5-brcst" extends="#instruction-cat5"> 510 <pattern pos="18">0</pattern> 511 <pattern pos="50">0</pattern> 512</bitset> 513 514<bitset name="brcst.active" extends="#instruction-cat5-brcst"> 515 <doc> 516 The subgroup is divided into (subgroup_size / CLUSTER_SIZE) 517 clusters. For each cluster brcst.active.w does: 518 519 Given a cluster of fibers f_0, f_1, ..., f_{CLUSTER_SIZE-1} brcst 520 broadcasts the SRC value from the fiber f_{CLUSTER_SIZE/2-1} 521 to fibers f_{CLUSTER_SIZE/2}, ..., f_{CLUSTER_SIZE-1}. The DST reg 522 in other fibers is unaffected. If fiber f_{CLUSTER_SIZE/2-1} is 523 inactive the value to broadcast is taken from lower fibers 524 f_{CLUSTER_SIZE/2-2}, f_{CLUSTER_SIZE/2-3}, ... 525 If all fibers f_0, f_1, ..., f_{CLUSTER_SIZE/2-1} are inactive 526 the DST reg remains unchanged for all fibers. 527 528 It is necessary in order to implement arithmetic subgroup 529 operations with prefix sum (https://en.wikipedia.org/wiki/Prefix_sum). 530 531 For brcst.active.w8 without inactive fibers: 532 Fiber | 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 533 SRC | s0 s1 s2 s3 ... s7 | s8 ... s11 ... s15 534 DST_before | d0 d1 ... d7 | d8 ... d15 535 DST_after | d0 d1 d2 d3 s3 s3 s3 s3 | d8 ... d11 s11 s11 s11 s11 536 537 If fibers 2 and 3 are inactive: 538 Fiber | 0 1 X X 4 5 6 7 | ... 539 SRC | s0 s1 X X ... s7 | ... 540 DST_before | d0 d1 ... d7 | ... 541 DST_after | d0 d1 X X s1 s1 s1 s1 | ... 542 </doc> 543 544 <gen min="600"/> 545 546 <display> 547 {SY}{JP}{NAME}.w{CLUSTER_SIZE} {TYPE}({WRMASK}){DST_HALF}{DST}{SRC1} 548 </display> 549 550 <field name="W" low="19" high="20" type="uint"/> 551 <pattern low="53" high="58">111110</pattern> <!-- OPC --> 552 553 <derived name="CLUSTER_SIZE" type="uint"> 554 <expr> 555 2 << {W} 556 </expr> 557 </derived> 558 <derived name="NUM_SRC" expr="#one" type="uint"/> 559 <derived name="HAS_SAMP" expr="#false" type="bool"/> 560 <derived name="HAS_TEX" expr="#false" type="bool"/> 561 <derived name="HAS_TYPE" expr="#true" type="bool"/> 562 563 <encode> 564 <map name="W">util_logbase2(src->cat5.cluster_size) - 1</map> 565 </encode> 566</bitset> 567 568<bitset name="#instruction-cat5-quad-shuffle" extends="#instruction-cat5-brcst"> 569 <gen min="600"/> 570 571 <display> 572 {SY}{JP}{NAME} {TYPE}({WRMASK}){DST_HALF}{DST}{SRC1}{SRC2} 573 </display> 574 575 <pattern low="53" high="58">111111</pattern> <!-- OPC --> 576 577 <derived name="HAS_SAMP" expr="#false" type="bool"/> 578 <derived name="HAS_TEX" expr="#false" type="bool"/> 579 <derived name="HAS_TYPE" expr="#true" type="bool"/> 580</bitset> 581 582<bitset name="quad_shuffle.brcst" extends="#instruction-cat5-quad-shuffle"> 583 <doc>subgroupQuadBroadcast</doc> 584 585 <pattern low="19" high="20">00</pattern> <!-- Quad-shuffle variant --> 586 587 <derived name="NUM_SRC" expr="#two" type="uint"/> 588</bitset> 589 590<bitset name="quad_shuffle.horiz" extends="#instruction-cat5-quad-shuffle"> 591 <doc>subgroupQuadSwapHorizontal</doc> 592 593 <pattern low="19" high="20">01</pattern> <!-- Quad-shuffle variant --> 594 595 <derived name="NUM_SRC" expr="#one" type="uint"/> 596</bitset> 597 598<bitset name="quad_shuffle.vert" extends="#instruction-cat5-quad-shuffle"> 599 <doc>subgroupQuadSwapVertical</doc> 600 601 <pattern low="19" high="20">10</pattern> <!-- Quad-shuffle variant --> 602 603 <derived name="NUM_SRC" expr="#one" type="uint"/> 604</bitset> 605 606<bitset name="quad_shuffle.diag" extends="#instruction-cat5-quad-shuffle"> 607 <doc>subgroupQuadSwapDiagonal</doc> 608 609 <pattern low="19" high="20">11</pattern> <!-- Quad-shuffle variant --> 610 611 <derived name="NUM_SRC" expr="#one" type="uint"/> 612</bitset> 613 614<!-- 615 All the magic for conditionally displaying various srcs, etc 616 for the non-bindless / non-indirect case, or things that are in 617 common with the bindless / indirect case 618 --> 619 620<bitset name="#cat5-src1" size="8"> 621 <override> 622 <expr>{NUM_SRC} > 0</expr> 623 <display> 624 , {HALF}{SRC} 625 </display> 626 <field name="SRC" low="0" high="7" type="#reg-gpr"/> 627 </override> 628 <display/> 629 <assert low="0" high="7">00000000</assert> 630 <encode type="struct ir3_register *"> 631 <map name="SRC">src</map> 632 </encode> 633</bitset> 634 635<bitset name="#cat5-src2" size="8"> 636 <override> 637 <expr>{O} || ({NUM_SRC} > 1)</expr> 638 <display> 639 , {HALF}{SRC} 640 </display> 641 <field name="SRC" low="0" high="7" type="#reg-gpr"/> 642 </override> 643 <override> 644 <expr>{SRC2_IMM_OFFSET}</expr> 645 <display> 646 {OFF} 647 </display> 648 <field name="OFF" low="0" high="7" type="uoffset"/> 649 </override> 650 <display/> 651 <assert low="0" high="7">00000000</assert> 652 <encode type="struct ir3_register *"> 653 <map name="SRC">src</map> 654 <map name="OFF">extract_reg_uim(src)</map> 655 </encode> 656</bitset> 657 658<bitset name="#cat5-samp" size="4"> 659 <override> 660 <expr>{HAS_SAMP}</expr> 661 <display> 662 , s#{SAMP} 663 </display> 664 <field name="SAMP" low="0" high="3" type="uint"/> 665 </override> 666 <display/> 667 <assert low="0" high="3">0000</assert> 668 <encode type="struct ir3_instruction *"> 669 <map name="SAMP">src->cat5.samp</map> 670 </encode> 671</bitset> 672 673<bitset name="#cat5-samp-s2en-bindless-a1" size="8"> 674 <doc>s2en (indirect) / bindless case with tex in a1.x</doc> 675 <override> 676 <expr>{HAS_SAMP}</expr> 677 <display> 678 , s#{SAMP} 679 </display> 680 <field name="SAMP" low="0" high="7" type="uint"/> 681 </override> 682 <display/> 683 <assert low="0" high="7">00000000</assert> 684 <encode type="struct ir3_instruction *"> 685 <map name="SAMP">src->cat5.samp</map> 686 </encode> 687</bitset> 688 689<bitset name="#cat5-tex-s2en-bindless-a1" size="8"> 690 <doc>s2en (indirect) / bindless case with samp in a1.x</doc> 691 <override> 692 <expr>{HAS_TEX}</expr> 693 <display> 694 , t#{TEX} 695 </display> 696 <field name="TEX" low="0" high="7" type="uint"/> 697 </override> 698 <display/> 699 <assert low="0" high="7">00000000</assert> 700 <encode type="struct ir3_instruction *"> 701 <map name="TEX">src->cat5.tex</map> 702 </encode> 703</bitset> 704 705<bitset name="#cat5-tex" size="7"> 706 <override> 707 <expr>{HAS_TEX}</expr> 708 <display> 709 , t#{TEX} 710 </display> 711 <field name="TEX" low="0" high="6" type="uint"/> 712 </override> 713 <display/> 714 <assert low="0" high="6">0000000</assert> 715 <encode type="struct ir3_instruction *"> 716 <map name="TEX">src->cat5.tex</map> 717 </encode> 718</bitset> 719 720<bitset name="#cat5-tex-s2en-bindless" size="4"> 721 <doc>s2en (indirect) / bindless case only has 4b tex</doc> 722 <override> 723 <expr>{HAS_TEX}</expr> 724 <display> 725 , t#{TEX} 726 </display> 727 <field name="TEX" low="0" high="3" type="uint"/> 728 </override> 729 <display/> 730 <assert low="0" high="3">0000</assert> 731 <encode type="struct ir3_instruction *"> 732 <map name="TEX">src->cat5.tex</map> 733 </encode> 734</bitset> 735 736<bitset name="#cat5-type" size="3"> 737 <display/> 738 <override> 739 <expr>{HAS_TYPE}</expr> 740 <display> 741 ({TYPE}) 742 </display> 743 </override> 744 <field name="TYPE" low="0" high="2" type="#type"/> 745 <encode type="struct ir3_instruction *"> 746 <!-- 747 Normally we only encode fields that have visible impact on 748 the decoded disasm, but the type field is one of those 749 special exceptions 750 --> 751 <map name="TYPE" force="true">src->cat5.type</map> 752 </encode> 753</bitset> 754 755<!-- 756 Helpers/bitsets/etc for dealing with the bindless/indirect case: 757 --> 758 759<enum name="#cat5-s2en-bindless-desc-mode"> 760 <doc> 761 We don't actually display this enum, but it is useful to 762 document the various cases 763 764 TODO we should probably have an option for uniforms w/out 765 display strings, but which have 'C' names that can be used 766 to generate header that the compiler can use 767 </doc> 768 <value val="0" display="CAT5_UNIFORM"> 769 <doc> 770 Use traditional GL binding model, get texture and sampler index 771 from src3 which is presumed to be uniform on a4xx+ (a3xx doesn't 772 have the other modes, but does handle non-uniform indexing). 773 </doc> 774 </value> 775 <value val="1" display="CAT5_BINDLESS_A1_UNIFORM"> 776 <doc> 777 The sampler base comes from the low 3 bits of a1.x, and the sampler 778 and texture index come from src3 which is presumed to be uniform. 779 </doc> 780 </value> 781 <value val="2" display="CAT5_BINDLESS_NONUNIFORM"> 782 <doc> 783 The texture and sampler share the same base, and the sampler and 784 texture index come from src3 which is *not* presumed to be uniform. 785 </doc> 786 </value> 787 <value val="3" display="CAT5_BINDLESS_A1_NONUNIFORM"> 788 <doc> 789 The sampler base comes from the low 3 bits of a1.x, and the sampler 790 and texture index come from src3 which is *not* presumed to be 791 uniform. 792 </doc> 793 </value> 794 <value val="4" display="CAT5_NONUNIFORM"> 795 <doc> 796 Use traditional GL binding model, get texture and sampler index 797 from src3 which is *not* presumed to be uniform. 798 </doc> 799 </value> 800 <value val="5" display="CAT5_BINDLESS_UNIFORM"> 801 <doc> 802 The texture and sampler share the same base, and the sampler and 803 texture index come from src3 which is presumed to be uniform. 804 </doc> 805 </value> 806 <value val="6" display="CAT5_BINDLESS_IMM"> 807 <doc> 808 The texture and sampler share the same base, get sampler index from low 809 4 bits of src3 and texture index from high 4 bits. 810 </doc> 811 </value> 812 <value val="7" display="CAT5_BINDLESS_A1_IMM"> 813 <doc> 814 The sampler base comes from the low 3 bits of a1.x, and the texture 815 index comes from the next 8 bits of a1.x. The sampler index is an 816 immediate in src3. 817 </doc> 818 </value> 819</enum> 820 821<!-- Helper to map s2en/bindless DESC_MODE to whether it is an indirect mode --> 822<expr name="#cat5-s2enb-is-indirect"> 823 {DESC_MODE} < 6 /* CAT5_BINDLESS_IMM */ 824</expr> 825 826<!-- Helper to map s2en/bindless DESC_MODE to whether it is a bindless mode --> 827<expr name="#cat5-s2enb-is-bindless"> 828 ({DESC_MODE} == 1) /* CAT5_BINDLESS_A1_UNIFORM */ || 829 ({DESC_MODE} == 2) /* CAT5_BINDLESS_NONUNIFORM */ || 830 ({DESC_MODE} == 3) /* CAT5_BINDLESS_A1_NONUNIFORM */ || 831 ({DESC_MODE} == 5) /* CAT5_BINDLESS_UNIFORM */ || 832 ({DESC_MODE} == 6) /* CAT5_BINDLESS_IMM */ || 833 ({DESC_MODE} == 7) /* CAT5_BINDLESS_A1_IMM */ 834</expr> 835 836<!-- Helper to map s2en/bindless DESC_MODE to whether it uses a1.x --> 837<expr name="#cat5-s2enb-uses_a1"> 838 ({DESC_MODE} == 1) /* CAT5_BINDLESS_A1_UNIFORM */ || 839 ({DESC_MODE} == 3) /* CAT5_BINDLESS_A1_NONUNIFORM */ || 840 ({DESC_MODE} == 7) /* CAT5_BINDLESS_A1_IMM */ 841</expr> 842 843<expr name="#cat5-s2enb-uses_a1-gen6"> 844 ISA_GPU_ID() >= 600 && ISA_GPU_ID() < 700 && 845 (({DESC_MODE} == 1) /* CAT5_BINDLESS_A1_UNIFORM */ || 846 ({DESC_MODE} == 3) /* CAT5_BINDLESS_A1_NONUNIFORM */ || 847 ({DESC_MODE} == 7))/* CAT5_BINDLESS_A1_IMM */ 848</expr> 849 850<expr name="#cat5-s2enb-uses_a1-gen7"> 851 ISA_GPU_ID() >= 700 && 852 (({DESC_MODE} == 1) /* CAT5_BINDLESS_A1_UNIFORM */ || 853 ({DESC_MODE} == 3) /* CAT5_BINDLESS_A1_NONUNIFORM */ || 854 ({DESC_MODE} == 7))/* CAT5_BINDLESS_A1_IMM */ 855</expr> 856 857<!-- Helper to map s2en/bindless DESC_MODE to whether it is uniform (flow control) mode --> 858<expr name="#cat5-s2enb-is-uniform"> 859 ({DESC_MODE} == 0) /* CAT5_UNIFORM */ || 860 ({DESC_MODE} == 1) /* CAT5_BINDLESS_A1_UNIFORM */ || 861 ({DESC_MODE} == 5) /* CAT5_BINDLESS_UNIFORM */ 862</expr> 863 864<!-- Helper to map s2en/bindless DESC_MODE to whether it is non-uniform mode. --> 865<expr name="#cat5-s2enb-is-nonuniform"> 866 ({DESC_MODE} == 2) /* CAT5_BINDLESS_NONUNIFORM */ || 867 ({DESC_MODE} == 3) /* CAT5_BINDLESS_A1_NONUNIFORM */ || 868 ({DESC_MODE} == 4) /* CAT5_NONUNIFORM */ 869</expr> 870 871<bitset name="#cat5-src3" size="8"> 872 <doc>bindless/indirect src3, which can either be GPR or samp/tex</doc> 873 <override expr="#cat5-s2enb-is-indirect"> 874 <display> 875 , {SRC_HALF}{SRC} 876 </display> 877 <field name="SRC" low="0" high="7" type="#reg-gpr"/> 878 <derived name="SRC_HALF" type="bool" display="h"> 879 <expr>!{BINDLESS}</expr> 880 </derived> 881 </override> 882 <override expr="#cat5-s2enb-uses_a1-gen6"> 883 <doc> 884 In the case that a1.x is used, all 8 bits encode sampler 885 </doc> 886 <display> 887 {SAMP} 888 </display> 889 <field name="SAMP" low="0" high="7" type="#cat5-samp-s2en-bindless-a1"> 890 <param name="HAS_SAMP"/> 891 </field> 892 </override> 893 <override expr="#cat5-s2enb-uses_a1-gen7"> 894 <doc> 895 In the case that a1.x is used, all 8 bits encode texture 896 </doc> 897 <display> 898 {TEX} 899 </display> 900 <field name="TEX" low="0" high="7" type="#cat5-tex-s2en-bindless-a1"> 901 <param name="HAS_TEX"/> 902 </field> 903 </override> 904 <display> 905 {SAMP}{TEX} 906 </display> 907 <field name="SAMP" low="0" high="3" type="#cat5-samp"> 908 <param name="HAS_SAMP"/> 909 </field> 910 <field name="TEX" low="4" high="7" type="#cat5-tex-s2en-bindless"> 911 <param name="HAS_TEX"/> 912 </field> 913 <encode type="struct ir3_register *"> 914 <map name="SAMP">s->instr</map> 915 <map name="TEX">s->instr</map> 916 <map name="SRC">src</map> 917 </encode> 918</bitset> 919 920</isa> 921