1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 * SPDX-License-Identifier: MIT
5 *
6 * based in part on anv driver which is:
7 * Copyright © 2015 Intel Corporation
8 */
9
10 #ifndef TU_PIPELINE_H
11 #define TU_PIPELINE_H
12
13 #include "tu_common.h"
14
15 #include "tu_cs.h"
16 #include "tu_descriptor_set.h"
17 #include "tu_shader.h"
18 #include "tu_suballoc.h"
19
20 enum tu_dynamic_state
21 {
22 TU_DYNAMIC_STATE_VIEWPORT,
23 TU_DYNAMIC_STATE_SCISSOR,
24 TU_DYNAMIC_STATE_RAST,
25 TU_DYNAMIC_STATE_DEPTH_BIAS,
26 TU_DYNAMIC_STATE_BLEND_CONSTANTS,
27 TU_DYNAMIC_STATE_DS,
28 TU_DYNAMIC_STATE_RB_DEPTH_CNTL,
29 TU_DYNAMIC_STATE_SAMPLE_LOCATIONS,
30 TU_DYNAMIC_STATE_VB_STRIDE,
31 TU_DYNAMIC_STATE_BLEND,
32 TU_DYNAMIC_STATE_VERTEX_INPUT,
33 TU_DYNAMIC_STATE_PATCH_CONTROL_POINTS,
34 TU_DYNAMIC_STATE_PRIM_MODE_SYSMEM,
35 TU_DYNAMIC_STATE_A7XX_FRAGMENT_SHADING_RATE = TU_DYNAMIC_STATE_PRIM_MODE_SYSMEM,
36 TU_DYNAMIC_STATE_COUNT,
37 };
38
39 struct cache_entry;
40
41 struct tu_lrz_blend
42 {
43 bool valid;
44 bool reads_dest;
45 };
46
47 struct tu_bandwidth
48 {
49 uint32_t color_bandwidth_per_sample;
50 uint32_t depth_cpp_per_sample;
51 uint32_t stencil_cpp_per_sample;
52 bool valid;
53 };
54
55 struct tu_nir_shaders
56 {
57 struct vk_pipeline_cache_object base;
58
59 /* This is optional, and is only filled out when a library pipeline is
60 * compiled with RETAIN_LINK_TIME_OPTIMIZATION_INFO.
61 */
62 nir_shader *nir[MESA_SHADER_STAGES];
63 };
64
65 extern const struct vk_pipeline_cache_object_ops tu_nir_shaders_ops;
66
67 static bool inline
tu6_shared_constants_enable(const struct tu_pipeline_layout * layout,const struct ir3_compiler * compiler)68 tu6_shared_constants_enable(const struct tu_pipeline_layout *layout,
69 const struct ir3_compiler *compiler)
70 {
71 return layout->push_constant_size > 0 &&
72 layout->push_constant_size <= (compiler->shared_consts_size * 16);
73 }
74
75 enum ir3_push_consts_type
76 tu_push_consts_type(const struct tu_pipeline_layout *layout,
77 const struct ir3_compiler *compiler);
78
79 struct tu_program_descriptor_linkage
80 {
81 struct ir3_const_state const_state;
82
83 uint32_t constlen;
84
85 struct tu_const_state tu_const_state;
86 };
87
88 struct tu_program_state
89 {
90 struct tu_draw_state config_state;
91 struct tu_draw_state vs_state, vs_binning_state;
92 struct tu_draw_state hs_state;
93 struct tu_draw_state ds_state;
94 struct tu_draw_state gs_state, gs_binning_state;
95 struct tu_draw_state vpc_state;
96 struct tu_draw_state fs_state;
97
98 struct tu_push_constant_range shared_consts;
99
100 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
101
102 unsigned dynamic_descriptor_offsets[MAX_SETS];
103
104 bool per_view_viewport;
105 bool writes_shading_rate;
106 bool reads_shading_rate;
107 bool accesses_smask;
108 };
109
110 struct tu_pipeline_executable {
111 gl_shader_stage stage;
112
113 struct ir3_info stats;
114 bool is_binning;
115
116 char *nir_from_spirv;
117 char *nir_final;
118 char *disasm;
119 };
120
121 enum tu_pipeline_type {
122 TU_PIPELINE_GRAPHICS,
123 TU_PIPELINE_GRAPHICS_LIB,
124 TU_PIPELINE_COMPUTE,
125 };
126
127 struct tu_pipeline
128 {
129 struct vk_object_base base;
130 enum tu_pipeline_type type;
131
132 struct tu_cs cs;
133 struct tu_suballoc_bo bo;
134
135 VkShaderStageFlags active_stages;
136 uint32_t active_desc_sets;
137
138 /* mask of enabled dynamic states
139 * if BIT(i) is set, pipeline->dynamic_state[i] is used
140 */
141 uint32_t set_state_mask;
142 struct tu_draw_state dynamic_state[TU_DYNAMIC_STATE_COUNT];
143
144 BITSET_DECLARE(static_state_mask, MESA_VK_DYNAMIC_GRAPHICS_STATE_ENUM_MAX);
145
146 struct {
147 bool raster_order_attachment_access;
148 } ds;
149
150 /* Misc. info from the fragment output interface state that is used
151 * elsewhere.
152 */
153 struct {
154 bool raster_order_attachment_access;
155 } output;
156
157 /* In other words - framebuffer fetch support */
158 struct {
159 /* If the pipeline sets SINGLE_PRIM_MODE for sysmem. */
160 bool sysmem_single_prim_mode;
161 struct tu_draw_state state_gmem;
162 } prim_order;
163
164 /* draw states for the pipeline */
165 struct tu_draw_state load_state;
166
167 struct tu_shader *shaders[MESA_SHADER_STAGES];
168
169 struct tu_program_state program;
170
171 struct tu_lrz_blend lrz_blend;
172 struct tu_bandwidth bandwidth;
173
174 void *executables_mem_ctx;
175 /* tu_pipeline_executable */
176 struct util_dynarray executables;
177 };
178
179 struct tu_graphics_lib_pipeline {
180 struct tu_pipeline base;
181
182 VkGraphicsPipelineLibraryFlagsEXT state;
183
184 struct vk_graphics_pipeline_state graphics_state;
185
186 /* For vk_graphics_pipeline_state */
187 void *state_data;
188
189 struct tu_nir_shaders *nir_shaders;
190 struct {
191 nir_shader *nir;
192 struct tu_shader_key key;
193 } shaders[MESA_SHADER_FRAGMENT + 1];
194
195 /* Used to stitch together an overall layout for the final pipeline. */
196 struct tu_descriptor_set_layout *layouts[MAX_SETS];
197 unsigned num_sets;
198 unsigned push_constant_size;
199 bool independent_sets;
200 };
201
202 struct tu_graphics_pipeline {
203 struct tu_pipeline base;
204
205 struct vk_dynamic_graphics_state dynamic_state;
206
207 /* Only used if the sample locations are static but the enable is dynamic.
208 * Otherwise we should be able to precompile the draw state.
209 */
210 struct vk_sample_locations_state sample_locations;
211
212 VkImageAspectFlags feedback_loops;
213 bool feedback_loop_may_involve_textures;
214 };
215
216 struct tu_compute_pipeline {
217 struct tu_pipeline base;
218
219 uint32_t local_size[3];
220 uint32_t instrlen;
221 };
222
223 VK_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, base, VkPipeline,
224 VK_OBJECT_TYPE_PIPELINE)
225
226 #define TU_DECL_PIPELINE_DOWNCAST(pipe_type, pipe_enum) \
227 static inline struct tu_##pipe_type##_pipeline * \
228 tu_pipeline_to_##pipe_type(struct tu_pipeline *pipeline) \
229 { \
230 assert(pipeline->type == pipe_enum); \
231 return (struct tu_##pipe_type##_pipeline *) pipeline; \
232 }
233
234 TU_DECL_PIPELINE_DOWNCAST(graphics, TU_PIPELINE_GRAPHICS)
235 TU_DECL_PIPELINE_DOWNCAST(graphics_lib, TU_PIPELINE_GRAPHICS_LIB)
236 TU_DECL_PIPELINE_DOWNCAST(compute, TU_PIPELINE_COMPUTE)
237
238 VkOffset2D tu_fdm_per_bin_offset(VkExtent2D frag_area, VkRect2D bin);
239
240 template <chip CHIP>
241 uint32_t tu_emit_draw_state(struct tu_cmd_buffer *cmd);
242
243 struct tu_pvtmem_config {
244 uint64_t iova;
245 uint32_t per_fiber_size;
246 uint32_t per_sp_size;
247 bool per_wave;
248 };
249
250 template <chip CHIP>
251 void
252 tu6_emit_xs_config(struct tu_cs *cs,
253 gl_shader_stage stage,
254 const struct ir3_shader_variant *xs);
255
256 template <chip CHIP>
257 void
258 tu6_emit_shared_consts_enable(struct tu_cs *cs, bool shared_consts_enable);
259
260 template <chip CHIP>
261 void
262 tu6_emit_vpc(struct tu_cs *cs,
263 const struct ir3_shader_variant *vs,
264 const struct ir3_shader_variant *hs,
265 const struct ir3_shader_variant *ds,
266 const struct ir3_shader_variant *gs,
267 const struct ir3_shader_variant *fs);
268
269 void
270 tu_fill_render_pass_state(struct vk_render_pass_state *rp,
271 const struct tu_render_pass *pass,
272 const struct tu_subpass *subpass);
273
274 #endif /* TU_PIPELINE_H */
275