1 /**************************************************************************
2 *
3 * Copyright 2003 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #ifndef I915_FPC_H
29 #define I915_FPC_H
30
31 #include "i915_context.h"
32 #include "i915_reg.h"
33
34 #include "pipe/p_shader_tokens.h"
35
36 #include "tgsi/tgsi_parse.h"
37
38 struct nir_shader;
39
40 #define I915_PROGRAM_SIZE 192
41
42 /**
43 * Program translation state
44 */
45 struct i915_fp_compile {
46 struct i915_fragment_shader *shader; /* the shader we're compiling */
47
48 bool used_constants[I915_MAX_CONSTANT];
49
50 /** maps TGSI immediate index to constant slot */
51 uint32_t num_immediates;
52 uint32_t immediates_map[I915_MAX_CONSTANT];
53 float immediates[I915_MAX_CONSTANT][4];
54
55 bool first_instruction;
56
57 uint32_t declarations[I915_PROGRAM_SIZE];
58 uint32_t program[I915_PROGRAM_SIZE];
59
60 uint32_t *csr; /**< Cursor, points into program. */
61
62 uint32_t *decl; /**< Cursor, points into declarations. */
63
64 uint32_t decl_s; /**< flags for which s regs need to be decl'd */
65 uint32_t decl_t; /**< flags for which t regs need to be decl'd */
66
67 uint32_t temp_flag; /**< Tracks temporary regs which are in use */
68 uint32_t utemp_flag; /**< Tracks TYPE_U temporary regs which are in use */
69
70 uint32_t register_phases[I915_MAX_TEMPORARY];
71 uint32_t nr_tex_indirect;
72 uint32_t nr_tex_insn;
73 uint32_t nr_alu_insn;
74 uint32_t nr_decl_insn;
75
76 bool log_program_errors;
77 char *error;
78 };
79
80 /* Having zero and one in here makes the definition of swizzle a lot
81 * easier.
82 */
83 #define UREG_TYPE_SHIFT 29
84 #define UREG_NR_SHIFT 24
85 #define UREG_CHANNEL_X_NEGATE_SHIFT 23
86 #define UREG_CHANNEL_X_SHIFT 20
87 #define UREG_CHANNEL_Y_NEGATE_SHIFT 19
88 #define UREG_CHANNEL_Y_SHIFT 16
89 #define UREG_CHANNEL_Z_NEGATE_SHIFT 15
90 #define UREG_CHANNEL_Z_SHIFT 12
91 #define UREG_CHANNEL_W_NEGATE_SHIFT 11
92 #define UREG_CHANNEL_W_SHIFT 8
93 #define UREG_CHANNEL_ZERO_NEGATE_MBZ 5
94 #define UREG_CHANNEL_ZERO_SHIFT 4
95 #define UREG_CHANNEL_ONE_NEGATE_MBZ 1
96 #define UREG_CHANNEL_ONE_SHIFT 0
97
98 #define UREG_BAD 0xffffffff /* not a valid ureg */
99
100 #define X SRC_X
101 #define Y SRC_Y
102 #define Z SRC_Z
103 #define W SRC_W
104 #define ZERO SRC_ZERO
105 #define ONE SRC_ONE
106
107 /* Construct a ureg:
108 */
109 #define UREG(type, nr) \
110 (((type) << UREG_TYPE_SHIFT) | ((nr) << UREG_NR_SHIFT) | \
111 (X << UREG_CHANNEL_X_SHIFT) | (Y << UREG_CHANNEL_Y_SHIFT) | \
112 (Z << UREG_CHANNEL_Z_SHIFT) | (W << UREG_CHANNEL_W_SHIFT) | \
113 (ZERO << UREG_CHANNEL_ZERO_SHIFT) | (ONE << UREG_CHANNEL_ONE_SHIFT))
114
115 #define GET_CHANNEL_SRC(reg, channel) ((reg << (channel * 4)) & (0xf << 20))
116 #define CHANNEL_SRC(src, channel) (src >> (channel * 4))
117
118 #define GET_UREG_TYPE(reg) (((reg) >> UREG_TYPE_SHIFT) & REG_TYPE_MASK)
119 #define GET_UREG_NR(reg) (((reg) >> UREG_NR_SHIFT) & REG_NR_MASK)
120
121 #define UREG_XYZW_CHANNEL_MASK 0x00ffff00
122
123 /* One neat thing about the UREG representation:
124 */
125 static inline int
swizzle(int reg,uint32_t x,uint32_t y,uint32_t z,uint32_t w)126 swizzle(int reg, uint32_t x, uint32_t y, uint32_t z, uint32_t w)
127 {
128 assert(x <= SRC_ONE);
129 assert(y <= SRC_ONE);
130 assert(z <= SRC_ONE);
131 assert(w <= SRC_ONE);
132 return ((reg & ~UREG_XYZW_CHANNEL_MASK) |
133 CHANNEL_SRC(GET_CHANNEL_SRC(reg, x), 0) |
134 CHANNEL_SRC(GET_CHANNEL_SRC(reg, y), 1) |
135 CHANNEL_SRC(GET_CHANNEL_SRC(reg, z), 2) |
136 CHANNEL_SRC(GET_CHANNEL_SRC(reg, w), 3));
137 }
138
139 #define A0_DEST(reg) (((reg)&UREG_TYPE_NR_MASK) >> UREG_A0_DEST_SHIFT_LEFT)
140 #define D0_DEST(reg) (((reg)&UREG_TYPE_NR_MASK) >> UREG_A0_DEST_SHIFT_LEFT)
141 #define T0_DEST(reg) (((reg)&UREG_TYPE_NR_MASK) >> UREG_A0_DEST_SHIFT_LEFT)
142 #define A0_SRC0(reg) (((reg)&UREG_MASK) >> UREG_A0_SRC0_SHIFT_LEFT)
143 #define A1_SRC0(reg) (((reg)&UREG_MASK) << UREG_A1_SRC0_SHIFT_RIGHT)
144 #define A1_SRC1(reg) (((reg)&UREG_MASK) >> UREG_A1_SRC1_SHIFT_LEFT)
145 #define A2_SRC1(reg) (((reg)&UREG_MASK) << UREG_A2_SRC1_SHIFT_RIGHT)
146 #define A2_SRC2(reg) (((reg)&UREG_MASK) >> UREG_A2_SRC2_SHIFT_LEFT)
147
148 /* These are special, and don't have swizzle/negate bits.
149 */
150 #define T0_SAMPLER(reg) (GET_UREG_NR(reg) << T0_SAMPLER_NR_SHIFT)
151 #define T1_ADDRESS_REG(reg) \
152 ((GET_UREG_NR(reg) << T1_ADDRESS_REG_NR_SHIFT) | \
153 (GET_UREG_TYPE(reg) << T1_ADDRESS_REG_TYPE_SHIFT))
154
155 /* Macros for translating UREG's into the various register fields used
156 * by the I915 programmable unit.
157 */
158 #define UREG_A0_DEST_SHIFT_LEFT (UREG_TYPE_SHIFT - A0_DEST_TYPE_SHIFT)
159 #define UREG_A0_SRC0_SHIFT_LEFT (UREG_TYPE_SHIFT - A0_SRC0_TYPE_SHIFT)
160 #define UREG_A1_SRC0_SHIFT_RIGHT \
161 (A1_SRC0_CHANNEL_W_SHIFT - UREG_CHANNEL_W_SHIFT)
162 #define UREG_A1_SRC1_SHIFT_LEFT (UREG_TYPE_SHIFT - A1_SRC1_TYPE_SHIFT)
163 #define UREG_A2_SRC1_SHIFT_RIGHT \
164 (A2_SRC1_CHANNEL_W_SHIFT - UREG_CHANNEL_W_SHIFT)
165 #define UREG_A2_SRC2_SHIFT_LEFT (UREG_TYPE_SHIFT - A2_SRC2_TYPE_SHIFT)
166
167 #define UREG_MASK 0xffffff00
168 #define UREG_TYPE_NR_MASK \
169 ((REG_TYPE_MASK << UREG_TYPE_SHIFT) | (REG_NR_MASK << UREG_NR_SHIFT))
170
171 /***********************************************************************
172 * Public interface for the compiler
173 */
174 extern void i915_translate_fragment_program(struct i915_context *i915,
175 struct i915_fragment_shader *fs);
176
177 extern uint32_t i915_get_temp(struct i915_fp_compile *p);
178 extern uint32_t i915_get_utemp(struct i915_fp_compile *p);
179 extern void i915_release_utemps(struct i915_fp_compile *p);
180
181 extern uint32_t i915_emit_texld(struct i915_fp_compile *p, uint32_t dest,
182 uint32_t destmask, uint32_t sampler,
183 uint32_t coord, uint32_t op,
184 uint32_t coord_mask);
185
186 extern uint32_t i915_emit_arith(struct i915_fp_compile *p, uint32_t op,
187 uint32_t dest, uint32_t mask, uint32_t saturate,
188 uint32_t src0, uint32_t src1, uint32_t src2);
189
190 extern uint32_t i915_emit_decl(struct i915_fp_compile *p, uint32_t type,
191 uint32_t nr, uint32_t d0_flags);
192
193 extern uint32_t i915_emit_const1f(struct i915_fp_compile *p, float c0);
194
195 extern uint32_t i915_emit_const2f(struct i915_fp_compile *p, float c0,
196 float c1);
197
198 extern uint32_t i915_emit_const4fv(struct i915_fp_compile *p, const float *c);
199
200 extern uint32_t i915_emit_const4f(struct i915_fp_compile *p, float c0, float c1,
201 float c2, float c3);
202
203 /*======================================================================
204 * i915_fpc_translate.c
205 */
206
207 extern void i915_program_error(struct i915_fp_compile *p, const char *msg, ...);
208
209 /*======================================================================
210 * i915_fpc_optimize.c
211 */
212
213 struct i915_src_register {
214 unsigned File : 4; /* TGSI_FILE_ */
215 unsigned Indirect : 1; /* BOOL */
216 unsigned Dimension : 1; /* BOOL */
217 int Index : 16; /* SINT */
218 unsigned SwizzleX : 3; /* TGSI_SWIZZLE_ */
219 unsigned SwizzleY : 3; /* TGSI_SWIZZLE_ */
220 unsigned SwizzleZ : 3; /* TGSI_SWIZZLE_ */
221 unsigned SwizzleW : 3; /* TGSI_SWIZZLE_ */
222 unsigned Absolute : 1; /* BOOL */
223 unsigned Negate : 1; /* BOOL */
224 };
225
226 /* Additional swizzle supported in i915 */
227 #define TGSI_SWIZZLE_ZERO 4
228 #define TGSI_SWIZZLE_ONE 5
229
230 struct i915_dst_register {
231 unsigned File : 4; /* TGSI_FILE_ */
232 unsigned WriteMask : 4; /* TGSI_WRITEMASK_ */
233 unsigned Indirect : 1; /* BOOL */
234 unsigned Dimension : 1; /* BOOL */
235 int Index : 16; /* SINT */
236 unsigned Padding : 6;
237 };
238
239 struct i915_full_dst_register {
240 struct i915_dst_register Register;
241 /*
242 struct tgsi_ind_register Indirect;
243 struct tgsi_dimension Dimension;
244 struct tgsi_ind_register DimIndirect;
245 */
246 };
247
248 struct i915_full_src_register {
249 struct i915_src_register Register;
250 /*
251 struct tgsi_ind_register Indirect;
252 struct tgsi_dimension Dimension;
253 struct tgsi_ind_register DimIndirect;
254 */
255 };
256
257 struct i915_full_instruction {
258 struct tgsi_instruction Instruction;
259 /*
260 struct tgsi_instruction_label Label;
261 */
262 struct tgsi_instruction_texture Texture;
263 struct i915_full_dst_register Dst[1];
264 struct i915_full_src_register Src[3];
265 };
266
267 union i915_full_token {
268 struct tgsi_token Token;
269 struct tgsi_full_declaration FullDeclaration;
270 struct tgsi_full_immediate FullImmediate;
271 struct i915_full_instruction FullInstruction;
272 struct tgsi_full_property FullProperty;
273 };
274
275 struct i915_token_list {
276 union i915_full_token *Tokens;
277 unsigned NumTokens;
278 };
279
280 char *i915_test_fragment_shader_compile(struct pipe_screen *screen,
281 struct nir_shader *s);
282
283 extern struct i915_token_list *i915_optimize(const struct tgsi_token *tokens);
284
285 extern void i915_optimize_free(struct i915_token_list *tokens);
286
287 extern uint32_t i915_coord_mask(enum tgsi_opcode opcode,
288 enum tgsi_texture_type tex);
289
290 #endif
291