1 /*
2 * Copyright 2009 Nicolai Hähnle <nhaehnle@gmail.com>
3 * SPDX-License-Identifier: MIT
4 */
5
6 #include "radeon_compiler.h"
7
8 #include <stdio.h>
9
10 #include "r300_fragprog.h"
11 #include "r300_fragprog_swizzle.h"
12 #include "r500_fragprog.h"
13 #include "radeon_compiler_util.h"
14 #include "radeon_dataflow.h"
15 #include "radeon_list.h"
16 #include "radeon_program_alu.h"
17 #include "radeon_program_tex.h"
18 #include "radeon_remove_constants.h"
19 #include "radeon_rename_regs.h"
20 #include "radeon_variable.h"
21
22 static void
rc_rewrite_depth_out(struct radeon_compiler * cc,void * user)23 rc_rewrite_depth_out(struct radeon_compiler *cc, void *user)
24 {
25 struct r300_fragment_program_compiler *c = (struct r300_fragment_program_compiler *)cc;
26 struct rc_instruction *rci;
27
28 for (rci = c->Base.Program.Instructions.Next; rci != &c->Base.Program.Instructions;
29 rci = rci->Next) {
30 struct rc_sub_instruction *inst = &rci->U.I;
31 unsigned i;
32 const struct rc_opcode_info *info = rc_get_opcode_info(inst->Opcode);
33
34 if (inst->DstReg.File != RC_FILE_OUTPUT || inst->DstReg.Index != c->OutputDepth)
35 continue;
36
37 if (inst->DstReg.WriteMask & RC_MASK_Z) {
38 inst->DstReg.WriteMask = RC_MASK_W;
39 } else {
40 inst->DstReg.WriteMask = 0;
41 continue;
42 }
43
44 if (!info->IsComponentwise) {
45 continue;
46 }
47
48 for (i = 0; i < info->NumSrcRegs; i++) {
49 inst->SrcReg[i] = lmul_swizzle(RC_SWIZZLE_ZZZZ, inst->SrcReg[i]);
50 }
51 }
52 }
53
54 /**
55 * This function will try to convert rgb instructions into alpha instructions
56 * and vice versa. While this is already attempted during the pair scheduling,
57 * it is much simpler to do it before pair conversion, so do it here at least for
58 * the simple cases.
59 *
60 * Currently only math opcodes writing to rgb (and with no friends) are
61 * converted to alpha.
62 *
63 * This function assumes all the instructions are still of type
64 * RC_INSTRUCTION_NORMAL, the conversion is much simpler.
65 *
66 * Beware that this needs to be also called before doing presubtract, because
67 * rc_get_variables can't get properly readers for normal instructions if presubtract
68 * is present (it works fine for pair instructions).
69 */
70 static void
rc_convert_rgb_alpha(struct radeon_compiler * c,void * user)71 rc_convert_rgb_alpha(struct radeon_compiler *c, void *user)
72 {
73 struct rc_list *variables;
74 struct rc_list *var_ptr;
75
76 variables = rc_get_variables(c);
77
78 for (var_ptr = variables; var_ptr; var_ptr = var_ptr->Next) {
79 struct rc_variable *var = var_ptr->Item;
80
81 if (var->Inst->U.I.DstReg.File != RC_FILE_TEMPORARY) {
82 continue;
83 }
84
85 /* Only rewrite scalar opcodes that are used separately for now. */
86 if (var->Friend)
87 continue;
88
89 const struct rc_opcode_info *opcode = rc_get_opcode_info(var->Inst->U.I.Opcode);
90 if (opcode->IsStandardScalar && var->Dst.WriteMask != RC_MASK_W) {
91 unsigned index = rc_find_free_temporary(c);
92 rc_variable_change_dst(var, index, RC_MASK_W);
93 }
94 }
95 }
96
97 void
r3xx_compile_fragment_program(struct r300_fragment_program_compiler * c)98 r3xx_compile_fragment_program(struct r300_fragment_program_compiler *c)
99 {
100 int is_r500 = c->Base.is_r500;
101 int opt = !c->Base.disable_optimizations;
102 int alpha2one = c->state.alpha_to_one;
103 bool dbg = c->Base.Debug & RC_DBG_LOG;
104
105 /* Lists of instruction transformations. */
106 struct radeon_program_transformation force_alpha_to_one[] = {{&rc_force_output_alpha_to_one, c},
107 {NULL, NULL}};
108
109 struct radeon_program_transformation rewrite_tex[] = {{&radeonTransformTEX, c}, {NULL, NULL}};
110
111 struct radeon_program_transformation native_rewrite_r500[] = {{&radeonTransformALU, NULL},
112 {&radeonTransformDeriv, NULL},
113 {NULL, NULL}};
114
115 struct radeon_program_transformation native_rewrite_r300[] = {{&radeonTransformALU, NULL},
116 {&radeonStubDeriv, NULL},
117 {NULL, NULL}};
118
119 struct radeon_program_transformation opt_presubtract[] = {{&rc_opt_presubtract, NULL},
120 {NULL, NULL}};
121
122 /* List of compiler passes. */
123 /* clang-format off */
124 struct radeon_compiler_pass fs_list[] = {
125 /* NAME DUMP PREDICATE FUNCTION PARAM */
126 {"rewrite depth out", 1, 1, rc_rewrite_depth_out, NULL},
127 {"force alpha to one", 1, alpha2one, rc_local_transform, force_alpha_to_one},
128 {"transform TEX", 1, 1, rc_local_transform, rewrite_tex},
129 {"transform IF", 1, is_r500, r500_transform_IF, NULL},
130 {"native rewrite", 1, is_r500, rc_local_transform, native_rewrite_r500},
131 {"native rewrite", 1, !is_r500, rc_local_transform, native_rewrite_r300},
132 {"deadcode", 1, opt, rc_dataflow_deadcode, NULL},
133 {"convert rgb<->alpha", 1, opt, rc_convert_rgb_alpha, NULL},
134 {"register rename", 1, !is_r500 || opt, rc_rename_regs, NULL},
135 {"dataflow optimize", 1, opt, rc_optimize, NULL},
136 {"inline literals", 1, is_r500 && opt, rc_inline_literals, NULL},
137 {"dataflow swizzles", 1, 1, rc_dataflow_swizzles, NULL},
138 {"dead constants", 1, 1, rc_remove_unused_constants, &c->code->constants_remap_table},
139 {"dataflow presubtract", 1, opt, rc_local_transform, opt_presubtract},
140 {"pair translate", 1, 1, rc_pair_translate, NULL},
141 {"pair scheduling", 1, 1, rc_pair_schedule, &opt},
142 {"dead sources", 1, 1, rc_pair_remove_dead_sources, NULL},
143 {"register allocation", 1, 1, rc_pair_regalloc, &opt},
144 {"final code validation", 0, 1, rc_validate_final_shader, NULL},
145 {"machine code generation", 0, is_r500, r500BuildFragmentProgramHwCode, NULL},
146 {"machine code generation", 0, !is_r500, r300BuildFragmentProgramHwCode, NULL},
147 {"dump machine code", 0, is_r500 && dbg, r500FragmentProgramDump, NULL},
148 {"dump machine code", 0, !is_r500 && dbg, r300FragmentProgramDump, NULL},
149 {NULL, 0, 0, NULL, NULL}};
150 /* clang-format on */
151
152 c->Base.type = RC_FRAGMENT_PROGRAM;
153 c->Base.SwizzleCaps = c->Base.is_r500 ? &r500_swizzle_caps : &r300_swizzle_caps;
154
155 rc_run_compiler(&c->Base, fs_list);
156
157 rc_constants_copy(&c->code->constants, &c->Base.Program.Constants);
158 }
159