1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
4 * SPDX-License-Identifier: MIT
5 */
6
7 #include "compiler/nir/nir.h"
8 #include "util/format/u_format.h"
9 #include "util/format/u_format_s3tc.h"
10 #include "util/u_screen.h"
11 #include "util/u_memory.h"
12 #include "util/hex.h"
13 #include "util/os_time.h"
14 #include "util/xmlconfig.h"
15 #include "vl/vl_decoder.h"
16 #include "vl/vl_video_buffer.h"
17
18 #include "r300_context.h"
19 #include "r300_texture.h"
20 #include "r300_screen_buffer.h"
21 #include "r300_state_inlines.h"
22 #include "r300_public.h"
23 #include "compiler/r300_nir.h"
24
25 #include "draw/draw_context.h"
26
27 /* Return the identifier behind whom the brave coders responsible for this
28 * amalgamation of code, sweat, and duct tape, routinely obscure their names.
29 *
30 * ...I should have just put "Corbin Simpson", but I'm not that cool.
31 *
32 * (Or egotistical. Yet.) */
r300_get_vendor(struct pipe_screen * pscreen)33 static const char* r300_get_vendor(struct pipe_screen* pscreen)
34 {
35 return "Mesa";
36 }
37
r300_get_device_vendor(struct pipe_screen * pscreen)38 static const char* r300_get_device_vendor(struct pipe_screen* pscreen)
39 {
40 return "ATI";
41 }
42
43 static const char* chip_families[] = {
44 "unknown",
45 "ATI R300",
46 "ATI R350",
47 "ATI RV350",
48 "ATI RV370",
49 "ATI RV380",
50 "ATI RS400",
51 "ATI RC410",
52 "ATI RS480",
53 "ATI R420",
54 "ATI R423",
55 "ATI R430",
56 "ATI R480",
57 "ATI R481",
58 "ATI RV410",
59 "ATI RS600",
60 "ATI RS690",
61 "ATI RS740",
62 "ATI RV515",
63 "ATI R520",
64 "ATI RV530",
65 "ATI R580",
66 "ATI RV560",
67 "ATI RV570"
68 };
69
r300_get_family_name(struct r300_screen * r300screen)70 static const char* r300_get_family_name(struct r300_screen* r300screen)
71 {
72 return chip_families[r300screen->caps.family];
73 }
74
r300_get_name(struct pipe_screen * pscreen)75 static const char* r300_get_name(struct pipe_screen* pscreen)
76 {
77 struct r300_screen* r300screen = r300_screen(pscreen);
78
79 return r300_get_family_name(r300screen);
80 }
81
r300_disk_cache_create(struct r300_screen * r300screen)82 static void r300_disk_cache_create(struct r300_screen* r300screen)
83 {
84 struct mesa_sha1 ctx;
85 unsigned char sha1[20];
86 char cache_id[20 * 2 + 1];
87
88 _mesa_sha1_init(&ctx);
89 if (!disk_cache_get_function_identifier(r300_disk_cache_create,
90 &ctx))
91 return;
92
93 _mesa_sha1_final(&ctx, sha1);
94 mesa_bytes_to_hex(cache_id, sha1, 20);
95
96 r300screen->disk_shader_cache =
97 disk_cache_create(r300_get_family_name(r300screen),
98 cache_id,
99 r300screen->debug);
100 }
101
r300_get_disk_shader_cache(struct pipe_screen * pscreen)102 static struct disk_cache* r300_get_disk_shader_cache(struct pipe_screen* pscreen)
103 {
104 struct r300_screen* r300screen = r300_screen(pscreen);
105 return r300screen->disk_shader_cache;
106 }
107
r300_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)108 static int r300_get_shader_param(struct pipe_screen *pscreen,
109 enum pipe_shader_type shader,
110 enum pipe_shader_cap param)
111 {
112 struct r300_screen* r300screen = r300_screen(pscreen);
113 bool is_r400 = r300screen->caps.is_r400;
114 bool is_r500 = r300screen->caps.is_r500;
115
116 switch (param) {
117 case PIPE_SHADER_CAP_SUPPORTED_IRS:
118 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
119 default:
120 break;
121 }
122
123 switch (shader) {
124 case PIPE_SHADER_FRAGMENT:
125 switch (param)
126 {
127 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
128 return is_r500 || is_r400 ? 512 : 96;
129 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
130 return is_r500 || is_r400 ? 512 : 64;
131 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
132 return is_r500 || is_r400 ? 512 : 32;
133 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
134 return is_r500 ? 511 : 4;
135 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
136 return is_r500 ? 64 : 0; /* Actually unlimited on r500. */
137 /* Fragment shader limits. */
138 case PIPE_SHADER_CAP_MAX_INPUTS:
139 /* 2 colors + 8 texcoords are always supported
140 * (minus fog and wpos).
141 *
142 * R500 has the ability to turn 3rd and 4th color into
143 * additional texcoords but there is no two-sided color
144 * selection then. However the facing bit can be used instead. */
145 return 10;
146 case PIPE_SHADER_CAP_MAX_OUTPUTS:
147 return 4;
148 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
149 return (is_r500 ? 256 : 32) * sizeof(float[4]);
150 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
151 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
152 return 1;
153 case PIPE_SHADER_CAP_MAX_TEMPS:
154 return is_r500 ? 128 : is_r400 ? 64 : 32;
155 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
156 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
157 return r300screen->caps.num_tex_units;
158 case PIPE_SHADER_CAP_CONT_SUPPORTED:
159 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
160 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
161 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
162 case PIPE_SHADER_CAP_SUBROUTINES:
163 case PIPE_SHADER_CAP_INTEGERS:
164 case PIPE_SHADER_CAP_INT64_ATOMICS:
165 case PIPE_SHADER_CAP_FP16:
166 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
167 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
168 case PIPE_SHADER_CAP_INT16:
169 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
170 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
171 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
172 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
173 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
174 return 0;
175 default:
176 break;
177 }
178 break;
179 case PIPE_SHADER_VERTEX:
180 switch (param)
181 {
182 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
183 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
184 case PIPE_SHADER_CAP_SUBROUTINES:
185 return 0;
186 default:;
187 }
188
189 if (!r300screen->caps.has_tcl) {
190 switch (param) {
191 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
192 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
193 return 0;
194
195 /* mesa/st requires that this cap is the same across stages, and the FS
196 * can't do ints.
197 */
198 case PIPE_SHADER_CAP_INTEGERS:
199 return 0;
200
201 /* Even if gallivm NIR can do this, we call nir_to_tgsi manually and
202 * TGSI can't.
203 */
204 case PIPE_SHADER_CAP_INT16:
205 case PIPE_SHADER_CAP_FP16:
206 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
207 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
208 return 0;
209
210 /* While draw could normally handle this for the VS, the NIR lowering
211 * to regs can't handle our non-native-integers, so we have to lower to
212 * if ladders.
213 */
214 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
215 return 0;
216 default:
217 return draw_get_shader_param(shader, param);
218 }
219 }
220
221 switch (param)
222 {
223 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
224 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
225 return is_r500 ? 1024 : 256;
226 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
227 return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */
228 case PIPE_SHADER_CAP_MAX_INPUTS:
229 return 16;
230 case PIPE_SHADER_CAP_MAX_OUTPUTS:
231 return 10;
232 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
233 return 256 * sizeof(float[4]);
234 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
235 return 1;
236 case PIPE_SHADER_CAP_MAX_TEMPS:
237 return 32;
238 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
239 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
240 return 1;
241 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
242 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
243 case PIPE_SHADER_CAP_CONT_SUPPORTED:
244 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
245 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
246 case PIPE_SHADER_CAP_SUBROUTINES:
247 case PIPE_SHADER_CAP_INTEGERS:
248 case PIPE_SHADER_CAP_FP16:
249 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
250 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
251 case PIPE_SHADER_CAP_INT16:
252 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
253 case PIPE_SHADER_CAP_INT64_ATOMICS:
254 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
255 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
256 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
257 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
258 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
259 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
260 return 0;
261 default:
262 break;
263 }
264 break;
265 default:
266 ; /* nothing */
267 }
268 return 0;
269 }
270
r300_get_video_param(struct pipe_screen * screen,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint,enum pipe_video_cap param)271 static int r300_get_video_param(struct pipe_screen *screen,
272 enum pipe_video_profile profile,
273 enum pipe_video_entrypoint entrypoint,
274 enum pipe_video_cap param)
275 {
276 switch (param) {
277 case PIPE_VIDEO_CAP_SUPPORTED:
278 return vl_profile_supported(screen, profile, entrypoint);
279 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
280 return 0;
281 case PIPE_VIDEO_CAP_MAX_WIDTH:
282 case PIPE_VIDEO_CAP_MAX_HEIGHT:
283 return vl_video_buffer_max_size(screen);
284 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
285 return PIPE_FORMAT_NV12;
286 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
287 return false;
288 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
289 return false;
290 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
291 return true;
292 case PIPE_VIDEO_CAP_MAX_LEVEL:
293 return vl_level_supported(screen, profile);
294 default:
295 return 0;
296 }
297 }
298
299 #define COMMON_NIR_OPTIONS \
300 .fdot_replicates = true, \
301 .fuse_ffma32 = true, \
302 .fuse_ffma64 = true, \
303 .lower_bitops = true, \
304 .lower_extract_byte = true, \
305 .lower_extract_word = true, \
306 .lower_fceil = true, \
307 .lower_fdiv = true, \
308 .lower_fdph = true, \
309 .lower_ffloor = true, \
310 .lower_flrp32 = true, \
311 .lower_flrp64 = true, \
312 .lower_fmod = true, \
313 .lower_fsign = true, \
314 .lower_fsqrt = true, \
315 .lower_ftrunc = true, \
316 .lower_insert_byte = true, \
317 .lower_insert_word = true, \
318 .lower_uniforms_to_ubo = true, \
319 .lower_vector_cmp = true, \
320 .no_integers = true
321
322 static const nir_shader_compiler_options r500_vs_compiler_options = {
323 COMMON_NIR_OPTIONS,
324 .has_fused_comp_and_csel = true,
325
326 /* Have HW loops support and 1024 max instr count, but don't unroll *too*
327 * hard.
328 */
329 .max_unroll_iterations = 29,
330 };
331
332 static const nir_shader_compiler_options r500_fs_compiler_options = {
333 COMMON_NIR_OPTIONS,
334 .lower_fpow = true, /* POW is only in the VS */
335 .has_fused_comp_and_csel = true,
336
337 /* Have HW loops support and 512 max instr count, but don't unroll *too*
338 * hard.
339 */
340 .max_unroll_iterations = 32,
341 };
342
343 static const nir_shader_compiler_options r300_vs_compiler_options = {
344 COMMON_NIR_OPTIONS,
345 .lower_fsat = true, /* No fsat in pre-r500 VS */
346 .lower_sincos = true,
347
348 /* Note: has HW loops support, but only 256 ALU instructions. */
349 .max_unroll_iterations = 32,
350 };
351
352 static const nir_shader_compiler_options r400_vs_compiler_options = {
353 COMMON_NIR_OPTIONS,
354 .lower_fsat = true, /* No fsat in pre-r500 VS */
355
356 /* Note: has HW loops support, but only 256 ALU instructions. */
357 .max_unroll_iterations = 32,
358 };
359
360 static const nir_shader_compiler_options r300_fs_compiler_options = {
361 COMMON_NIR_OPTIONS,
362 .lower_fpow = true, /* POW is only in the VS */
363 .lower_sincos = true,
364 .has_fused_comp_and_csel = true,
365
366 /* No HW loops support, so set it equal to ALU instr max */
367 .max_unroll_iterations = 64,
368 };
369
370 static const nir_shader_compiler_options gallivm_compiler_options = {
371 COMMON_NIR_OPTIONS,
372 .has_fused_comp_and_csel = true,
373 .max_unroll_iterations = 32,
374
375 .support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
376 .support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
377 };
378
379 static const void *
r300_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)380 r300_get_compiler_options(struct pipe_screen *pscreen,
381 enum pipe_shader_ir ir,
382 enum pipe_shader_type shader)
383 {
384 struct r300_screen* r300screen = r300_screen(pscreen);
385
386 assert(ir == PIPE_SHADER_IR_NIR);
387
388 if (shader == PIPE_SHADER_VERTEX && !r300screen->caps.has_tcl) {
389 return &gallivm_compiler_options;
390 } else if (r300screen->caps.is_r500) {
391 if (shader == PIPE_SHADER_VERTEX)
392 return &r500_vs_compiler_options;
393 else
394 return &r500_fs_compiler_options;
395 } else {
396 if (shader == PIPE_SHADER_VERTEX) {
397 if (r300screen->caps.is_r400)
398 return &r400_vs_compiler_options;
399
400 return &r300_vs_compiler_options;
401 } else {
402 return &r300_fs_compiler_options;
403 }
404 }
405 }
406
407 /**
408 * Whether the format matches:
409 * PIPE_FORMAT_?10?10?10?2_UNORM
410 */
411 static inline bool
util_format_is_rgba1010102_variant(const struct util_format_description * desc)412 util_format_is_rgba1010102_variant(const struct util_format_description *desc)
413 {
414 static const unsigned size[4] = {10, 10, 10, 2};
415 unsigned chan;
416
417 if (desc->block.width != 1 ||
418 desc->block.height != 1 ||
419 desc->block.bits != 32)
420 return false;
421
422 for (chan = 0; chan < 4; ++chan) {
423 if(desc->channel[chan].type != UTIL_FORMAT_TYPE_UNSIGNED &&
424 desc->channel[chan].type != UTIL_FORMAT_TYPE_VOID)
425 return false;
426 if (desc->channel[chan].size != size[chan])
427 return false;
428 }
429
430 return true;
431 }
432
r300_is_blending_supported(struct r300_screen * rscreen,enum pipe_format format)433 static bool r300_is_blending_supported(struct r300_screen *rscreen,
434 enum pipe_format format)
435 {
436 int c;
437 const struct util_format_description *desc =
438 util_format_description(format);
439
440 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
441 return false;
442
443 c = util_format_get_first_non_void_channel(format);
444
445 /* RGBA16F */
446 if (rscreen->caps.is_r500 &&
447 desc->nr_channels == 4 &&
448 desc->channel[c].size == 16 &&
449 desc->channel[c].type == UTIL_FORMAT_TYPE_FLOAT)
450 return true;
451
452 if (desc->channel[c].normalized &&
453 desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED &&
454 desc->channel[c].size >= 4 &&
455 desc->channel[c].size <= 10) {
456 /* RGB10_A2, RGBA8, RGB5_A1, RGBA4, RGB565 */
457 if (desc->nr_channels >= 3)
458 return true;
459
460 if (format == PIPE_FORMAT_R8G8_UNORM)
461 return true;
462
463 /* R8, I8, L8, A8 */
464 if (desc->nr_channels == 1)
465 return true;
466 }
467
468 return false;
469 }
470
r300_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned usage)471 static bool r300_is_format_supported(struct pipe_screen* screen,
472 enum pipe_format format,
473 enum pipe_texture_target target,
474 unsigned sample_count,
475 unsigned storage_sample_count,
476 unsigned usage)
477 {
478 uint32_t retval = 0;
479 bool is_r500 = r300_screen(screen)->caps.is_r500;
480 bool is_r400 = r300_screen(screen)->caps.is_r400;
481 bool is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
482 format == PIPE_FORMAT_R10G10B10X2_SNORM ||
483 format == PIPE_FORMAT_B10G10R10A2_UNORM ||
484 format == PIPE_FORMAT_B10G10R10X2_UNORM ||
485 format == PIPE_FORMAT_R10SG10SB10SA2U_NORM;
486 bool is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM ||
487 format == PIPE_FORMAT_RGTC1_SNORM ||
488 format == PIPE_FORMAT_LATC1_UNORM ||
489 format == PIPE_FORMAT_LATC1_SNORM;
490 bool is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM ||
491 format == PIPE_FORMAT_RGTC2_SNORM ||
492 format == PIPE_FORMAT_LATC2_UNORM ||
493 format == PIPE_FORMAT_LATC2_SNORM;
494 bool is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
495 format == PIPE_FORMAT_R16G16_FLOAT ||
496 format == PIPE_FORMAT_R16G16B16_FLOAT ||
497 format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
498 format == PIPE_FORMAT_R16G16B16X16_FLOAT;
499 const struct util_format_description *desc;
500
501 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
502 return false;
503
504 /* Check multisampling support. */
505 switch (sample_count) {
506 case 0:
507 case 1:
508 break;
509 case 2:
510 case 4:
511 case 6:
512 /* No texturing and scanout. */
513 if (usage & (PIPE_BIND_SAMPLER_VIEW |
514 PIPE_BIND_DISPLAY_TARGET |
515 PIPE_BIND_SCANOUT)) {
516 return false;
517 }
518
519 desc = util_format_description(format);
520
521 if (is_r500) {
522 /* Only allow depth/stencil, RGBA8, RGBA1010102, RGBA16F. */
523 if (!util_format_is_depth_or_stencil(format) &&
524 !util_format_is_rgba8_variant(desc) &&
525 !util_format_is_rgba1010102_variant(desc) &&
526 format != PIPE_FORMAT_R16G16B16A16_FLOAT &&
527 format != PIPE_FORMAT_R16G16B16X16_FLOAT) {
528 return false;
529 }
530 } else {
531 /* Only allow depth/stencil, RGBA8. */
532 if (!util_format_is_depth_or_stencil(format) &&
533 !util_format_is_rgba8_variant(desc)) {
534 return false;
535 }
536 }
537 break;
538 default:
539 return false;
540 }
541
542 /* Check sampler format support. */
543 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
544 /* these two are broken for an unknown reason */
545 format != PIPE_FORMAT_R8G8B8X8_SNORM &&
546 format != PIPE_FORMAT_R16G16B16X16_SNORM &&
547 /* ATI1N is r5xx-only. */
548 (is_r500 || !is_ati1n) &&
549 /* ATI2N is supported on r4xx-r5xx. However state tracker can't handle
550 * fallbacks for ATI1N only, so if we enable ATI2N, we will crash for ATI1N.
551 * Therefore disable both on r400 for now. Additionally, some online source
552 * claim r300 can also do ATI2N.
553 */
554 (is_r500 || !is_ati2n) &&
555 r300_is_sampler_format_supported(format)) {
556 retval |= PIPE_BIND_SAMPLER_VIEW;
557 }
558
559 /* Check colorbuffer format support. */
560 if ((usage & (PIPE_BIND_RENDER_TARGET |
561 PIPE_BIND_DISPLAY_TARGET |
562 PIPE_BIND_SCANOUT |
563 PIPE_BIND_SHARED |
564 PIPE_BIND_BLENDABLE)) &&
565 /* 2101010 cannot be rendered to on non-r5xx. */
566 (!is_color2101010 || is_r500) &&
567 r300_is_colorbuffer_format_supported(format)) {
568 retval |= usage &
569 (PIPE_BIND_RENDER_TARGET |
570 PIPE_BIND_DISPLAY_TARGET |
571 PIPE_BIND_SCANOUT |
572 PIPE_BIND_SHARED);
573
574 if (r300_is_blending_supported(r300_screen(screen), format)) {
575 retval |= usage & PIPE_BIND_BLENDABLE;
576 }
577 }
578
579 /* Check depth-stencil format support. */
580 if (usage & PIPE_BIND_DEPTH_STENCIL &&
581 r300_is_zs_format_supported(format)) {
582 retval |= PIPE_BIND_DEPTH_STENCIL;
583 }
584
585 /* Check vertex buffer format support. */
586 if (usage & PIPE_BIND_VERTEX_BUFFER) {
587 if (r300_screen(screen)->caps.has_tcl) {
588 /* Half float is supported on >= R400. */
589 if ((is_r400 || is_r500 || !is_half_float) &&
590 r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) {
591 retval |= PIPE_BIND_VERTEX_BUFFER;
592 }
593 } else {
594 /* SW TCL */
595 if (!util_format_is_pure_integer(format)) {
596 retval |= PIPE_BIND_VERTEX_BUFFER;
597 }
598 }
599 }
600
601 if (usage & PIPE_BIND_INDEX_BUFFER) {
602 if (format == PIPE_FORMAT_R8_UINT ||
603 format == PIPE_FORMAT_R16_UINT ||
604 format == PIPE_FORMAT_R32_UINT)
605 retval |= PIPE_BIND_INDEX_BUFFER;
606 }
607
608 return retval == usage;
609 }
610
r300_init_screen_caps(struct r300_screen * r300screen)611 static void r300_init_screen_caps(struct r300_screen* r300screen)
612 {
613 struct pipe_caps *caps = (struct pipe_caps *)&r300screen->screen.caps;
614
615 u_init_pipe_screen_caps(&r300screen->screen, 1);
616
617 bool is_r500 = r300screen->caps.is_r500;
618
619 /* Supported features (boolean caps). */
620 caps->npot_textures = true;
621 caps->mixed_framebuffer_sizes = true;
622 caps->mixed_color_depth_bits = true;
623 caps->anisotropic_filter = true;
624 caps->occlusion_query = true;
625 caps->texture_mirror_clamp = true;
626 caps->texture_mirror_clamp_to_edge = true;
627 caps->blend_equation_separate = true;
628 caps->vertex_element_instance_divisor = true;
629 caps->fs_coord_origin_upper_left = true;
630 caps->fs_coord_pixel_center_half_integer = true;
631 caps->conditional_render = true;
632 caps->texture_barrier = true;
633 caps->tgsi_can_compact_constants = true;
634 caps->clip_halfz = true;
635 caps->allow_mapped_buffers_during_execution = true;
636 caps->legacy_math_rules = true;
637 caps->tgsi_texcoord = true;
638 caps->call_finalize_nir_in_linker = true;
639
640 caps->texture_transfer_modes = PIPE_TEXTURE_TRANSFER_BLIT;
641
642 caps->min_map_buffer_alignment = R300_BUFFER_ALIGNMENT;
643
644 caps->constant_buffer_offset_alignment = 16;
645
646 caps->glsl_feature_level =
647 caps->glsl_feature_level_compatibility = 120;
648
649 /* r300 cannot do swizzling of compressed textures. Supported otherwise. */
650 caps->texture_swizzle = r300screen->caps.dxtc_swizzle;
651
652 /* We don't support color clamping on r500, so that we can use color
653 * interpolators for generic varyings. */
654 caps->vertex_color_clamped = !is_r500;
655
656 /* Supported on r500 only. */
657 caps->vertex_color_unclamped =
658 caps->mixed_colorbuffer_formats =
659 caps->fragment_shader_texture_lod =
660 caps->fragment_shader_derivatives = is_r500;
661
662 caps->shareable_shaders = false;
663
664 caps->max_gs_invocations = 32;
665 caps->max_shader_buffer_size = 1 << 27;
666
667 /* SWTCL-only features. */
668 caps->primitive_restart =
669 caps->primitive_restart_fixed_index =
670 caps->user_vertex_buffers =
671 caps->vs_window_space_position = !r300screen->caps.has_tcl;
672
673 /* HWTCL-only features / limitations. */
674 caps->vertex_input_alignment =
675 r300screen->caps.has_tcl ? PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE : PIPE_VERTEX_INPUT_ALIGNMENT_NONE;
676
677 /* Texturing. */
678 caps->max_texture_2d_size = is_r500 ? 4096 : 2048;
679 caps->max_texture_3d_levels =
680 caps->max_texture_cube_levels = is_r500 ? 13 : 12; /* 13 == 4096, 12 == 2048 */
681
682 /* Render targets. */
683 caps->max_render_targets = 4;
684 caps->endianness = PIPE_ENDIAN_LITTLE;
685
686 caps->max_viewports = 1;
687
688 caps->max_vertex_attrib_stride = 2048;
689
690 caps->max_varyings = 10;
691
692 caps->prefer_imm_arrays_as_constbuf = false;
693
694 caps->vendor_id = 0x1002;
695 caps->device_id = r300screen->info.pci_id;
696 caps->video_memory = r300screen->info.vram_size_kb >> 10;
697 caps->uma = false;
698 caps->pci_group = r300screen->info.pci.domain;
699 caps->pci_bus = r300screen->info.pci.bus;
700 caps->pci_device = r300screen->info.pci.dev;
701 caps->pci_function = r300screen->info.pci.func;
702
703 caps->min_line_width =
704 caps->min_line_width_aa =
705 caps->min_point_size =
706 caps->min_point_size_aa = 1;
707 caps->point_size_granularity =
708 caps->line_width_granularity = 0.1;
709 caps->max_line_width =
710 caps->max_line_width_aa =
711 caps->max_point_size =
712 caps->max_point_size_aa =
713 /* The maximum dimensions of the colorbuffer are our practical
714 * rendering limits. 2048 pixels should be enough for anybody. */
715 r300screen->caps.is_r500 ? 4096.0f :
716 (r300screen->caps.is_r400 ? 4021.0f : 2560.0f);
717 caps->max_texture_anisotropy = 16.0f;
718 caps->max_texture_lod_bias = 16.0f;
719 }
720
r300_destroy_screen(struct pipe_screen * pscreen)721 static void r300_destroy_screen(struct pipe_screen* pscreen)
722 {
723 struct r300_screen* r300screen = r300_screen(pscreen);
724 struct radeon_winsys *rws = radeon_winsys(pscreen);
725
726 if (rws && !rws->unref(rws))
727 return;
728
729 mtx_destroy(&r300screen->cmask_mutex);
730 slab_destroy_parent(&r300screen->pool_transfers);
731
732 disk_cache_destroy(r300screen->disk_shader_cache);
733
734 if (rws)
735 rws->destroy(rws);
736
737 FREE(r300screen);
738 }
739
r300_fence_reference(struct pipe_screen * screen,struct pipe_fence_handle ** ptr,struct pipe_fence_handle * fence)740 static void r300_fence_reference(struct pipe_screen *screen,
741 struct pipe_fence_handle **ptr,
742 struct pipe_fence_handle *fence)
743 {
744 struct radeon_winsys *rws = r300_screen(screen)->rws;
745
746 rws->fence_reference(rws, ptr, fence);
747 }
748
r300_fence_finish(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_fence_handle * fence,uint64_t timeout)749 static bool r300_fence_finish(struct pipe_screen *screen,
750 struct pipe_context *ctx,
751 struct pipe_fence_handle *fence,
752 uint64_t timeout)
753 {
754 struct radeon_winsys *rws = r300_screen(screen)->rws;
755
756 return rws->fence_wait(rws, fence, timeout);
757 }
758
r300_screen_get_fd(struct pipe_screen * screen)759 static int r300_screen_get_fd(struct pipe_screen *screen)
760 {
761 struct radeon_winsys *rws = r300_screen(screen)->rws;
762
763 return rws->get_fd(rws);
764 }
765
r300_screen_create(struct radeon_winsys * rws,const struct pipe_screen_config * config)766 struct pipe_screen* r300_screen_create(struct radeon_winsys *rws,
767 const struct pipe_screen_config *config)
768 {
769 struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
770
771 if (!r300screen) {
772 FREE(r300screen);
773 return NULL;
774 }
775
776 rws->query_info(rws, &r300screen->info);
777
778 r300_init_debug(r300screen);
779 r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps);
780
781 driParseConfigFiles(config->options, config->options_info, 0, "r300", NULL,
782 NULL, NULL, 0, NULL, 0);
783
784 #define OPT_BOOL(name, dflt, description) \
785 r300screen->options.name = driQueryOptionb(config->options, "r300_" #name);
786 #include "r300_debug_options.h"
787
788 if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK) ||
789 r300screen->options.nozmask)
790 r300screen->caps.zmask_ram = 0;
791 if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ) ||
792 r300screen->options.nohiz)
793 r300screen->caps.hiz_ram = 0;
794 if (SCREEN_DBG_ON(r300screen, DBG_NO_TCL))
795 r300screen->caps.has_tcl = false;
796
797 if (SCREEN_DBG_ON(r300screen, DBG_IEEEMATH))
798 r300screen->options.ieeemath = true;
799 if (SCREEN_DBG_ON(r300screen, DBG_FFMATH))
800 r300screen->options.ffmath = true;
801
802 r300screen->rws = rws;
803 r300screen->screen.destroy = r300_destroy_screen;
804 r300screen->screen.get_name = r300_get_name;
805 r300screen->screen.get_vendor = r300_get_vendor;
806 r300screen->screen.get_compiler_options = r300_get_compiler_options;
807 r300screen->screen.finalize_nir = r300_finalize_nir;
808 r300screen->screen.get_device_vendor = r300_get_device_vendor;
809 r300screen->screen.get_disk_shader_cache = r300_get_disk_shader_cache;
810 r300screen->screen.get_screen_fd = r300_screen_get_fd;
811 r300screen->screen.get_shader_param = r300_get_shader_param;
812 r300screen->screen.get_video_param = r300_get_video_param;
813 r300screen->screen.is_format_supported = r300_is_format_supported;
814 r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
815 r300screen->screen.context_create = r300_create_context;
816 r300screen->screen.fence_reference = r300_fence_reference;
817 r300screen->screen.fence_finish = r300_fence_finish;
818
819 r300_init_screen_resource_functions(r300screen);
820
821 r300_init_screen_caps(r300screen);
822
823 r300_disk_cache_create(r300screen);
824
825 slab_create_parent(&r300screen->pool_transfers, sizeof(struct pipe_transfer), 64);
826
827 (void) mtx_init(&r300screen->cmask_mutex, mtx_plain);
828
829 return &r300screen->screen;
830 }
831