1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * Authors: Marek Olšák <maraeo@gmail.com>
4 * SPDX-License-Identifier: MIT
5 */
6
7 #include "r600_pipe_common.h"
8 #include "r600_cs.h"
9 #include "evergreen_compute.h"
10 #include "util/list.h"
11 #include "util/u_draw_quad.h"
12 #include "util/u_memory.h"
13 #include "util/format/u_format_s3tc.h"
14 #include "util/u_upload_mgr.h"
15 #include "util/os_time.h"
16 #include "util/hex.h"
17 #include "vl/vl_decoder.h"
18 #include "vl/vl_video_buffer.h"
19 #include "radeon_video.h"
20 #include "git_sha1.h"
21
22 #include <inttypes.h>
23 #include <sys/utsname.h>
24 #include <stdlib.h>
25
26 #if AMD_LLVM_AVAILABLE
27 #include <llvm-c/TargetMachine.h>
28 #endif
29
30 struct r600_multi_fence {
31 struct pipe_reference reference;
32 struct pipe_fence_handle *gfx;
33 struct pipe_fence_handle *sdma;
34
35 /* If the context wasn't flushed at fence creation, this is non-NULL. */
36 struct {
37 struct r600_common_context *ctx;
38 unsigned ib_index;
39 } gfx_unflushed;
40 };
41
42 /*
43 * pipe_context
44 */
45
46 /**
47 * Write an EOP event.
48 *
49 * \param event EVENT_TYPE_*
50 * \param event_flags Optional cache flush flags (TC)
51 * \param data_sel 1 = fence, 3 = timestamp
52 * \param buf Buffer
53 * \param va GPU address
54 * \param old_value Previous fence value (for a bug workaround)
55 * \param new_value Fence value to write for this event.
56 */
r600_gfx_write_event_eop(struct r600_common_context * ctx,unsigned event,unsigned event_flags,unsigned data_sel,struct r600_resource * buf,uint64_t va,uint32_t new_fence,unsigned query_type)57 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
58 unsigned event, unsigned event_flags,
59 unsigned data_sel,
60 struct r600_resource *buf, uint64_t va,
61 uint32_t new_fence, unsigned query_type)
62 {
63 struct radeon_cmdbuf *cs = &ctx->gfx.cs;
64 unsigned op = EVENT_TYPE(event) |
65 EVENT_INDEX(5) |
66 event_flags;
67 unsigned sel = EOP_DATA_SEL(data_sel);
68
69 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
70 radeon_emit(cs, op);
71 radeon_emit(cs, va);
72 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
73 radeon_emit(cs, new_fence); /* immediate data */
74 radeon_emit(cs, 0); /* unused */
75
76 if (buf)
77 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE |
78 RADEON_PRIO_QUERY);
79 }
80
r600_gfx_write_fence_dwords(struct r600_common_screen * screen)81 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
82 {
83 unsigned dwords = 6;
84
85 if (!screen->info.r600_has_virtual_memory)
86 dwords += 2;
87
88 return dwords;
89 }
90
r600_gfx_wait_fence(struct r600_common_context * ctx,struct r600_resource * buf,uint64_t va,uint32_t ref,uint32_t mask)91 void r600_gfx_wait_fence(struct r600_common_context *ctx,
92 struct r600_resource *buf,
93 uint64_t va, uint32_t ref, uint32_t mask)
94 {
95 struct radeon_cmdbuf *cs = &ctx->gfx.cs;
96
97 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
98 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
99 radeon_emit(cs, va);
100 radeon_emit(cs, va >> 32);
101 radeon_emit(cs, ref); /* reference value */
102 radeon_emit(cs, mask); /* mask */
103 radeon_emit(cs, 4); /* poll interval */
104
105 if (buf)
106 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_READ |
107 RADEON_PRIO_QUERY);
108 }
109
r600_draw_rectangle(struct blitter_context * blitter,void * vertex_elements_cso,blitter_get_vs_func get_vs,int x1,int y1,int x2,int y2,float depth,unsigned num_instances,enum blitter_attrib_type type,const union blitter_attrib * attrib)110 void r600_draw_rectangle(struct blitter_context *blitter,
111 void *vertex_elements_cso,
112 blitter_get_vs_func get_vs,
113 int x1, int y1, int x2, int y2,
114 float depth, unsigned num_instances,
115 enum blitter_attrib_type type,
116 const union blitter_attrib *attrib)
117 {
118 struct r600_common_context *rctx =
119 (struct r600_common_context*)util_blitter_get_pipe(blitter);
120 struct pipe_viewport_state viewport;
121 struct pipe_resource *buf = NULL;
122 unsigned offset = 0;
123 float *vb;
124
125 rctx->b.bind_vertex_elements_state(&rctx->b, vertex_elements_cso);
126 rctx->b.bind_vs_state(&rctx->b, get_vs(blitter));
127
128 /* Some operations (like color resolve on r6xx) don't work
129 * with the conventional primitive types.
130 * One that works is PT_RECTLIST, which we use here. */
131
132 /* setup viewport */
133 viewport.scale[0] = 1.0f;
134 viewport.scale[1] = 1.0f;
135 viewport.scale[2] = 1.0f;
136 viewport.translate[0] = 0.0f;
137 viewport.translate[1] = 0.0f;
138 viewport.translate[2] = 0.0f;
139 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
140
141 /* Upload vertices. The hw rectangle has only 3 vertices,
142 * The 4th one is derived from the first 3.
143 * The vertex specification should match u_blitter's vertex element state. */
144 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
145 rctx->screen->info.tcc_cache_line_size,
146 &offset, &buf, (void**)&vb);
147 if (!buf)
148 return;
149
150 vb[0] = x1;
151 vb[1] = y1;
152 vb[2] = depth;
153 vb[3] = 1;
154
155 vb[8] = x1;
156 vb[9] = y2;
157 vb[10] = depth;
158 vb[11] = 1;
159
160 vb[16] = x2;
161 vb[17] = y1;
162 vb[18] = depth;
163 vb[19] = 1;
164
165 switch (type) {
166 case UTIL_BLITTER_ATTRIB_COLOR:
167 memcpy(vb+4, attrib->color, sizeof(float)*4);
168 memcpy(vb+12, attrib->color, sizeof(float)*4);
169 memcpy(vb+20, attrib->color, sizeof(float)*4);
170 break;
171 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
172 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
173 vb[6] = vb[14] = vb[22] = attrib->texcoord.z;
174 vb[7] = vb[15] = vb[23] = attrib->texcoord.w;
175 /* fall through */
176 vb[4] = attrib->texcoord.x1;
177 vb[5] = attrib->texcoord.y1;
178 vb[12] = attrib->texcoord.x1;
179 vb[13] = attrib->texcoord.y2;
180 vb[20] = attrib->texcoord.x2;
181 vb[21] = attrib->texcoord.y1;
182 break;
183 default:; /* Nothing to do. */
184 }
185
186 /* draw */
187 struct pipe_vertex_buffer vbuffer = {};
188 vbuffer.buffer.resource = buf;
189 vbuffer.buffer_offset = offset;
190
191 util_set_vertex_buffers(&rctx->b, 1, false, &vbuffer);
192 util_draw_arrays_instanced(&rctx->b, R600_PRIM_RECTANGLE_LIST, 0, 3,
193 0, num_instances);
194 pipe_resource_reference(&buf, NULL);
195 }
196
r600_dma_emit_wait_idle(struct r600_common_context * rctx)197 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
198 {
199 struct radeon_cmdbuf *cs = &rctx->dma.cs;
200
201 if (rctx->gfx_level >= EVERGREEN)
202 radeon_emit(cs, 0xf0000000); /* NOP */
203 else {
204 /* TODO: R600-R700 should use the FENCE packet.
205 * CS checker support is required. */
206 }
207 }
208
r600_need_dma_space(struct r600_common_context * ctx,unsigned num_dw,struct r600_resource * dst,struct r600_resource * src)209 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
210 struct r600_resource *dst, struct r600_resource *src)
211 {
212 uint64_t vram = (uint64_t)ctx->dma.cs.used_vram_kb * 1024;
213 uint64_t gtt = (uint64_t)ctx->dma.cs.used_gart_kb * 1024;
214
215 if (dst) {
216 vram += dst->vram_usage;
217 gtt += dst->gart_usage;
218 }
219 if (src) {
220 vram += src->vram_usage;
221 gtt += src->gart_usage;
222 }
223
224 /* Flush the GFX IB if DMA depends on it. */
225 if (radeon_emitted(&ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
226 ((dst &&
227 ctx->ws->cs_is_buffer_referenced(&ctx->gfx.cs, dst->buf,
228 RADEON_USAGE_READWRITE)) ||
229 (src &&
230 ctx->ws->cs_is_buffer_referenced(&ctx->gfx.cs, src->buf,
231 RADEON_USAGE_WRITE))))
232 ctx->gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
233
234 /* Flush if there's not enough space, or if the memory usage per IB
235 * is too large.
236 *
237 * IBs using too little memory are limited by the IB submission overhead.
238 * IBs using too much memory are limited by the kernel/TTM overhead.
239 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
240 *
241 * This heuristic makes sure that DMA requests are executed
242 * very soon after the call is made and lowers memory usage.
243 * It improves texture upload performance by keeping the DMA
244 * engine busy while uploads are being submitted.
245 */
246 num_dw++; /* for emit_wait_idle below */
247 if (!ctx->ws->cs_check_space(&ctx->dma.cs, num_dw) ||
248 ctx->dma.cs.used_vram_kb + ctx->dma.cs.used_gart_kb > 64 * 1024 ||
249 !radeon_cs_memory_below_limit(ctx->screen, &ctx->dma.cs, vram, gtt)) {
250 ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
251 assert((num_dw + ctx->dma.cs.current.cdw) <= ctx->dma.cs.current.max_dw);
252 }
253
254 /* Wait for idle if either buffer has been used in the IB before to
255 * prevent read-after-write hazards.
256 */
257 if ((dst &&
258 ctx->ws->cs_is_buffer_referenced(&ctx->dma.cs, dst->buf,
259 RADEON_USAGE_READWRITE)) ||
260 (src &&
261 ctx->ws->cs_is_buffer_referenced(&ctx->dma.cs, src->buf,
262 RADEON_USAGE_WRITE)))
263 r600_dma_emit_wait_idle(ctx);
264
265 /* If GPUVM is not supported, the CS checker needs 2 entries
266 * in the buffer list per packet, which has to be done manually.
267 */
268 if (ctx->screen->info.r600_has_virtual_memory) {
269 if (dst)
270 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
271 RADEON_USAGE_WRITE);
272 if (src)
273 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
274 RADEON_USAGE_READ);
275 }
276
277 /* this function is called before all DMA calls, so increment this. */
278 ctx->num_dma_calls++;
279 }
280
r600_preflush_suspend_features(struct r600_common_context * ctx)281 void r600_preflush_suspend_features(struct r600_common_context *ctx)
282 {
283 /* suspend queries */
284 if (!list_is_empty(&ctx->active_queries))
285 r600_suspend_queries(ctx);
286
287 ctx->streamout.suspended = false;
288 if (ctx->streamout.begin_emitted) {
289 r600_emit_streamout_end(ctx);
290 ctx->streamout.suspended = true;
291 }
292 }
293
r600_postflush_resume_features(struct r600_common_context * ctx)294 void r600_postflush_resume_features(struct r600_common_context *ctx)
295 {
296 if (ctx->streamout.suspended) {
297 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
298 r600_streamout_buffers_dirty(ctx);
299 }
300
301 /* resume queries */
302 if (!list_is_empty(&ctx->active_queries))
303 r600_resume_queries(ctx);
304 }
305
r600_fence_server_sync(struct pipe_context * ctx,struct pipe_fence_handle * fence)306 static void r600_fence_server_sync(struct pipe_context *ctx,
307 struct pipe_fence_handle *fence)
308 {
309 /* radeon synchronizes all rings by default and will not implement
310 * fence imports.
311 */
312 }
313
r600_flush_from_st(struct pipe_context * ctx,struct pipe_fence_handle ** fence,unsigned flags)314 static void r600_flush_from_st(struct pipe_context *ctx,
315 struct pipe_fence_handle **fence,
316 unsigned flags)
317 {
318 struct pipe_screen *screen = ctx->screen;
319 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
320 struct radeon_winsys *ws = rctx->ws;
321 struct pipe_fence_handle *gfx_fence = NULL;
322 struct pipe_fence_handle *sdma_fence = NULL;
323 bool deferred_fence = false;
324 unsigned rflags = PIPE_FLUSH_ASYNC;
325
326 if (flags & PIPE_FLUSH_END_OF_FRAME)
327 rflags |= PIPE_FLUSH_END_OF_FRAME;
328
329 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
330 if (rctx->dma.cs.priv)
331 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
332
333 if (!radeon_emitted(&rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
334 if (fence)
335 ws->fence_reference(ws, &gfx_fence, rctx->last_gfx_fence);
336 if (!(flags & PIPE_FLUSH_DEFERRED))
337 ws->cs_sync_flush(&rctx->gfx.cs);
338 } else {
339 /* Instead of flushing, create a deferred fence. Constraints:
340 * - the gallium frontend must allow a deferred flush.
341 * - the gallium frontend must request a fence.
342 * Thread safety in fence_finish must be ensured by the gallium frontend.
343 */
344 if (flags & PIPE_FLUSH_DEFERRED && fence) {
345 gfx_fence = rctx->ws->cs_get_next_fence(&rctx->gfx.cs);
346 deferred_fence = true;
347 } else {
348 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
349 }
350 }
351
352 /* Both engines can signal out of order, so we need to keep both fences. */
353 if (fence) {
354 struct r600_multi_fence *multi_fence =
355 CALLOC_STRUCT(r600_multi_fence);
356 if (!multi_fence) {
357 ws->fence_reference(ws, &sdma_fence, NULL);
358 ws->fence_reference(ws, &gfx_fence, NULL);
359 goto finish;
360 }
361
362 multi_fence->reference.count = 1;
363 /* If both fences are NULL, fence_finish will always return true. */
364 multi_fence->gfx = gfx_fence;
365 multi_fence->sdma = sdma_fence;
366
367 if (deferred_fence) {
368 multi_fence->gfx_unflushed.ctx = rctx;
369 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
370 }
371
372 screen->fence_reference(screen, fence, NULL);
373 *fence = (struct pipe_fence_handle*)multi_fence;
374 }
375 finish:
376 if (!(flags & PIPE_FLUSH_DEFERRED)) {
377 if (rctx->dma.cs.priv)
378 ws->cs_sync_flush(&rctx->dma.cs);
379 ws->cs_sync_flush(&rctx->gfx.cs);
380 }
381 }
382
r600_flush_dma_ring(void * ctx,unsigned flags,struct pipe_fence_handle ** fence)383 static void r600_flush_dma_ring(void *ctx, unsigned flags,
384 struct pipe_fence_handle **fence)
385 {
386 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
387 struct radeon_cmdbuf *cs = &rctx->dma.cs;
388 struct radeon_saved_cs saved;
389 bool check_vm =
390 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
391 rctx->check_vm_faults;
392
393 if (!radeon_emitted(cs, 0)) {
394 if (fence)
395 rctx->ws->fence_reference(rctx->ws, fence, rctx->last_sdma_fence);
396 return;
397 }
398
399 if (check_vm)
400 radeon_save_cs(rctx->ws, cs, &saved, true);
401
402 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
403 if (fence)
404 rctx->ws->fence_reference(rctx->ws, fence, rctx->last_sdma_fence);
405
406 if (check_vm) {
407 /* Use conservative timeout 800ms, after which we won't wait any
408 * longer and assume the GPU is hung.
409 */
410 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
411
412 rctx->check_vm_faults(rctx, &saved, AMD_IP_SDMA);
413 radeon_clear_saved_cs(&saved);
414 }
415 }
416
417 /**
418 * Store a linearized copy of all chunks of \p cs together with the buffer
419 * list in \p saved.
420 */
radeon_save_cs(struct radeon_winsys * ws,struct radeon_cmdbuf * cs,struct radeon_saved_cs * saved,bool get_buffer_list)421 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
422 struct radeon_saved_cs *saved, bool get_buffer_list)
423 {
424 uint32_t *buf;
425 unsigned i;
426
427 /* Save the IB chunks. */
428 saved->num_dw = cs->prev_dw + cs->current.cdw;
429 saved->ib = MALLOC(4 * saved->num_dw);
430 if (!saved->ib)
431 goto oom;
432
433 buf = saved->ib;
434 for (i = 0; i < cs->num_prev; ++i) {
435 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
436 buf += cs->prev[i].cdw;
437 }
438 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
439
440 if (!get_buffer_list)
441 return;
442
443 /* Save the buffer list. */
444 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
445 saved->bo_list = CALLOC(saved->bo_count,
446 sizeof(saved->bo_list[0]));
447 if (!saved->bo_list) {
448 FREE(saved->ib);
449 goto oom;
450 }
451 ws->cs_get_buffer_list(cs, saved->bo_list);
452
453 return;
454
455 oom:
456 fprintf(stderr, "%s: out of memory\n", __func__);
457 memset(saved, 0, sizeof(*saved));
458 }
459
radeon_clear_saved_cs(struct radeon_saved_cs * saved)460 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
461 {
462 FREE(saved->ib);
463 FREE(saved->bo_list);
464
465 memset(saved, 0, sizeof(*saved));
466 }
467
r600_get_reset_status(struct pipe_context * ctx)468 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
469 {
470 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
471
472 return rctx->ws->ctx_query_reset_status(rctx->ctx, false, NULL, NULL);
473 }
474
r600_set_debug_callback(struct pipe_context * ctx,const struct util_debug_callback * cb)475 static void r600_set_debug_callback(struct pipe_context *ctx,
476 const struct util_debug_callback *cb)
477 {
478 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
479
480 if (cb)
481 rctx->debug = *cb;
482 else
483 memset(&rctx->debug, 0, sizeof(rctx->debug));
484 }
485
r600_set_device_reset_callback(struct pipe_context * ctx,const struct pipe_device_reset_callback * cb)486 static void r600_set_device_reset_callback(struct pipe_context *ctx,
487 const struct pipe_device_reset_callback *cb)
488 {
489 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
490
491 if (cb)
492 rctx->device_reset_callback = *cb;
493 else
494 memset(&rctx->device_reset_callback, 0,
495 sizeof(rctx->device_reset_callback));
496 }
497
r600_check_device_reset(struct r600_common_context * rctx)498 bool r600_check_device_reset(struct r600_common_context *rctx)
499 {
500 enum pipe_reset_status status;
501
502 if (!rctx->device_reset_callback.reset)
503 return false;
504
505 if (!rctx->b.get_device_reset_status)
506 return false;
507
508 status = rctx->b.get_device_reset_status(&rctx->b);
509 if (status == PIPE_NO_RESET)
510 return false;
511
512 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
513 return true;
514 }
515
r600_dma_clear_buffer_fallback(struct pipe_context * ctx,struct pipe_resource * dst,uint64_t offset,uint64_t size,unsigned value)516 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
517 struct pipe_resource *dst,
518 uint64_t offset, uint64_t size,
519 unsigned value)
520 {
521 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
522
523 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
524 }
525
r600_resource_commit(struct pipe_context * pctx,struct pipe_resource * resource,unsigned level,struct pipe_box * box,bool commit)526 static bool r600_resource_commit(struct pipe_context *pctx,
527 struct pipe_resource *resource,
528 unsigned level, struct pipe_box *box,
529 bool commit)
530 {
531 struct r600_common_context *ctx = (struct r600_common_context *)pctx;
532 struct r600_resource *res = r600_resource(resource);
533
534 /*
535 * Since buffer commitment changes cannot be pipelined, we need to
536 * (a) flush any pending commands that refer to the buffer we're about
537 * to change, and
538 * (b) wait for threaded submit to finish, including those that were
539 * triggered by some other, earlier operation.
540 */
541 if (radeon_emitted(&ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
542 ctx->ws->cs_is_buffer_referenced(&ctx->gfx.cs,
543 res->buf, RADEON_USAGE_READWRITE)) {
544 ctx->gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
545 }
546 if (radeon_emitted(&ctx->dma.cs, 0) &&
547 ctx->ws->cs_is_buffer_referenced(&ctx->dma.cs,
548 res->buf, RADEON_USAGE_READWRITE)) {
549 ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
550 }
551
552 ctx->ws->cs_sync_flush(&ctx->dma.cs);
553 ctx->ws->cs_sync_flush(&ctx->gfx.cs);
554
555 assert(resource->target == PIPE_BUFFER);
556
557 return ctx->ws->buffer_commit(ctx->ws, res->buf, box->x, box->width, commit);
558 }
559
r600_common_context_init(struct r600_common_context * rctx,struct r600_common_screen * rscreen,unsigned context_flags)560 bool r600_common_context_init(struct r600_common_context *rctx,
561 struct r600_common_screen *rscreen,
562 unsigned context_flags)
563 {
564 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
565 slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
566
567 rctx->screen = rscreen;
568 rctx->ws = rscreen->ws;
569 rctx->family = rscreen->family;
570 rctx->gfx_level = rscreen->gfx_level;
571
572 rctx->b.clear_buffer = u_default_clear_buffer;
573 rctx->b.invalidate_resource = r600_invalidate_resource;
574 rctx->b.resource_commit = r600_resource_commit;
575 rctx->b.buffer_map = r600_buffer_transfer_map;
576 rctx->b.texture_map = r600_texture_transfer_map;
577 rctx->b.transfer_flush_region = r600_buffer_flush_region;
578 rctx->b.buffer_unmap = r600_buffer_transfer_unmap;
579 rctx->b.texture_unmap = r600_texture_transfer_unmap;
580 rctx->b.texture_subdata = u_default_texture_subdata;
581 rctx->b.flush = r600_flush_from_st;
582 rctx->b.set_debug_callback = r600_set_debug_callback;
583 rctx->b.fence_server_sync = r600_fence_server_sync;
584 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
585
586 /* evergreen_compute.c has a special codepath for global buffers.
587 * Everything else can use the direct path.
588 */
589 if ((rscreen->gfx_level == EVERGREEN || rscreen->gfx_level == CAYMAN) &&
590 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
591 rctx->b.buffer_subdata = u_default_buffer_subdata;
592 else
593 rctx->b.buffer_subdata = r600_buffer_subdata;
594
595 rctx->b.get_device_reset_status = r600_get_reset_status;
596 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
597
598 r600_init_context_texture_functions(rctx);
599 r600_init_viewport_functions(rctx);
600 r600_streamout_init(rctx);
601 r600_query_init(rctx);
602 cayman_init_msaa(&rctx->b);
603
604 u_suballocator_init(&rctx->allocator_zeroed_memory, &rctx->b, rscreen->info.gart_page_size,
605 0, PIPE_USAGE_DEFAULT, 0, true);
606
607 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
608 0, PIPE_USAGE_STREAM, 0);
609 if (!rctx->b.stream_uploader)
610 return false;
611
612 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
613 0, PIPE_USAGE_DEFAULT, 0);
614 if (!rctx->b.const_uploader)
615 return false;
616
617 rctx->ctx = rctx->ws->ctx_create(rctx->ws, RADEON_CTX_PRIORITY_MEDIUM, false);
618 if (!rctx->ctx)
619 return false;
620
621 if (rscreen->info.ip[AMD_IP_SDMA].num_queues && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
622 rctx->ws->cs_create(&rctx->dma.cs, rctx->ctx, AMD_IP_SDMA,
623 r600_flush_dma_ring, rctx);
624 rctx->dma.flush = r600_flush_dma_ring;
625 }
626
627 return true;
628 }
629
r600_common_context_cleanup(struct r600_common_context * rctx)630 void r600_common_context_cleanup(struct r600_common_context *rctx)
631 {
632 if (rctx->query_result_shader)
633 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
634
635 rctx->ws->cs_destroy(&rctx->gfx.cs);
636 rctx->ws->cs_destroy(&rctx->dma.cs);
637 if (rctx->ctx)
638 rctx->ws->ctx_destroy(rctx->ctx);
639
640 if (rctx->b.stream_uploader)
641 u_upload_destroy(rctx->b.stream_uploader);
642 if (rctx->b.const_uploader)
643 u_upload_destroy(rctx->b.const_uploader);
644
645 slab_destroy_child(&rctx->pool_transfers);
646 slab_destroy_child(&rctx->pool_transfers_unsync);
647
648 u_suballocator_destroy(&rctx->allocator_zeroed_memory);
649 rctx->ws->fence_reference(rctx->ws, &rctx->last_gfx_fence, NULL);
650 rctx->ws->fence_reference(rctx->ws, &rctx->last_sdma_fence, NULL);
651 r600_resource_reference(&rctx->eop_bug_scratch, NULL);
652 }
653
654 /*
655 * pipe_screen
656 */
657
658 static const struct debug_named_value common_debug_options[] = {
659 /* logging */
660 { "tex", DBG_TEX, "Print texture info" },
661 { "nir", DBG_NIR, "Enable experimental NIR shaders" },
662 { "compute", DBG_COMPUTE, "Print compute info" },
663 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
664 { "info", DBG_INFO, "Print driver information" },
665
666 /* shaders */
667 { "fs", DBG_FS, "Print fetch shaders" },
668 { "vs", DBG_VS, "Print vertex shaders" },
669 { "gs", DBG_GS, "Print geometry shaders" },
670 { "ps", DBG_PS, "Print pixel shaders" },
671 { "cs", DBG_CS, "Print compute shaders" },
672 { "tcs", DBG_TCS, "Print tessellation control shaders" },
673 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
674 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
675 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
676
677 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
678 { "testvmfaultcp", DBG_TEST_VMFAULT_CP, "Invoke a CP VM fault test and exit." },
679 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA, "Invoke a SDMA VM fault test and exit." },
680 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER, "Invoke a shader VM fault test and exit." },
681
682 /* features */
683 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
684 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
685 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
686 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
687 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
688 { "notiling", DBG_NO_TILING, "Disable tiling" },
689 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
690 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
691 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
692 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
693
694 DEBUG_NAMED_VALUE_END /* must be last */
695 };
696
r600_get_vendor(struct pipe_screen * pscreen)697 static const char* r600_get_vendor(struct pipe_screen* pscreen)
698 {
699 return "Mesa";
700 }
701
r600_get_device_vendor(struct pipe_screen * pscreen)702 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
703 {
704 return "AMD";
705 }
706
r600_get_family_name(const struct r600_common_screen * rscreen)707 static const char *r600_get_family_name(const struct r600_common_screen *rscreen)
708 {
709 switch (rscreen->info.family) {
710 case CHIP_R600: return "AMD R600";
711 case CHIP_RV610: return "AMD RV610";
712 case CHIP_RV630: return "AMD RV630";
713 case CHIP_RV670: return "AMD RV670";
714 case CHIP_RV620: return "AMD RV620";
715 case CHIP_RV635: return "AMD RV635";
716 case CHIP_RS780: return "AMD RS780";
717 case CHIP_RS880: return "AMD RS880";
718 case CHIP_RV770: return "AMD RV770";
719 case CHIP_RV730: return "AMD RV730";
720 case CHIP_RV710: return "AMD RV710";
721 case CHIP_RV740: return "AMD RV740";
722 case CHIP_CEDAR: return "AMD CEDAR";
723 case CHIP_REDWOOD: return "AMD REDWOOD";
724 case CHIP_JUNIPER: return "AMD JUNIPER";
725 case CHIP_CYPRESS: return "AMD CYPRESS";
726 case CHIP_HEMLOCK: return "AMD HEMLOCK";
727 case CHIP_PALM: return "AMD PALM";
728 case CHIP_SUMO: return "AMD SUMO";
729 case CHIP_SUMO2: return "AMD SUMO2";
730 case CHIP_BARTS: return "AMD BARTS";
731 case CHIP_TURKS: return "AMD TURKS";
732 case CHIP_CAICOS: return "AMD CAICOS";
733 case CHIP_CAYMAN: return "AMD CAYMAN";
734 case CHIP_ARUBA: return "AMD ARUBA";
735 default: return "AMD unknown";
736 }
737 }
738
r600_disk_cache_create(struct r600_common_screen * rscreen)739 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
740 {
741 /* Don't use the cache if shader dumping is enabled. */
742 if (rscreen->debug_flags & DBG_ALL_SHADERS)
743 return;
744
745 struct mesa_sha1 ctx;
746 unsigned char sha1[20];
747 char cache_id[20 * 2 + 1];
748
749 _mesa_sha1_init(&ctx);
750 if (!disk_cache_get_function_identifier(r600_disk_cache_create,
751 &ctx))
752 return;
753
754 _mesa_sha1_final(&ctx, sha1);
755 mesa_bytes_to_hex(cache_id, sha1, 20);
756
757 /* These flags affect shader compilation. */
758 rscreen->disk_shader_cache =
759 disk_cache_create(r600_get_family_name(rscreen),
760 cache_id, 0);
761 }
762
r600_get_disk_shader_cache(struct pipe_screen * pscreen)763 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
764 {
765 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
766 return rscreen->disk_shader_cache;
767 }
768
r600_get_name(struct pipe_screen * pscreen)769 static const char* r600_get_name(struct pipe_screen* pscreen)
770 {
771 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
772
773 return rscreen->renderer_string;
774 }
775
r600_get_video_param(struct pipe_screen * screen,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint,enum pipe_video_cap param)776 static int r600_get_video_param(struct pipe_screen *screen,
777 enum pipe_video_profile profile,
778 enum pipe_video_entrypoint entrypoint,
779 enum pipe_video_cap param)
780 {
781 switch (param) {
782 case PIPE_VIDEO_CAP_SUPPORTED:
783 return vl_profile_supported(screen, profile, entrypoint);
784 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
785 return 1;
786 case PIPE_VIDEO_CAP_MAX_WIDTH:
787 case PIPE_VIDEO_CAP_MAX_HEIGHT:
788 return vl_video_buffer_max_size(screen);
789 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
790 return PIPE_FORMAT_NV12;
791 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
792 return false;
793 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
794 return false;
795 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
796 return true;
797 case PIPE_VIDEO_CAP_MAX_LEVEL:
798 return vl_level_supported(screen, profile);
799 default:
800 return 0;
801 }
802 }
803
r600_get_llvm_processor_name(enum radeon_family family)804 const char *r600_get_llvm_processor_name(enum radeon_family family)
805 {
806 switch (family) {
807 case CHIP_R600:
808 case CHIP_RV630:
809 case CHIP_RV635:
810 case CHIP_RV670:
811 return "r600";
812 case CHIP_RV610:
813 case CHIP_RV620:
814 case CHIP_RS780:
815 case CHIP_RS880:
816 return "rs880";
817 case CHIP_RV710:
818 return "rv710";
819 case CHIP_RV730:
820 return "rv730";
821 case CHIP_RV740:
822 case CHIP_RV770:
823 return "rv770";
824 case CHIP_PALM:
825 case CHIP_CEDAR:
826 return "cedar";
827 case CHIP_SUMO:
828 case CHIP_SUMO2:
829 return "sumo";
830 case CHIP_REDWOOD:
831 return "redwood";
832 case CHIP_JUNIPER:
833 return "juniper";
834 case CHIP_HEMLOCK:
835 case CHIP_CYPRESS:
836 return "cypress";
837 case CHIP_BARTS:
838 return "barts";
839 case CHIP_TURKS:
840 return "turks";
841 case CHIP_CAICOS:
842 return "caicos";
843 case CHIP_CAYMAN:
844 case CHIP_ARUBA:
845 return "cayman";
846
847 default:
848 return "";
849 }
850 }
851
get_max_threads_per_block(struct r600_common_screen * screen,enum pipe_shader_ir ir_type)852 static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
853 enum pipe_shader_ir ir_type)
854 {
855 if (ir_type != PIPE_SHADER_IR_TGSI &&
856 ir_type != PIPE_SHADER_IR_NIR)
857 return 256;
858 if (screen->gfx_level >= EVERGREEN)
859 return 1024;
860 return 256;
861 }
862
r600_get_compute_param(struct pipe_screen * screen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * ret)863 static int r600_get_compute_param(struct pipe_screen *screen,
864 enum pipe_shader_ir ir_type,
865 enum pipe_compute_cap param,
866 void *ret)
867 {
868 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
869
870 //TODO: select these params by asic
871 switch (param) {
872 case PIPE_COMPUTE_CAP_IR_TARGET: {
873 const char *gpu;
874 const char *triple = "r600--";
875 gpu = r600_get_llvm_processor_name(rscreen->family);
876 if (ret) {
877 sprintf(ret, "%s-%s", gpu, triple);
878 }
879 /* +2 for dash and terminating NIL byte */
880 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
881 }
882 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
883 if (ret) {
884 uint64_t *grid_dimension = ret;
885 grid_dimension[0] = 3;
886 }
887 return 1 * sizeof(uint64_t);
888
889 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
890 if (ret) {
891 uint64_t *grid_size = ret;
892 grid_size[0] = 65535;
893 grid_size[1] = 65535;
894 grid_size[2] = 65535;
895 }
896 return 3 * sizeof(uint64_t) ;
897
898 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
899 if (ret) {
900 uint64_t *block_size = ret;
901 unsigned threads_per_block = get_max_threads_per_block(rscreen, ir_type);
902 block_size[0] = threads_per_block;
903 block_size[1] = threads_per_block;
904 block_size[2] = threads_per_block;
905 }
906 return 3 * sizeof(uint64_t);
907
908 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
909 if (ret) {
910 uint64_t *max_threads_per_block = ret;
911 *max_threads_per_block = get_max_threads_per_block(rscreen, ir_type);
912 }
913 return sizeof(uint64_t);
914 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
915 if (ret) {
916 uint32_t *address_bits = ret;
917 address_bits[0] = 32;
918 }
919 return 1 * sizeof(uint32_t);
920
921 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
922 if (ret) {
923 uint64_t *max_global_size = ret;
924 uint64_t max_mem_alloc_size;
925
926 r600_get_compute_param(screen, ir_type,
927 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
928 &max_mem_alloc_size);
929
930 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
931 * 1/4 of the MAX_GLOBAL_SIZE. Since the
932 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
933 * make sure we never report more than
934 * 4 * MAX_MEM_ALLOC_SIZE.
935 */
936 *max_global_size = MIN2(4 * max_mem_alloc_size,
937 rscreen->info.max_heap_size_kb * 1024ull);
938 }
939 return sizeof(uint64_t);
940
941 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
942 if (ret) {
943 uint64_t *max_local_size = ret;
944 /* Value reported by the closed source driver. */
945 *max_local_size = 32768;
946 }
947 return sizeof(uint64_t);
948
949 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
950 if (ret) {
951 uint64_t *max_input_size = ret;
952 /* Value reported by the closed source driver. */
953 *max_input_size = 1024;
954 }
955 return sizeof(uint64_t);
956
957 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
958 if (ret) {
959 uint64_t *max_mem_alloc_size = ret;
960
961 *max_mem_alloc_size = (rscreen->info.max_heap_size_kb / 4) * 1024ull;
962 }
963 return sizeof(uint64_t);
964
965 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
966 if (ret) {
967 uint32_t *max_clock_frequency = ret;
968 *max_clock_frequency = rscreen->info.max_gpu_freq_mhz;
969 }
970 return sizeof(uint32_t);
971
972 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
973 if (ret) {
974 uint32_t *max_compute_units = ret;
975 *max_compute_units = rscreen->info.num_cu;
976 }
977 return sizeof(uint32_t);
978
979 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
980 if (ret) {
981 uint32_t *images_supported = ret;
982 *images_supported = 0;
983 }
984 return sizeof(uint32_t);
985 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
986 break; /* unused */
987 case PIPE_COMPUTE_CAP_SUBGROUP_SIZES:
988 if (ret) {
989 uint32_t *subgroup_size = ret;
990 *subgroup_size = r600_wavefront_size(rscreen->family);
991 }
992 return sizeof(uint32_t);
993 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
994 if (ret) {
995 uint64_t *max_variable_threads_per_block = ret;
996 *max_variable_threads_per_block = 0;
997 }
998 return sizeof(uint64_t);
999 case PIPE_COMPUTE_CAP_MAX_SUBGROUPS:
1000 return 0;
1001 }
1002
1003 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1004 return 0;
1005 }
1006
r600_get_timestamp(struct pipe_screen * screen)1007 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1008 {
1009 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1010
1011 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1012 rscreen->info.clock_crystal_freq;
1013 }
1014
r600_fence_reference(struct pipe_screen * screen,struct pipe_fence_handle ** dst,struct pipe_fence_handle * src)1015 static void r600_fence_reference(struct pipe_screen *screen,
1016 struct pipe_fence_handle **dst,
1017 struct pipe_fence_handle *src)
1018 {
1019 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1020 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1021 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1022
1023 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1024 ws->fence_reference(ws, &(*rdst)->gfx, NULL);
1025 ws->fence_reference(ws, &(*rdst)->sdma, NULL);
1026 FREE(*rdst);
1027 }
1028 *rdst = rsrc;
1029 }
1030
r600_fence_finish(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_fence_handle * fence,uint64_t timeout)1031 static bool r600_fence_finish(struct pipe_screen *screen,
1032 struct pipe_context *ctx,
1033 struct pipe_fence_handle *fence,
1034 uint64_t timeout)
1035 {
1036 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1037 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1038 struct r600_common_context *rctx;
1039 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1040
1041 ctx = threaded_context_unwrap_sync(ctx);
1042 rctx = ctx ? (struct r600_common_context*)ctx : NULL;
1043
1044 if (rfence->sdma) {
1045 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1046 return false;
1047
1048 /* Recompute the timeout after waiting. */
1049 if (timeout && timeout != OS_TIMEOUT_INFINITE) {
1050 int64_t time = os_time_get_nano();
1051 timeout = abs_timeout > time ? abs_timeout - time : 0;
1052 }
1053 }
1054
1055 if (!rfence->gfx)
1056 return true;
1057
1058 /* Flush the gfx IB if it hasn't been flushed yet. */
1059 if (rctx &&
1060 rfence->gfx_unflushed.ctx == rctx &&
1061 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1062 rctx->gfx.flush(rctx, timeout ? 0 : PIPE_FLUSH_ASYNC, NULL);
1063 rfence->gfx_unflushed.ctx = NULL;
1064
1065 if (!timeout)
1066 return false;
1067
1068 /* Recompute the timeout after all that. */
1069 if (timeout && timeout != OS_TIMEOUT_INFINITE) {
1070 int64_t time = os_time_get_nano();
1071 timeout = abs_timeout > time ? abs_timeout - time : 0;
1072 }
1073 }
1074
1075 return rws->fence_wait(rws, rfence->gfx, timeout);
1076 }
1077
r600_query_memory_info(struct pipe_screen * screen,struct pipe_memory_info * info)1078 static void r600_query_memory_info(struct pipe_screen *screen,
1079 struct pipe_memory_info *info)
1080 {
1081 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1082 struct radeon_winsys *ws = rscreen->ws;
1083 unsigned vram_usage, gtt_usage;
1084
1085 info->total_device_memory = rscreen->info.vram_size_kb;
1086 info->total_staging_memory = rscreen->info.gart_size_kb;
1087
1088 /* The real TTM memory usage is somewhat random, because:
1089 *
1090 * 1) TTM delays freeing memory, because it can only free it after
1091 * fences expire.
1092 *
1093 * 2) The memory usage can be really low if big VRAM evictions are
1094 * taking place, but the real usage is well above the size of VRAM.
1095 *
1096 * Instead, return statistics of this process.
1097 */
1098 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1099 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1100
1101 info->avail_device_memory =
1102 vram_usage <= info->total_device_memory ?
1103 info->total_device_memory - vram_usage : 0;
1104 info->avail_staging_memory =
1105 gtt_usage <= info->total_staging_memory ?
1106 info->total_staging_memory - gtt_usage : 0;
1107
1108 info->device_memory_evicted =
1109 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1110
1111 /* Just return the number of evicted 64KB pages. */
1112 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1113 }
1114
r600_resource_create_common(struct pipe_screen * screen,const struct pipe_resource * templ)1115 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1116 const struct pipe_resource *templ)
1117 {
1118 if (templ->target == PIPE_BUFFER) {
1119 return r600_buffer_create(screen, templ, 256);
1120 } else {
1121 return r600_texture_create(screen, templ);
1122 }
1123 }
1124
1125 static const void *
r600_get_compiler_options(struct pipe_screen * screen,enum pipe_shader_ir ir,enum pipe_shader_type shader)1126 r600_get_compiler_options(struct pipe_screen *screen,
1127 enum pipe_shader_ir ir,
1128 enum pipe_shader_type shader)
1129 {
1130 assert(ir == PIPE_SHADER_IR_NIR);
1131
1132 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
1133
1134 if (shader != PIPE_SHADER_FRAGMENT)
1135 return &rscreen->nir_options;
1136 else
1137 return &rscreen->nir_options_fs;
1138 }
1139
1140 extern bool r600_lower_to_scalar_instr_filter(const nir_instr *instr, const void *);
1141
r600_resource_destroy(struct pipe_screen * screen,struct pipe_resource * res)1142 static void r600_resource_destroy(struct pipe_screen *screen,
1143 struct pipe_resource *res)
1144 {
1145 if (res->target == PIPE_BUFFER) {
1146 if (r600_resource(res)->compute_global_bo)
1147 r600_compute_global_buffer_destroy(screen, res);
1148 else
1149 r600_buffer_destroy(screen, res);
1150 } else {
1151 r600_texture_destroy(screen, res);
1152 }
1153 }
1154
r600_get_screen_fd(struct pipe_screen * screen)1155 static int r600_get_screen_fd(struct pipe_screen *screen)
1156 {
1157 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1158
1159 return ws->get_fd(ws);
1160 }
1161
r600_get_driver_uuid(UNUSED struct pipe_screen * screen,char * uuid)1162 static void r600_get_driver_uuid(UNUSED struct pipe_screen *screen, char *uuid)
1163 {
1164 const char *driver_id = PACKAGE_VERSION MESA_GIT_SHA1 "r600";
1165
1166 /* The driver UUID is used for determining sharability of images and
1167 * memory between two Vulkan instances in separate processes, but also
1168 * to determining memory objects and sharability between Vulkan and
1169 * OpenGL driver. People who want to share memory need to also check
1170 * the device UUID.
1171 */
1172 struct mesa_sha1 sha1_ctx;
1173 _mesa_sha1_init(&sha1_ctx);
1174
1175 _mesa_sha1_update(&sha1_ctx, driver_id, strlen(driver_id));
1176
1177 uint8_t sha1[SHA1_DIGEST_LENGTH];
1178 _mesa_sha1_final(&sha1_ctx, sha1);
1179
1180 assert(SHA1_DIGEST_LENGTH >= PIPE_UUID_SIZE);
1181 memcpy(uuid, sha1, PIPE_UUID_SIZE);
1182 }
1183
r600_get_device_uuid(struct pipe_screen * screen,char * uuid)1184 static void r600_get_device_uuid(struct pipe_screen *screen, char *uuid)
1185 {
1186 uint32_t *uint_uuid = (uint32_t *)uuid;
1187 struct r600_common_screen* rs = (struct r600_common_screen*)screen;
1188
1189 assert(PIPE_UUID_SIZE >= sizeof(uint32_t) * 4);
1190
1191 /* Copied from ac_device_info
1192 * Use the device info directly instead of using a sha1. GL/VK UUIDs
1193 * are 16 byte vs 20 byte for sha1, and the truncation that would be
1194 * required would get rid of part of the little entropy we have.
1195 */
1196 memset(uuid, 0, PIPE_UUID_SIZE);
1197 if (!rs->info.pci.valid)
1198 fprintf(stderr,
1199 "r600 device_uuid output is based on invalid pci bus info.\n");
1200 uint_uuid[0] = rs->info.pci.domain;
1201 uint_uuid[1] = rs->info.pci.bus;
1202 uint_uuid[2] = rs->info.pci.dev;
1203 uint_uuid[3] = rs->info.pci.func;
1204 }
1205
r600_common_screen_init(struct r600_common_screen * rscreen,struct radeon_winsys * ws)1206 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1207 struct radeon_winsys *ws)
1208 {
1209 char family_name[32] = {}, kernel_version[128] = {};
1210 struct utsname uname_data;
1211 const char *chip_name;
1212
1213 ws->query_info(ws, &rscreen->info);
1214 rscreen->ws = ws;
1215
1216 chip_name = r600_get_family_name(rscreen);
1217
1218 if (uname(&uname_data) == 0)
1219 snprintf(kernel_version, sizeof(kernel_version),
1220 " / %s", uname_data.release);
1221
1222 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1223 "%s (%sDRM %i.%i.%i%s"
1224 #if AMD_LLVM_AVAILABLE
1225 ", LLVM " MESA_LLVM_VERSION_STRING
1226 #endif
1227 ")",
1228 chip_name, family_name, rscreen->info.drm_major,
1229 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1230 kernel_version);
1231
1232 rscreen->b.get_name = r600_get_name;
1233 rscreen->b.get_vendor = r600_get_vendor;
1234 rscreen->b.get_device_vendor = r600_get_device_vendor;
1235 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1236 rscreen->b.get_compute_param = r600_get_compute_param;
1237 rscreen->b.get_screen_fd = r600_get_screen_fd;
1238 rscreen->b.get_timestamp = r600_get_timestamp;
1239 rscreen->b.get_compiler_options = r600_get_compiler_options;
1240 rscreen->b.fence_finish = r600_fence_finish;
1241 rscreen->b.fence_reference = r600_fence_reference;
1242 rscreen->b.resource_destroy = r600_resource_destroy;
1243 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1244 rscreen->b.query_memory_info = r600_query_memory_info;
1245 rscreen->b.get_device_uuid = r600_get_device_uuid;
1246 rscreen->b.get_driver_uuid = r600_get_driver_uuid;
1247
1248 if (rscreen->info.ip[AMD_IP_UVD].num_queues) {
1249 rscreen->b.get_video_param = rvid_get_video_param;
1250 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1251 } else {
1252 rscreen->b.get_video_param = r600_get_video_param;
1253 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1254 }
1255
1256 r600_init_screen_texture_functions(rscreen);
1257 r600_init_screen_query_functions(rscreen);
1258
1259 rscreen->family = rscreen->info.family;
1260 rscreen->gfx_level = rscreen->info.gfx_level;
1261 rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1262
1263 r600_disk_cache_create(rscreen);
1264
1265 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1266
1267 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1268 if (rscreen->force_aniso >= 0) {
1269 printf("radeon: Forcing anisotropy filter to %ix\n",
1270 /* round down to a power of two */
1271 1 << util_logbase2(rscreen->force_aniso));
1272 }
1273
1274 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1275 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1276
1277 if (rscreen->debug_flags & DBG_INFO) {
1278 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1279 rscreen->info.pci.domain, rscreen->info.pci.bus,
1280 rscreen->info.pci.dev, rscreen->info.pci.func);
1281 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1282 printf("family = %i (%s)\n", rscreen->info.family,
1283 r600_get_family_name(rscreen));
1284 printf("gfx_level = %i\n", rscreen->info.gfx_level);
1285 printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size);
1286 printf("gart_page_size = %u\n", rscreen->info.gart_page_size);
1287 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size_kb, 1024));
1288 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size_kb, 1024));
1289 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size_kb, 1024));
1290 printf("max_heap_size = %i MB\n",
1291 (int)DIV_ROUND_UP(rscreen->info.max_heap_size_kb, 1024));
1292 printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size);
1293 printf("has_dedicated_vram = %u\n", rscreen->info.has_dedicated_vram);
1294 printf("r600_has_virtual_memory = %i\n", rscreen->info.r600_has_virtual_memory);
1295 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1296 printf("ip[AMD_IP_UVD] = %u\n", rscreen->info.ip[AMD_IP_UVD].num_queues);
1297 printf("ip[AMD_IP_SDMA] = %i\n", rscreen->info.ip[AMD_IP_SDMA].num_queues);
1298 printf("ip[AMD_IP_COMPUTE] = %u\n", rscreen->info.ip[AMD_IP_COMPUTE].num_queues);
1299 printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version);
1300 printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version);
1301 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1302 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1303 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1304 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1305 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
1306 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1307 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1308 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1309 printf("has_syncobj = %u\n", rscreen->info.has_syncobj);
1310
1311 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1312 printf("max_gpu_freq_mhz = %i\n", rscreen->info.max_gpu_freq_mhz);
1313 printf("num_cu = %i\n", rscreen->info.num_cu);
1314 printf("max_se = %i\n", rscreen->info.max_se);
1315 printf("max_sh_per_se = %i\n", rscreen->info.max_sa_per_se);
1316
1317 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1318 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1319 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1320 printf("num_render_backends = %i\n", rscreen->info.max_render_backends);
1321 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1322 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1323 printf("enabled_rb_mask = 0x%" PRIx64 "\n", rscreen->info.enabled_rb_mask);
1324 printf("max_alignment = %u\n", (unsigned)rscreen->info.max_alignment);
1325 }
1326
1327 const struct nir_shader_compiler_options nir_options = {
1328 .fuse_ffma16 = true,
1329 .fuse_ffma32 = true,
1330 .fuse_ffma64 = true,
1331 .lower_flrp32 = true,
1332 .lower_flrp64 = true,
1333 .lower_fdiv = true,
1334 .lower_isign = true,
1335 .lower_fsign = true,
1336 .lower_fmod = true,
1337 .lower_uadd_carry = true,
1338 .lower_usub_borrow = true,
1339 .lower_bitfield_extract = true,
1340 .lower_bitfield_insert = true,
1341 .lower_extract_byte = true,
1342 .lower_extract_word = true,
1343 .lower_insert_byte = true,
1344 .lower_insert_word = true,
1345 .lower_ldexp = true,
1346 /* due to a bug in the shader compiler, some loops hang
1347 * if they are not unrolled, see:
1348 * https://bugs.freedesktop.org/show_bug.cgi?id=86720
1349 */
1350 .max_unroll_iterations = 255,
1351 .lower_interpolate_at = true,
1352 .vectorize_io = true,
1353 .has_umad24 = true,
1354 .has_umul24 = true,
1355 .has_fmulz = true,
1356 .has_fsub = true,
1357 .has_isub = true,
1358 .has_find_msb_rev = true,
1359 .lower_iabs = true,
1360 .lower_uadd_sat = true,
1361 .lower_usub_sat = true,
1362 .has_fused_comp_and_csel = true,
1363 .lower_ifind_msb = true,
1364 .lower_ufind_msb = true,
1365 .lower_to_scalar = true,
1366 .lower_to_scalar_filter = r600_lower_to_scalar_instr_filter,
1367 .lower_fpow = true,
1368 .lower_int64_options = ~0,
1369 .lower_cs_local_index_to_id = true,
1370 .lower_uniforms_to_ubo = true,
1371 .lower_image_offset_to_range_base = 1,
1372 .vectorize_tess_levels = 1,
1373 .io_options = nir_io_mediump_is_32bit,
1374 };
1375
1376 rscreen->nir_options = nir_options;
1377
1378 if (rscreen->info.family < CHIP_CEDAR)
1379 rscreen->nir_options.force_indirect_unrolling_sampler = true;
1380
1381 if (rscreen->info.gfx_level >= EVERGREEN) {
1382 rscreen->nir_options.has_bfe = true;
1383 rscreen->nir_options.has_bfm = true;
1384 rscreen->nir_options.has_bitfield_select = true;
1385 }
1386
1387 if (rscreen->info.gfx_level < EVERGREEN) {
1388 /* Pre-EG doesn't have these ALU ops */
1389 rscreen->nir_options.lower_bit_count = true;
1390 rscreen->nir_options.lower_bitfield_reverse = true;
1391 }
1392
1393 if (rscreen->info.gfx_level < CAYMAN) {
1394 rscreen->nir_options.lower_doubles_options = nir_lower_fp64_full_software;
1395 rscreen->nir_options.lower_atomic_offset_to_range_base = true;
1396 } else {
1397 rscreen->nir_options.lower_doubles_options =
1398 nir_lower_ddiv |
1399 nir_lower_dfloor |
1400 nir_lower_dceil |
1401 nir_lower_dmod |
1402 nir_lower_dsub |
1403 nir_lower_dtrunc |
1404 nir_lower_dround_even;
1405 }
1406
1407 rscreen->nir_options_fs = rscreen->nir_options;
1408 rscreen->nir_options_fs.lower_all_io_to_temps = true;
1409 rscreen->nir_options.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES);
1410 rscreen->nir_options.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES);
1411
1412 return true;
1413 }
1414
r600_destroy_common_screen(struct r600_common_screen * rscreen)1415 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1416 {
1417 r600_perfcounters_destroy(rscreen);
1418 r600_gpu_load_kill_thread(rscreen);
1419
1420 mtx_destroy(&rscreen->gpu_load_mutex);
1421 mtx_destroy(&rscreen->aux_context_lock);
1422 rscreen->aux_context->destroy(rscreen->aux_context);
1423
1424 slab_destroy_parent(&rscreen->pool_transfers);
1425
1426 disk_cache_destroy(rscreen->disk_shader_cache);
1427 rscreen->ws->destroy(rscreen->ws);
1428 FREE(rscreen);
1429 }
1430
r600_can_dump_shader(struct r600_common_screen * rscreen,unsigned processor)1431 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1432 unsigned processor)
1433 {
1434 return rscreen->debug_flags & (1 << processor);
1435 }
1436
r600_extra_shader_checks(struct r600_common_screen * rscreen,unsigned processor)1437 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1438 {
1439 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1440 r600_can_dump_shader(rscreen, processor);
1441 }
1442
r600_screen_clear_buffer(struct r600_common_screen * rscreen,struct pipe_resource * dst,uint64_t offset,uint64_t size,unsigned value)1443 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1444 uint64_t offset, uint64_t size, unsigned value)
1445 {
1446 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1447
1448 mtx_lock(&rscreen->aux_context_lock);
1449 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1450 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1451 mtx_unlock(&rscreen->aux_context_lock);
1452 }
1453