1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * Authors: Marek Olšák <maraeo@gmail.com>
4 * SPDX-License-Identifier: MIT
5 */
6
7 #include "r600_pipe_common.h"
8 #include "r600_cs.h"
9
10 #include "util/u_memory.h"
11 #include "evergreend.h"
12
13 #define R_008490_CP_STRMOUT_CNTL 0x008490
14 #define R_028AB0_VGT_STRMOUT_EN 0x028AB0
15 #define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20
16
17 static void r600_set_streamout_enable(struct r600_common_context *rctx, bool enable);
18
19 static struct pipe_stream_output_target *
r600_create_so_target(struct pipe_context * ctx,struct pipe_resource * buffer,unsigned buffer_offset,unsigned buffer_size)20 r600_create_so_target(struct pipe_context *ctx,
21 struct pipe_resource *buffer,
22 unsigned buffer_offset,
23 unsigned buffer_size)
24 {
25 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
26 struct r600_so_target *t;
27 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
28
29 t = CALLOC_STRUCT(r600_so_target);
30 if (!t) {
31 return NULL;
32 }
33
34 u_suballocator_alloc(&rctx->allocator_zeroed_memory, 4, 4,
35 &t->buf_filled_size_offset,
36 (struct pipe_resource**)&t->buf_filled_size);
37 if (!t->buf_filled_size) {
38 FREE(t);
39 return NULL;
40 }
41
42 t->b.reference.count = 1;
43 t->b.context = ctx;
44 pipe_resource_reference(&t->b.buffer, buffer);
45 t->b.buffer_offset = buffer_offset;
46 t->b.buffer_size = buffer_size;
47
48 util_range_add(buffer, &rbuffer->valid_buffer_range, buffer_offset,
49 buffer_offset + buffer_size);
50 return &t->b;
51 }
52
r600_so_target_destroy(struct pipe_context * ctx,struct pipe_stream_output_target * target)53 static void r600_so_target_destroy(struct pipe_context *ctx,
54 struct pipe_stream_output_target *target)
55 {
56 struct r600_so_target *t = (struct r600_so_target*)target;
57 pipe_resource_reference(&t->b.buffer, NULL);
58 r600_resource_reference(&t->buf_filled_size, NULL);
59 FREE(t);
60 }
61
r600_streamout_buffers_dirty(struct r600_common_context * rctx)62 void r600_streamout_buffers_dirty(struct r600_common_context *rctx)
63 {
64 struct r600_atom *begin = &rctx->streamout.begin_atom;
65 unsigned num_bufs = util_bitcount(rctx->streamout.enabled_mask);
66 unsigned num_bufs_appended = util_bitcount(rctx->streamout.enabled_mask &
67 rctx->streamout.append_bitmask);
68
69 if (!num_bufs)
70 return;
71
72 rctx->streamout.num_dw_for_end =
73 12 + /* flush_vgt_streamout */
74 num_bufs * 11; /* STRMOUT_BUFFER_UPDATE, BUFFER_SIZE */
75
76 begin->num_dw = 12; /* flush_vgt_streamout */
77
78 begin->num_dw += num_bufs * 7; /* SET_CONTEXT_REG */
79
80 if (rctx->family >= CHIP_RS780 && rctx->family <= CHIP_RV740)
81 begin->num_dw += num_bufs * 5; /* STRMOUT_BASE_UPDATE */
82
83 begin->num_dw +=
84 num_bufs_appended * 8 + /* STRMOUT_BUFFER_UPDATE */
85 (num_bufs - num_bufs_appended) * 6 + /* STRMOUT_BUFFER_UPDATE */
86 (rctx->family > CHIP_R600 && rctx->family < CHIP_RS780 ? 2 : 0); /* SURFACE_BASE_UPDATE */
87
88 rctx->set_atom_dirty(rctx, begin, true);
89
90 r600_set_streamout_enable(rctx, true);
91 }
92
r600_set_streamout_targets(struct pipe_context * ctx,unsigned num_targets,struct pipe_stream_output_target ** targets,const unsigned * offsets,enum mesa_prim output_prim)93 void r600_set_streamout_targets(struct pipe_context *ctx,
94 unsigned num_targets,
95 struct pipe_stream_output_target **targets,
96 const unsigned *offsets,
97 enum mesa_prim output_prim)
98 {
99 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
100 unsigned i;
101 unsigned enabled_mask = 0, append_bitmask = 0;
102
103 /* Stop streamout. */
104 if (rctx->streamout.num_targets && rctx->streamout.begin_emitted) {
105 r600_emit_streamout_end(rctx);
106 }
107
108 /* Set the new targets. */
109 for (i = 0; i < num_targets; i++) {
110 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], targets[i]);
111 if (!targets[i])
112 continue;
113
114 r600_context_add_resource_size(ctx, targets[i]->buffer);
115 enabled_mask |= 1 << i;
116 if (offsets[i] == ((unsigned)-1))
117 append_bitmask |= 1 << i;
118 }
119 for (; i < rctx->streamout.num_targets; i++) {
120 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], NULL);
121 }
122
123 rctx->streamout.enabled_mask = enabled_mask;
124
125 rctx->streamout.num_targets = num_targets;
126 rctx->streamout.append_bitmask = append_bitmask;
127
128 if (num_targets) {
129 r600_streamout_buffers_dirty(rctx);
130 } else {
131 rctx->set_atom_dirty(rctx, &rctx->streamout.begin_atom, false);
132 r600_set_streamout_enable(rctx, false);
133 }
134 }
135
r600_flush_vgt_streamout(struct r600_common_context * rctx)136 static void r600_flush_vgt_streamout(struct r600_common_context *rctx)
137 {
138 struct radeon_cmdbuf *cs = &rctx->gfx.cs;
139 unsigned reg_strmout_cntl;
140
141 /* The register is at different places on different ASICs. */
142 if (rctx->gfx_level >= EVERGREEN) {
143 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
144 } else {
145 reg_strmout_cntl = R_008490_CP_STRMOUT_CNTL;
146 }
147
148 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
149
150 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
151 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
152
153 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
154 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
155 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
156 radeon_emit(cs, 0);
157 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
158 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
159 radeon_emit(cs, 4); /* poll interval */
160 }
161
r600_emit_streamout_begin(struct r600_common_context * rctx,struct r600_atom * atom)162 static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r600_atom *atom)
163 {
164 struct radeon_cmdbuf *cs = &rctx->gfx.cs;
165 struct r600_so_target **t = rctx->streamout.targets;
166 uint16_t *stride_in_dw = rctx->streamout.stride_in_dw;
167 unsigned i, update_flags = 0;
168
169 r600_flush_vgt_streamout(rctx);
170
171 for (i = 0; i < rctx->streamout.num_targets; i++) {
172 if (!t[i])
173 continue;
174
175 t[i]->stride_in_dw = stride_in_dw[i];
176
177 uint64_t va = r600_resource(t[i]->b.buffer)->gpu_address;
178
179 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
180
181 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
182 radeon_emit(cs, (t[i]->b.buffer_offset +
183 t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
184 radeon_emit(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
185 radeon_emit(cs, va >> 8); /* BUFFER_BASE */
186
187 r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer),
188 RADEON_USAGE_WRITE | RADEON_PRIO_SHADER_RW_BUFFER);
189
190 /* R7xx requires this packet after updating BUFFER_BASE.
191 * Without this, R7xx locks up. */
192 if (rctx->family >= CHIP_RS780 && rctx->family <= CHIP_RV740) {
193 radeon_emit(cs, PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0));
194 radeon_emit(cs, i);
195 radeon_emit(cs, va >> 8);
196
197 r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer),
198 RADEON_USAGE_WRITE | RADEON_PRIO_SHADER_RW_BUFFER);
199 }
200
201 if (rctx->streamout.append_bitmask & (1 << i) && t[i]->buf_filled_size_valid) {
202 uint64_t va = t[i]->buf_filled_size->gpu_address +
203 t[i]->buf_filled_size_offset;
204
205 /* Append. */
206 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
207 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
208 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
209 radeon_emit(cs, 0); /* unused */
210 radeon_emit(cs, 0); /* unused */
211 radeon_emit(cs, va); /* src address lo */
212 radeon_emit(cs, va >> 32); /* src address hi */
213
214 r600_emit_reloc(rctx, &rctx->gfx, t[i]->buf_filled_size,
215 RADEON_USAGE_READ | RADEON_PRIO_SO_FILLED_SIZE);
216 } else {
217 /* Start from the beginning. */
218 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
219 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
220 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
221 radeon_emit(cs, 0); /* unused */
222 radeon_emit(cs, 0); /* unused */
223 radeon_emit(cs, t[i]->b.buffer_offset >> 2); /* buffer offset in DW */
224 radeon_emit(cs, 0); /* unused */
225 }
226 }
227
228 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770) {
229 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
230 radeon_emit(cs, update_flags);
231 }
232 rctx->streamout.begin_emitted = true;
233 }
234
r600_emit_streamout_end(struct r600_common_context * rctx)235 void r600_emit_streamout_end(struct r600_common_context *rctx)
236 {
237 struct radeon_cmdbuf *cs = &rctx->gfx.cs;
238 struct r600_so_target **t = rctx->streamout.targets;
239 unsigned i;
240 uint64_t va;
241
242 r600_flush_vgt_streamout(rctx);
243
244 for (i = 0; i < rctx->streamout.num_targets; i++) {
245 if (!t[i])
246 continue;
247
248 va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
249 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
250 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
251 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
252 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
253 radeon_emit(cs, va); /* dst address lo */
254 radeon_emit(cs, va >> 32); /* dst address hi */
255 radeon_emit(cs, 0); /* unused */
256 radeon_emit(cs, 0); /* unused */
257
258 r600_emit_reloc(rctx, &rctx->gfx, t[i]->buf_filled_size,
259 RADEON_USAGE_WRITE | RADEON_PRIO_SO_FILLED_SIZE);
260
261 /* Zero the buffer size. The counters (primitives generated,
262 * primitives emitted) may be enabled even if there is not
263 * buffer bound. This ensures that the primitives-emitted query
264 * won't increment. */
265 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
266
267 t[i]->buf_filled_size_valid = true;
268 }
269
270 rctx->streamout.begin_emitted = false;
271 rctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
272 }
273
274 /* STREAMOUT CONFIG DERIVED STATE
275 *
276 * Streamout must be enabled for the PRIMITIVES_GENERATED query to work.
277 * The buffer mask is an independent state, so no writes occur if there
278 * are no buffers bound.
279 */
280
r600_emit_streamout_enable(struct r600_common_context * rctx,struct r600_atom * atom)281 static void r600_emit_streamout_enable(struct r600_common_context *rctx,
282 struct r600_atom *atom)
283 {
284 unsigned strmout_config_reg = R_028AB0_VGT_STRMOUT_EN;
285 unsigned strmout_config_val = S_028B94_STREAMOUT_0_EN(r600_get_strmout_en(rctx));
286 unsigned strmout_buffer_reg = R_028B20_VGT_STRMOUT_BUFFER_EN;
287 unsigned strmout_buffer_val = rctx->streamout.hw_enabled_mask &
288 rctx->streamout.enabled_stream_buffers_mask;
289
290 if (rctx->gfx_level >= EVERGREEN) {
291 strmout_buffer_reg = R_028B98_VGT_STRMOUT_BUFFER_CONFIG;
292
293 strmout_config_reg = R_028B94_VGT_STRMOUT_CONFIG;
294 strmout_config_val |=
295 S_028B94_STREAMOUT_1_EN(r600_get_strmout_en(rctx)) |
296 S_028B94_STREAMOUT_2_EN(r600_get_strmout_en(rctx)) |
297 S_028B94_STREAMOUT_3_EN(r600_get_strmout_en(rctx));
298 }
299 radeon_set_context_reg(&rctx->gfx.cs, strmout_buffer_reg, strmout_buffer_val);
300 radeon_set_context_reg(&rctx->gfx.cs, strmout_config_reg, strmout_config_val);
301 }
302
r600_set_streamout_enable(struct r600_common_context * rctx,bool enable)303 static void r600_set_streamout_enable(struct r600_common_context *rctx, bool enable)
304 {
305 bool old_strmout_en = r600_get_strmout_en(rctx);
306 unsigned old_hw_enabled_mask = rctx->streamout.hw_enabled_mask;
307
308 rctx->streamout.streamout_enabled = enable;
309
310 rctx->streamout.hw_enabled_mask = rctx->streamout.enabled_mask |
311 (rctx->streamout.enabled_mask << 4) |
312 (rctx->streamout.enabled_mask << 8) |
313 (rctx->streamout.enabled_mask << 12);
314
315 if ((old_strmout_en != r600_get_strmout_en(rctx)) ||
316 (old_hw_enabled_mask != rctx->streamout.hw_enabled_mask)) {
317 rctx->set_atom_dirty(rctx, &rctx->streamout.enable_atom, true);
318 }
319 }
320
r600_update_prims_generated_query_state(struct r600_common_context * rctx,unsigned type,int diff)321 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
322 unsigned type, int diff)
323 {
324 if (type == PIPE_QUERY_PRIMITIVES_GENERATED) {
325 bool old_strmout_en = r600_get_strmout_en(rctx);
326
327 rctx->streamout.num_prims_gen_queries += diff;
328 assert(rctx->streamout.num_prims_gen_queries >= 0);
329
330 rctx->streamout.prims_gen_query_enabled =
331 rctx->streamout.num_prims_gen_queries != 0;
332
333 if (old_strmout_en != r600_get_strmout_en(rctx)) {
334 rctx->set_atom_dirty(rctx, &rctx->streamout.enable_atom, true);
335 }
336 }
337 }
338
r600_streamout_init(struct r600_common_context * rctx)339 void r600_streamout_init(struct r600_common_context *rctx)
340 {
341 rctx->b.create_stream_output_target = r600_create_so_target;
342 rctx->b.stream_output_target_destroy = r600_so_target_destroy;
343 rctx->streamout.begin_atom.emit = r600_emit_streamout_begin;
344 rctx->streamout.enable_atom.emit = r600_emit_streamout_enable;
345 rctx->streamout.enable_atom.num_dw = 6;
346 }
347