1 /*
2 * Copyright 2025 Advanced Micro Devices, Inc.
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7 #include "radeon_bitstream.h"
8
9 static const uint32_t index_to_shifts[4] = {24, 16, 8, 0};
10
radeon_bs_output_one_byte(struct radeon_bitstream * bs,uint8_t byte)11 static void radeon_bs_output_one_byte(struct radeon_bitstream *bs, uint8_t byte)
12 {
13 if (bs->buf) {
14 *(bs->buf++) = byte;
15 return;
16 }
17
18 if (bs->byte_index == 0)
19 bs->cs->current.buf[bs->cs->current.cdw] = 0;
20 bs->cs->current.buf[bs->cs->current.cdw] |=
21 ((uint32_t)(byte) << index_to_shifts[bs->byte_index]);
22 bs->byte_index++;
23
24 if (bs->byte_index >= 4) {
25 bs->byte_index = 0;
26 bs->cs->current.cdw++;
27 }
28 }
29
radeon_bs_emulation_prevention(struct radeon_bitstream * bs,uint8_t byte)30 static void radeon_bs_emulation_prevention(struct radeon_bitstream *bs, uint8_t byte)
31 {
32 if (bs->emulation_prevention) {
33 if ((bs->num_zeros >= 2) && ((byte == 0x00) || (byte == 0x01) ||
34 (byte == 0x02) || (byte == 0x03))) {
35 radeon_bs_output_one_byte(bs, 0x03);
36 bs->bits_output += 8;
37 bs->num_zeros = 0;
38 }
39 bs->num_zeros = (byte == 0 ? (bs->num_zeros + 1) : 0);
40 }
41 }
42
radeon_bs_reset(struct radeon_bitstream * bs,uint8_t * out,struct radeon_cmdbuf * cs)43 void radeon_bs_reset(struct radeon_bitstream *bs, uint8_t *out, struct radeon_cmdbuf *cs)
44 {
45 memset(bs, 0, sizeof(*bs));
46 bs->buf = out;
47 bs->cs = cs;
48 }
49
radeon_bs_set_emulation_prevention(struct radeon_bitstream * bs,bool set)50 void radeon_bs_set_emulation_prevention(struct radeon_bitstream *bs, bool set)
51 {
52 if (set != bs->emulation_prevention) {
53 bs->emulation_prevention = set;
54 bs->num_zeros = 0;
55 }
56 }
57
radeon_bs_byte_align(struct radeon_bitstream * bs)58 void radeon_bs_byte_align(struct radeon_bitstream *bs)
59 {
60 uint32_t num_padding_zeros = (32 - bs->bits_in_shifter) % 8;
61
62 if (num_padding_zeros > 0)
63 radeon_bs_code_fixed_bits(bs, 0, num_padding_zeros);
64 }
65
radeon_bs_flush_headers(struct radeon_bitstream * bs)66 void radeon_bs_flush_headers(struct radeon_bitstream *bs)
67 {
68 if (bs->bits_in_shifter != 0) {
69 uint8_t output_byte = bs->shifter >> 24;
70 radeon_bs_emulation_prevention(bs, output_byte);
71 radeon_bs_output_one_byte(bs, output_byte);
72 bs->bits_output += bs->bits_in_shifter;
73 bs->shifter = 0;
74 bs->bits_in_shifter = 0;
75 bs->num_zeros = 0;
76 }
77
78 if (bs->byte_index > 0) {
79 bs->cs->current.cdw++;
80 bs->byte_index = 0;
81 }
82 }
83
radeon_bs_code_fixed_bits(struct radeon_bitstream * bs,uint32_t value,uint32_t num_bits)84 void radeon_bs_code_fixed_bits(struct radeon_bitstream *bs, uint32_t value, uint32_t num_bits)
85 {
86 uint32_t bits_to_pack = 0;
87 bs->bits_size += num_bits;
88
89 while (num_bits > 0) {
90 uint32_t value_to_pack = value & (0xffffffff >> (32 - num_bits));
91 bits_to_pack =
92 num_bits > (32 - bs->bits_in_shifter) ? (32 - bs->bits_in_shifter) : num_bits;
93
94 if (bits_to_pack < num_bits)
95 value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
96
97 bs->shifter |= value_to_pack << (32 - bs->bits_in_shifter - bits_to_pack);
98 num_bits -= bits_to_pack;
99 bs->bits_in_shifter += bits_to_pack;
100
101 while (bs->bits_in_shifter >= 8) {
102 uint8_t output_byte = bs->shifter >> 24;
103 bs->shifter <<= 8;
104 radeon_bs_emulation_prevention(bs, output_byte);
105 radeon_bs_output_one_byte(bs, output_byte);
106 bs->bits_in_shifter -= 8;
107 bs->bits_output += 8;
108 }
109 }
110 }
111
radeon_bs_code_ue(struct radeon_bitstream * bs,uint32_t value)112 void radeon_bs_code_ue(struct radeon_bitstream *bs, uint32_t value)
113 {
114 uint32_t x = 0;
115 uint32_t ue_code = value + 1;
116 value += 1;
117
118 while (value) {
119 value = value >> 1;
120 x += 1;
121 }
122
123 if (x > 1)
124 radeon_bs_code_fixed_bits(bs, 0, x - 1);
125 radeon_bs_code_fixed_bits(bs, ue_code, x);
126 }
127
radeon_bs_code_se(struct radeon_bitstream * bs,int32_t value)128 void radeon_bs_code_se(struct radeon_bitstream *bs, int32_t value)
129 {
130 uint32_t v = 0;
131
132 if (value != 0)
133 v = (value < 0 ? ((uint32_t)(0 - value) << 1) : (((uint32_t)(value) << 1) - 1));
134
135 radeon_bs_code_ue(bs, v);
136 }
137
radeon_bs_code_uvlc(struct radeon_bitstream * bs,uint32_t value)138 void radeon_bs_code_uvlc(struct radeon_bitstream *bs, uint32_t value)
139 {
140 uint32_t num_bits = 0;
141 uint64_t value_plus1 = (uint64_t)value + 1;
142 uint32_t num_leading_zeros = 0;
143
144 while ((uint64_t)1 << num_bits <= value_plus1)
145 num_bits++;
146
147 num_leading_zeros = num_bits - 1;
148 radeon_bs_code_fixed_bits(bs, 0, num_leading_zeros);
149 radeon_bs_code_fixed_bits(bs, 1, 1);
150 radeon_bs_code_fixed_bits(bs, (uint32_t)value_plus1, num_leading_zeros);
151 }
152
radeon_bs_code_ns(struct radeon_bitstream * bs,uint32_t value,uint32_t max)153 void radeon_bs_code_ns(struct radeon_bitstream *bs, uint32_t value, uint32_t max)
154 {
155 uint32_t w = 0;
156 uint32_t m;
157 uint32_t max_num = max;
158
159 while ( max_num ) {
160 max_num >>= 1;
161 w++;
162 }
163
164 m = (1 << w) - max;
165
166 assert(w > 1);
167
168 if (value < m) {
169 radeon_bs_code_fixed_bits(bs, value, (w - 1));
170 } else {
171 uint32_t diff = value - m;
172 uint32_t out = (((diff >> 1) + m) << 1) | (diff & 0x1);
173 radeon_bs_code_fixed_bits(bs, out, w);
174 }
175 }
176
radeon_bs_h264_hrd_parameters(struct radeon_bitstream * bs,struct pipe_h264_enc_hrd_params * hrd)177 void radeon_bs_h264_hrd_parameters(struct radeon_bitstream *bs,
178 struct pipe_h264_enc_hrd_params *hrd)
179 {
180 radeon_bs_code_ue(bs, hrd->cpb_cnt_minus1);
181 radeon_bs_code_fixed_bits(bs, hrd->bit_rate_scale, 4);
182 radeon_bs_code_fixed_bits(bs, hrd->cpb_size_scale, 4);
183 for (uint32_t i = 0; i <= hrd->cpb_cnt_minus1; i++) {
184 radeon_bs_code_ue(bs, hrd->bit_rate_value_minus1[i]);
185 radeon_bs_code_ue(bs, hrd->cpb_size_value_minus1[i]);
186 radeon_bs_code_fixed_bits(bs, hrd->cbr_flag[i], 1);
187 }
188 radeon_bs_code_fixed_bits(bs, hrd->initial_cpb_removal_delay_length_minus1, 5);
189 radeon_bs_code_fixed_bits(bs, hrd->cpb_removal_delay_length_minus1, 5);
190 radeon_bs_code_fixed_bits(bs, hrd->dpb_output_delay_length_minus1, 5);
191 radeon_bs_code_fixed_bits(bs, hrd->time_offset_length, 5);
192 }
193
radeon_bs_hevc_profile_tier(struct radeon_bitstream * bs,struct pipe_h265_profile_tier * pt)194 static void radeon_bs_hevc_profile_tier(struct radeon_bitstream *bs,
195 struct pipe_h265_profile_tier *pt)
196 {
197 radeon_bs_code_fixed_bits(bs, pt->general_profile_space, 2);
198 radeon_bs_code_fixed_bits(bs, pt->general_tier_flag, 1);
199 radeon_bs_code_fixed_bits(bs, pt->general_profile_idc, 5);
200 radeon_bs_code_fixed_bits(bs, pt->general_profile_compatibility_flag, 32);
201 radeon_bs_code_fixed_bits(bs, pt->general_progressive_source_flag, 1);
202 radeon_bs_code_fixed_bits(bs, pt->general_interlaced_source_flag, 1);
203 radeon_bs_code_fixed_bits(bs, pt->general_non_packed_constraint_flag, 1);
204 radeon_bs_code_fixed_bits(bs, pt->general_frame_only_constraint_flag, 1);
205 /* general_reserved_zero_44bits */
206 radeon_bs_code_fixed_bits(bs, 0x0, 16);
207 radeon_bs_code_fixed_bits(bs, 0x0, 16);
208 radeon_bs_code_fixed_bits(bs, 0x0, 12);
209 }
210
radeon_bs_hevc_profile_tier_level(struct radeon_bitstream * bs,uint32_t max_num_sub_layers_minus1,struct pipe_h265_profile_tier_level * ptl)211 void radeon_bs_hevc_profile_tier_level(struct radeon_bitstream *bs,
212 uint32_t max_num_sub_layers_minus1,
213 struct pipe_h265_profile_tier_level *ptl)
214 {
215 uint32_t i;
216
217 radeon_bs_hevc_profile_tier(bs, &ptl->profile_tier);
218 radeon_bs_code_fixed_bits(bs, ptl->general_level_idc, 8);
219
220 for (i = 0; i < max_num_sub_layers_minus1; ++i) {
221 radeon_bs_code_fixed_bits(bs, ptl->sub_layer_profile_present_flag[i], 1);
222 radeon_bs_code_fixed_bits(bs, ptl->sub_layer_level_present_flag[i], 1);
223 }
224
225 if (max_num_sub_layers_minus1 > 0) {
226 for (i = max_num_sub_layers_minus1; i < 8; ++i)
227 radeon_bs_code_fixed_bits(bs, 0x0, 2); /* reserved_zero_2bits */
228 }
229
230 for (i = 0; i < max_num_sub_layers_minus1; ++i) {
231 if (ptl->sub_layer_profile_present_flag[i])
232 radeon_bs_hevc_profile_tier(bs, &ptl->sub_layer_profile_tier[i]);
233
234 if (ptl->sub_layer_level_present_flag[i])
235 radeon_bs_code_fixed_bits(bs, ptl->sub_layer_level_idc[i], 8);
236 }
237 }
238
radeon_bs_hevc_sub_layer_hrd_parameters(struct radeon_bitstream * bs,uint32_t cpb_cnt,uint32_t sub_pic_hrd_params_present_flag,struct pipe_h265_enc_sublayer_hrd_params * hrd)239 static void radeon_bs_hevc_sub_layer_hrd_parameters(struct radeon_bitstream *bs,
240 uint32_t cpb_cnt,
241 uint32_t sub_pic_hrd_params_present_flag,
242 struct pipe_h265_enc_sublayer_hrd_params *hrd)
243 {
244 for (uint32_t i = 0; i < cpb_cnt; i++) {
245 radeon_bs_code_ue(bs, hrd->bit_rate_value_minus1[i]);
246 radeon_bs_code_ue(bs, hrd->cpb_size_value_minus1[i]);
247 if (sub_pic_hrd_params_present_flag) {
248 radeon_bs_code_ue(bs, hrd->cpb_size_du_value_minus1[i]);
249 radeon_bs_code_ue(bs, hrd->bit_rate_du_value_minus1[i]);
250 }
251 radeon_bs_code_fixed_bits(bs, hrd->cbr_flag[i], 1);
252 }
253 }
254
radeon_bs_hevc_hrd_parameters(struct radeon_bitstream * bs,uint32_t common_inf_present_flag,uint32_t max_sub_layers_minus1,struct pipe_h265_enc_hrd_params * hrd)255 void radeon_bs_hevc_hrd_parameters(struct radeon_bitstream *bs,
256 uint32_t common_inf_present_flag,
257 uint32_t max_sub_layers_minus1,
258 struct pipe_h265_enc_hrd_params *hrd)
259 {
260 if (common_inf_present_flag) {
261 radeon_bs_code_fixed_bits(bs, hrd->nal_hrd_parameters_present_flag, 1);
262 radeon_bs_code_fixed_bits(bs, hrd->vcl_hrd_parameters_present_flag, 1);
263 if (hrd->nal_hrd_parameters_present_flag || hrd->vcl_hrd_parameters_present_flag) {
264 radeon_bs_code_fixed_bits(bs, hrd->sub_pic_hrd_params_present_flag, 1);
265 if (hrd->sub_pic_hrd_params_present_flag) {
266 radeon_bs_code_fixed_bits(bs, hrd->tick_divisor_minus2, 8);
267 radeon_bs_code_fixed_bits(bs, hrd->du_cpb_removal_delay_increment_length_minus1, 5);
268 radeon_bs_code_fixed_bits(bs, hrd->sub_pic_hrd_params_present_flag, 1);
269 radeon_bs_code_fixed_bits(bs, hrd->dpb_output_delay_du_length_minus1, 5);
270 }
271 radeon_bs_code_fixed_bits(bs, hrd->bit_rate_scale, 4);
272 radeon_bs_code_fixed_bits(bs, hrd->cpb_rate_scale, 4);
273 if (hrd->sub_pic_hrd_params_present_flag)
274 radeon_bs_code_fixed_bits(bs, hrd->cpb_size_du_scale, 4);
275 radeon_bs_code_fixed_bits(bs, hrd->initial_cpb_removal_delay_length_minus1, 5);
276 radeon_bs_code_fixed_bits(bs, hrd->au_cpb_removal_delay_length_minus1, 5);
277 radeon_bs_code_fixed_bits(bs, hrd->dpb_output_delay_length_minus1, 5);
278 }
279 }
280
281 for (uint32_t i = 0; i <= max_sub_layers_minus1; i++) {
282 radeon_bs_code_fixed_bits(bs, hrd->fixed_pic_rate_general_flag[i], 1);
283 if (!hrd->fixed_pic_rate_general_flag[i])
284 radeon_bs_code_fixed_bits(bs, hrd->fixed_pic_rate_within_cvs_flag[i], 1);
285 if (hrd->fixed_pic_rate_within_cvs_flag[i])
286 radeon_bs_code_ue(bs, hrd->elemental_duration_in_tc_minus1[i]);
287 else
288 radeon_bs_code_fixed_bits(bs, hrd->low_delay_hrd_flag[i], 1);
289 if (!hrd->low_delay_hrd_flag[i])
290 radeon_bs_code_ue(bs, hrd->cpb_cnt_minus1[i]);
291 if (hrd->nal_hrd_parameters_present_flag) {
292 radeon_bs_hevc_sub_layer_hrd_parameters(bs,
293 hrd->cpb_cnt_minus1[i] + 1,
294 hrd->sub_pic_hrd_params_present_flag,
295 &hrd->nal_hrd_parameters[i]);
296 }
297 if (hrd->vcl_hrd_parameters_present_flag) {
298 radeon_bs_hevc_sub_layer_hrd_parameters(bs,
299 hrd->cpb_cnt_minus1[i] + 1,
300 hrd->sub_pic_hrd_params_present_flag,
301 &hrd->vlc_hrd_parameters[i]);
302 }
303 }
304 }
305
306 /* returns NumPicTotalCurr */
radeon_bs_hevc_st_ref_pic_set(struct radeon_bitstream * bs,uint32_t index,uint32_t num_short_term_ref_pic_sets,struct pipe_h265_st_ref_pic_set * st_rps)307 uint32_t radeon_bs_hevc_st_ref_pic_set(struct radeon_bitstream *bs,
308 uint32_t index,
309 uint32_t num_short_term_ref_pic_sets,
310 struct pipe_h265_st_ref_pic_set *st_rps)
311 {
312 struct pipe_h265_st_ref_pic_set *ref_rps = NULL;
313 struct pipe_h265_st_ref_pic_set *rps = &st_rps[index];
314 uint32_t i, num_pic_total_curr = 0;
315
316 if (index)
317 radeon_bs_code_fixed_bits(bs, rps->inter_ref_pic_set_prediction_flag, 1);
318
319 if (rps->inter_ref_pic_set_prediction_flag) {
320 if (index == num_short_term_ref_pic_sets)
321 radeon_bs_code_ue(bs, rps->delta_idx_minus1);
322 radeon_bs_code_fixed_bits(bs, rps->delta_rps_sign, 1);
323 radeon_bs_code_ue(bs, rps->abs_delta_rps_minus1);
324 ref_rps = st_rps + index +
325 (1 - 2 * rps->delta_rps_sign) * (st_rps->delta_idx_minus1 + 1);
326 for (i = 0; i <= (ref_rps->num_negative_pics + ref_rps->num_positive_pics); i++) {
327 radeon_bs_code_fixed_bits(bs, rps->used_by_curr_pic_flag[i], 1);
328 if (!rps->used_by_curr_pic_flag[i])
329 radeon_bs_code_fixed_bits(bs, rps->use_delta_flag[i], 1);
330 }
331 } else {
332 radeon_bs_code_ue(bs, rps->num_negative_pics);
333 radeon_bs_code_ue(bs, rps->num_positive_pics);
334 for (i = 0; i < rps->num_negative_pics; i++) {
335 radeon_bs_code_ue(bs, rps->delta_poc_s0_minus1[i]);
336 radeon_bs_code_fixed_bits(bs, rps->used_by_curr_pic_s0_flag[i], 1);
337 if (rps->used_by_curr_pic_s0_flag[i])
338 num_pic_total_curr++;
339 }
340 for (i = 0; i < st_rps->num_positive_pics; i++) {
341 radeon_bs_code_ue(bs, rps->delta_poc_s1_minus1[i]);
342 radeon_bs_code_fixed_bits(bs, rps->used_by_curr_pic_s1_flag[i], 1);
343 if (rps->used_by_curr_pic_s1_flag[i])
344 num_pic_total_curr++;
345 }
346 }
347
348 return num_pic_total_curr;
349 }
350