1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * SPDX-License-Identifier: MIT 5 */ 6 7 #ifndef RADEON_BITSTREAM_H 8 #define RADEON_BITSTREAM_H 9 10 #include "pipe/p_video_state.h" 11 #include "winsys/radeon_winsys.h" 12 13 struct radeon_bitstream { 14 bool emulation_prevention; 15 uint32_t shifter; 16 uint32_t bits_in_shifter; 17 uint32_t num_zeros; 18 uint32_t byte_index; 19 uint32_t bits_output; 20 uint32_t bits_size; 21 uint8_t *buf; 22 struct radeon_cmdbuf *cs; 23 }; 24 25 void radeon_bs_reset(struct radeon_bitstream *bs, uint8_t *out, struct radeon_cmdbuf *cs); 26 void radeon_bs_set_emulation_prevention(struct radeon_bitstream *bs, bool set); 27 void radeon_bs_byte_align(struct radeon_bitstream *bs); 28 void radeon_bs_flush_headers(struct radeon_bitstream *bs); 29 30 void radeon_bs_code_fixed_bits(struct radeon_bitstream *bs, uint32_t value, uint32_t num_bits); 31 void radeon_bs_code_ue(struct radeon_bitstream *bs, uint32_t value); 32 void radeon_bs_code_se(struct radeon_bitstream *bs, int32_t value); 33 void radeon_bs_code_uvlc(struct radeon_bitstream *bs, uint32_t value); 34 void radeon_bs_code_ns(struct radeon_bitstream *bs, uint32_t value, uint32_t max); 35 36 void radeon_bs_h264_hrd_parameters(struct radeon_bitstream *bs, 37 struct pipe_h264_enc_hrd_params *hrd); 38 39 void radeon_bs_hevc_profile_tier_level(struct radeon_bitstream *bs, 40 uint32_t max_num_sub_layers_minus1, 41 struct pipe_h265_profile_tier_level *ptl); 42 43 void radeon_bs_hevc_hrd_parameters(struct radeon_bitstream *bs, 44 uint32_t common_inf_present_flag, 45 uint32_t max_sub_layers_minus1, 46 struct pipe_h265_enc_hrd_params *hrd); 47 48 uint32_t radeon_bs_hevc_st_ref_pic_set(struct radeon_bitstream *bs, 49 uint32_t index, 50 uint32_t num_short_term_ref_pic_sets, 51 struct pipe_h265_st_ref_pic_set *st_rps); 52 53 #endif 54