1 /************************************************************************** 2 * 3 * Copyright 2017 Advanced Micro Devices, Inc. 4 * 5 * SPDX-License-Identifier: MIT 6 * 7 **************************************************************************/ 8 9 #ifndef _RADEON_VCN_DEC_H 10 #define _RADEON_VCN_DEC_H 11 12 #include "radeon_vcn.h" 13 #include "util/list.h" 14 15 #include "ac_vcn_dec.h" 16 17 #define NUM_BUFFERS 4 18 #define MAX_JPEG_INST 64 19 20 #define RADEON_DEC_ERR(fmt, args...) \ 21 do { \ 22 dec->error = true; \ 23 fprintf(stderr, "EE %s:%d %s VCN - " fmt, __FILE__, __LINE__, __func__, ##args); \ 24 } while(0) 25 26 struct rvcn_dec_dynamic_dpb_t2 { 27 struct list_head list; 28 uint8_t index; 29 struct pipe_video_buffer *vbuf; 30 }; 31 32 struct jpeg_registers { 33 #define RDECODE_JPEG_REG_VER_V1 0 34 #define RDECODE_JPEG_REG_VER_V2 1 35 #define RDECODE_JPEG_REG_VER_V3 2 36 unsigned version; 37 unsigned jpeg_dec_soft_rst; 38 unsigned jrbc_ib_cond_rd_timer; 39 unsigned jrbc_ib_ref_data; 40 unsigned lmi_jpeg_read_64bit_bar_high; 41 unsigned lmi_jpeg_read_64bit_bar_low; 42 unsigned jpeg_rb_base; 43 unsigned jpeg_rb_size; 44 unsigned jpeg_rb_wptr; 45 unsigned jpeg_pitch; 46 unsigned jpeg_uv_pitch; 47 unsigned dec_addr_mode; 48 unsigned dec_y_gfx10_tiling_surface; 49 unsigned dec_uv_gfx10_tiling_surface; 50 unsigned lmi_jpeg_write_64bit_bar_high; 51 unsigned lmi_jpeg_write_64bit_bar_low; 52 unsigned jpeg_tier_cntl2; 53 unsigned jpeg_outbuf_rptr; 54 unsigned jpeg_outbuf_cntl; 55 unsigned jpeg_int_en; 56 unsigned jpeg_cntl; 57 unsigned jpeg_rb_rptr; 58 unsigned jpeg_outbuf_wptr; 59 unsigned jpeg_luma_base0_0; 60 unsigned jpeg_chroma_base0_0; 61 unsigned jpeg_chromav_base0_0; 62 unsigned jpeg_index; 63 unsigned jpeg_data; 64 }; 65 66 struct radeon_decoder { 67 struct pipe_video_codec base; 68 69 unsigned stream_handle; 70 unsigned stream_type; 71 unsigned frame_number; 72 unsigned db_alignment; 73 unsigned dpb_size; 74 unsigned last_width; 75 unsigned last_height; 76 unsigned max_width; 77 unsigned max_height; 78 unsigned addr_gfx_mode; 79 80 struct pipe_screen *screen; 81 struct radeon_winsys *ws; 82 struct radeon_cmdbuf cs; 83 84 void *msg; 85 uint32_t *fb; 86 uint8_t *it; 87 uint8_t *probs; 88 void *bs_ptr; 89 rvcn_decode_buffer_t *decode_buffer; 90 bool vcn_dec_sw_ring; 91 struct rvcn_sq_var sq; 92 93 struct rvid_buffer *msg_fb_it_probs_buffers; 94 unsigned num_dec_bufs; 95 struct rvid_buffer *bs_buffers; 96 struct rvid_buffer dpb; 97 struct rvid_buffer ctx; 98 struct rvid_buffer sessionctx; 99 100 unsigned bs_size; 101 unsigned cur_buffer; 102 void *render_pic_list[32]; 103 unsigned h264_valid_ref_num[17]; 104 unsigned h264_valid_poc_num[34]; 105 unsigned av1_version; 106 bool show_frame; 107 unsigned ref_idx; 108 bool tmz_ctx; 109 struct { 110 unsigned data0; 111 unsigned data1; 112 unsigned cmd; 113 unsigned cntl; 114 } reg; 115 struct jpeg_params jpg; 116 struct jpeg_registers jpg_reg; 117 enum { 118 DPB_MAX_RES = 0, 119 DPB_DYNAMIC_TIER_1, 120 DPB_DYNAMIC_TIER_2 121 } dpb_type; 122 123 struct { 124 enum { 125 CODEC_8_BITS = 0, 126 CODEC_10_BITS, 127 CODEC_12_BITS 128 } bts; 129 uint8_t index; 130 unsigned ref_size; 131 unsigned num_refs; 132 uint8_t ref_list[16]; 133 } ref_codec; 134 135 struct list_head dpb_ref_list; 136 struct list_head dpb_unref_list; 137 138 bool (*send_cmd)(struct radeon_decoder *dec, struct pipe_video_buffer *target, 139 struct pipe_picture_desc *picture); 140 /* Additional contexts for mJPEG */ 141 struct radeon_cmdbuf *jcs; 142 struct radeon_winsys_ctx **jctx; 143 unsigned cb_idx; 144 unsigned njctx; 145 146 bool error; 147 148 struct pipe_context *ectx; 149 }; 150 151 bool send_cmd_dec(struct radeon_decoder *dec, struct pipe_video_buffer *target, 152 struct pipe_picture_desc *picture); 153 154 bool send_cmd_jpeg(struct radeon_decoder *dec, struct pipe_video_buffer *target, 155 struct pipe_picture_desc *picture); 156 157 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context, 158 const struct pipe_video_codec *templat); 159 160 #endif 161