1 /************************************************************************** 2 * 3 * Copyright 2017 Advanced Micro Devices, Inc. 4 * 5 * SPDX-License-Identifier: MIT 6 * 7 **************************************************************************/ 8 9 #include "pipe/p_video_codec.h" 10 #include "radeon_vcn_enc.h" 11 #include "radeon_video.h" 12 #include "si_pipe.h" 13 #include "util/u_video.h" 14 15 #include <stdio.h> 16 17 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1 18 #define RENCODE_FW_INTERFACE_MINOR_VERSION 1 19 radeon_enc_op_preset(struct radeon_encoder * enc)20static void radeon_enc_op_preset(struct radeon_encoder *enc) 21 { 22 uint32_t preset_mode; 23 24 if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_SPEED && 25 (!enc->enc_pic.hevc_deblock.disable_sao && 26 (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC))) 27 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE; 28 else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_QUALITY) 29 preset_mode = RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE; 30 else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_BALANCE) 31 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE; 32 else 33 preset_mode = RENCODE_IB_OP_SET_SPEED_ENCODING_MODE; 34 35 RADEON_ENC_BEGIN(preset_mode); 36 RADEON_ENC_END(); 37 } 38 radeon_enc_quality_params(struct radeon_encoder * enc)39static void radeon_enc_quality_params(struct radeon_encoder *enc) 40 { 41 RADEON_ENC_BEGIN(enc->cmd.quality_params); 42 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode); 43 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity); 44 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval); 45 RADEON_ENC_CS(enc->enc_pic.quality_params.two_pass_search_center_map_mode); 46 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_strength); 47 RADEON_ENC_END(); 48 } 49 radeon_enc_loop_filter_hevc(struct radeon_encoder * enc)50static void radeon_enc_loop_filter_hevc(struct radeon_encoder *enc) 51 { 52 RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc); 53 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled); 54 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled); 55 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2); 56 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2); 57 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset); 58 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset); 59 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.disable_sao); 60 RADEON_ENC_END(); 61 } 62 radeon_enc_input_format(struct radeon_encoder * enc)63static void radeon_enc_input_format(struct radeon_encoder *enc) 64 { 65 RADEON_ENC_BEGIN(enc->cmd.input_format); 66 RADEON_ENC_CS(enc->enc_pic.enc_input_format.input_color_volume); 67 RADEON_ENC_CS(enc->enc_pic.enc_input_format.input_color_space); 68 RADEON_ENC_CS(enc->enc_pic.enc_input_format.input_color_range); 69 RADEON_ENC_CS(enc->enc_pic.enc_input_format.input_chroma_subsampling); 70 RADEON_ENC_CS(enc->enc_pic.enc_input_format.input_chroma_location); 71 RADEON_ENC_CS(enc->enc_pic.enc_input_format.input_color_bit_depth); 72 RADEON_ENC_CS(enc->enc_pic.enc_input_format.input_color_packing_format); 73 RADEON_ENC_END(); 74 } 75 radeon_enc_output_format(struct radeon_encoder * enc)76static void radeon_enc_output_format(struct radeon_encoder *enc) 77 { 78 RADEON_ENC_BEGIN(enc->cmd.output_format); 79 RADEON_ENC_CS(enc->enc_pic.enc_output_format.output_color_volume); 80 RADEON_ENC_CS(enc->enc_pic.enc_output_format.output_color_range); 81 RADEON_ENC_CS(enc->enc_pic.enc_output_format.output_chroma_location); 82 RADEON_ENC_CS(enc->enc_pic.enc_output_format.output_color_bit_depth); 83 RADEON_ENC_END(); 84 } 85 radeon_enc_ref_swizzle_mode(struct radeon_encoder * enc)86static uint32_t radeon_enc_ref_swizzle_mode(struct radeon_encoder *enc) 87 { 88 /* return RENCODE_REC_SWIZZLE_MODE_LINEAR; for debugging purpose */ 89 if (enc->enc_pic.bit_depth_luma_minus8 != 0) 90 return RENCODE_REC_SWIZZLE_MODE_8x8_1D_THIN_12_24BPP; 91 else 92 return RENCODE_REC_SWIZZLE_MODE_256B_S; 93 } 94 radeon_enc_ctx(struct radeon_encoder * enc)95static void radeon_enc_ctx(struct radeon_encoder *enc) 96 { 97 enc->enc_pic.ctx_buf.swizzle_mode = radeon_enc_ref_swizzle_mode(enc); 98 enc->enc_pic.ctx_buf.two_pass_search_center_map_offset = 0; 99 100 RADEON_ENC_BEGIN(enc->cmd.ctx); 101 RADEON_ENC_READWRITE(enc->dpb->res->buf, enc->dpb->res->domains, 0); 102 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode); 103 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch); 104 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch); 105 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures); 106 107 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) { 108 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset); 109 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset); 110 } 111 112 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_luma_pitch); 113 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_chroma_pitch); 114 115 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) { 116 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_reconstructed_pictures[i].luma_offset); 117 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_reconstructed_pictures[i].chroma_offset); 118 } 119 120 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.yuv.luma_offset); 121 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.yuv.chroma_offset); 122 RADEON_ENC_CS(enc->enc_pic.ctx_buf.two_pass_search_center_map_offset); 123 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.red_offset); 124 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.green_offset); 125 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.blue_offset); 126 127 RADEON_ENC_END(); 128 } 129 radeon_enc_spec_misc_hevc(struct radeon_encoder * enc)130static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc) 131 { 132 RADEON_ENC_BEGIN(enc->cmd.spec_misc_hevc); 133 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3); 134 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled); 135 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled); 136 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag); 137 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag); 138 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled); 139 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled); 140 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cu_qp_delta_enabled_flag); 141 RADEON_ENC_END(); 142 } 143 encode(struct radeon_encoder * enc)144static void encode(struct radeon_encoder *enc) 145 { 146 unsigned i; 147 148 enc->before_encode(enc); 149 enc->session_info(enc); 150 enc->total_task_size = 0; 151 enc->task_info(enc, enc->need_feedback); 152 153 if (enc->need_spec_misc) 154 enc->spec_misc(enc); 155 156 if (enc->need_rate_control || enc->need_rc_per_pic) { 157 i = 0; 158 do { 159 enc->enc_pic.layer_sel.temporal_layer_index = i; 160 if (enc->need_rate_control) { 161 enc->layer_select(enc); 162 enc->rc_layer_init(enc); 163 } 164 if (enc->need_rc_per_pic) { 165 enc->layer_select(enc); 166 enc->rc_per_pic(enc); 167 } 168 } while (++i < enc->enc_pic.num_temporal_layers); 169 } 170 171 enc->enc_pic.layer_sel.temporal_layer_index = enc->enc_pic.temporal_id; 172 enc->layer_select(enc); 173 174 enc->encode_headers(enc); 175 enc->ctx(enc); 176 enc->ctx_override(enc); 177 enc->bitstream(enc); 178 enc->feedback(enc); 179 enc->metadata(enc); 180 enc->encode_statistics(enc); 181 enc->intra_refresh(enc); 182 enc->qp_map(enc); 183 enc->input_format(enc); 184 enc->output_format(enc); 185 186 enc->op_preset(enc); 187 enc->op_enc(enc); 188 *enc->p_task_size = (enc->total_task_size); 189 } 190 radeon_enc_2_0_init(struct radeon_encoder * enc)191void radeon_enc_2_0_init(struct radeon_encoder *enc) 192 { 193 radeon_enc_1_2_init(enc); 194 enc->encode = encode; 195 enc->input_format = radeon_enc_input_format; 196 enc->output_format = radeon_enc_output_format; 197 enc->ctx = radeon_enc_ctx; 198 enc->op_preset = radeon_enc_op_preset; 199 enc->quality_params = radeon_enc_quality_params; 200 enc->ctx_override = radeon_enc_dummy; 201 enc->metadata = radeon_enc_dummy; 202 203 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) { 204 enc->deblocking_filter = radeon_enc_loop_filter_hevc; 205 enc->spec_misc = radeon_enc_spec_misc_hevc; 206 } 207 208 enc->enc_pic.session_info.interface_version = 209 ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) | 210 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT)); 211 } 212