1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 /* 3 * Copyright (c) 2012-2023 Broadcom. All Rights Reserved. The term 4 * "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. 5 * 6 * Permission is hereby granted, free of charge, to any person 7 * obtaining a copy of this software and associated documentation 8 * files (the "Software"), to deal in the Software without 9 * restriction, including without limitation the rights to use, copy, 10 * modify, merge, publish, distribute, sublicense, and/or sell copies 11 * of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be 15 * included in all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 20 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 21 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 22 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 24 * SOFTWARE. 25 * 26 */ 27 28 /* 29 * VGPU10ShaderTokens.h -- 30 * 31 * VGPU10 shader token definitions. 32 */ 33 34 #ifndef VGPU10SHADERTOKENS_H 35 #define VGPU10SHADERTOKENS_H 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 #include "vm_basic_types.h" 42 43 #define VGPU10_MAX_VS_INPUTS 16 44 #define VGPU10_MAX_VS_OUTPUTS 16 45 #define VGPU10_MAX_GS_INPUTS 16 46 #define VGPU10_MAX_GS_OUTPUTS 32 47 #define VGPU10_MAX_PS_INPUTS 32 48 #define VGPU10_MAX_PS_OUTPUTS 8 49 #define VGPU10_MAX_TEMPS 4096 50 #define VGPU10_MAX_CONSTANT_BUFFERS (14 + 1) 51 #define VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT 4096 52 #define VGPU10_MAX_IMMEDIATE_CONSTANT_BUFFER_ELEMENT_COUNT 4096 53 #define VGPU10_MAX_SAMPLERS 16 54 #define VGPU10_MAX_RESOURCES 128 55 #define VGPU10_MIN_TEXEL_FETCH_OFFSET -8 56 #define VGPU10_MAX_TEXEL_FETCH_OFFSET 7 57 58 #define VGPU10_1_MAX_VS_INPUTS 32 59 #define VGPU10_1_MAX_VS_OUTPUTS 32 60 #define VGPU10_1_MAX_GS_INPUTS 32 61 62 #define VGPU11_MAX_HS_INPUT_CONTROL_POINTS 32 63 #define VGPU11_MAX_HS_INPUT_PATCH_CONSTANTS 32 64 #define VGPU11_MAX_HS_OUTPUT_CP_PHASE_ELEMENTS 32 65 #define VGPU11_MAX_HS_OUTPUT_CONTROL_POINTS 32 66 #define VGPU11_MAX_HS_OUTPUTS 32 67 #define VGPU11_MAX_DS_INPUT_CONTROL_POINTS 32 68 #define VGPU11_MAX_DS_INPUT_PATCH_CONSTANTS 32 69 #define VGPU11_MAX_DS_OUTPUTS 32 70 #define VGPU11_MAX_GS_STREAMS 4 71 #define VGPU11_MAX_FUNCTION_BODIES 256 72 #define VGPU11_MAX_FUNCTION_TABLES 256 73 #define VGPU11_MAX_INTERFACES 253 74 75 #define VGPU10_MAX_INPUTS 32 76 #define VGPU10_MAX_OUTPUTS 32 77 #define VGPU10_MAX_INPUT_PATCH_CONSTANTS 32 78 79 typedef enum { 80 VGPU10_PIXEL_SHADER = 0, 81 VGPU10_VERTEX_SHADER = 1, 82 VGPU10_GEOMETRY_SHADER = 2, 83 84 VGPU10_HULL_SHADER = 3, 85 VGPU10_DOMAIN_SHADER = 4, 86 VGPU10_COMPUTE_SHADER = 5 87 } VGPU10_PROGRAM_TYPE; 88 89 typedef union { 90 struct { 91 unsigned int minorVersion : 4; 92 unsigned int majorVersion : 4; 93 unsigned int : 8; 94 unsigned int programType : 16; 95 }; 96 uint32 value; 97 } VGPU10ProgramToken; 98 99 typedef enum { 100 VGPU10_OPCODE_ADD = 0, 101 VGPU10_OPCODE_AND = 1, 102 VGPU10_OPCODE_BREAK = 2, 103 VGPU10_OPCODE_BREAKC = 3, 104 VGPU10_OPCODE_CALL = 4, 105 VGPU10_OPCODE_CALLC = 5, 106 VGPU10_OPCODE_CASE = 6, 107 VGPU10_OPCODE_CONTINUE = 7, 108 VGPU10_OPCODE_CONTINUEC = 8, 109 VGPU10_OPCODE_CUT = 9, 110 VGPU10_OPCODE_DEFAULT = 10, 111 VGPU10_OPCODE_DERIV_RTX = 11, 112 VGPU10_OPCODE_DERIV_RTY = 12, 113 VGPU10_OPCODE_DISCARD = 13, 114 VGPU10_OPCODE_DIV = 14, 115 VGPU10_OPCODE_DP2 = 15, 116 VGPU10_OPCODE_DP3 = 16, 117 VGPU10_OPCODE_DP4 = 17, 118 VGPU10_OPCODE_ELSE = 18, 119 VGPU10_OPCODE_EMIT = 19, 120 VGPU10_OPCODE_EMITTHENCUT = 20, 121 VGPU10_OPCODE_ENDIF = 21, 122 VGPU10_OPCODE_ENDLOOP = 22, 123 VGPU10_OPCODE_ENDSWITCH = 23, 124 VGPU10_OPCODE_EQ = 24, 125 VGPU10_OPCODE_EXP = 25, 126 VGPU10_OPCODE_FRC = 26, 127 VGPU10_OPCODE_FTOI = 27, 128 VGPU10_OPCODE_FTOU = 28, 129 VGPU10_OPCODE_GE = 29, 130 VGPU10_OPCODE_IADD = 30, 131 VGPU10_OPCODE_IF = 31, 132 VGPU10_OPCODE_IEQ = 32, 133 VGPU10_OPCODE_IGE = 33, 134 VGPU10_OPCODE_ILT = 34, 135 VGPU10_OPCODE_IMAD = 35, 136 VGPU10_OPCODE_IMAX = 36, 137 VGPU10_OPCODE_IMIN = 37, 138 VGPU10_OPCODE_IMUL = 38, 139 VGPU10_OPCODE_INE = 39, 140 VGPU10_OPCODE_INEG = 40, 141 VGPU10_OPCODE_ISHL = 41, 142 VGPU10_OPCODE_ISHR = 42, 143 VGPU10_OPCODE_ITOF = 43, 144 VGPU10_OPCODE_LABEL = 44, 145 VGPU10_OPCODE_LD = 45, 146 VGPU10_OPCODE_LD_MS = 46, 147 VGPU10_OPCODE_LOG = 47, 148 VGPU10_OPCODE_LOOP = 48, 149 VGPU10_OPCODE_LT = 49, 150 VGPU10_OPCODE_MAD = 50, 151 VGPU10_OPCODE_MIN = 51, 152 VGPU10_OPCODE_MAX = 52, 153 VGPU10_OPCODE_CUSTOMDATA = 53, 154 VGPU10_OPCODE_MOV = 54, 155 VGPU10_OPCODE_MOVC = 55, 156 VGPU10_OPCODE_MUL = 56, 157 VGPU10_OPCODE_NE = 57, 158 VGPU10_OPCODE_NOP = 58, 159 VGPU10_OPCODE_NOT = 59, 160 VGPU10_OPCODE_OR = 60, 161 VGPU10_OPCODE_RESINFO = 61, 162 VGPU10_OPCODE_RET = 62, 163 VGPU10_OPCODE_RETC = 63, 164 VGPU10_OPCODE_ROUND_NE = 64, 165 VGPU10_OPCODE_ROUND_NI = 65, 166 VGPU10_OPCODE_ROUND_PI = 66, 167 VGPU10_OPCODE_ROUND_Z = 67, 168 VGPU10_OPCODE_RSQ = 68, 169 VGPU10_OPCODE_SAMPLE = 69, 170 VGPU10_OPCODE_SAMPLE_C = 70, 171 VGPU10_OPCODE_SAMPLE_C_LZ = 71, 172 VGPU10_OPCODE_SAMPLE_L = 72, 173 VGPU10_OPCODE_SAMPLE_D = 73, 174 VGPU10_OPCODE_SAMPLE_B = 74, 175 VGPU10_OPCODE_SQRT = 75, 176 VGPU10_OPCODE_SWITCH = 76, 177 VGPU10_OPCODE_SINCOS = 77, 178 VGPU10_OPCODE_UDIV = 78, 179 VGPU10_OPCODE_ULT = 79, 180 VGPU10_OPCODE_UGE = 80, 181 VGPU10_OPCODE_UMUL = 81, 182 VGPU10_OPCODE_UMAD = 82, 183 VGPU10_OPCODE_UMAX = 83, 184 VGPU10_OPCODE_UMIN = 84, 185 VGPU10_OPCODE_USHR = 85, 186 VGPU10_OPCODE_UTOF = 86, 187 VGPU10_OPCODE_XOR = 87, 188 VGPU10_OPCODE_DCL_RESOURCE = 88, 189 VGPU10_OPCODE_DCL_CONSTANT_BUFFER = 89, 190 VGPU10_OPCODE_DCL_SAMPLER = 90, 191 VGPU10_OPCODE_DCL_INDEX_RANGE = 91, 192 VGPU10_OPCODE_DCL_GS_OUTPUT_PRIMITIVE_TOPOLOGY = 92, 193 VGPU10_OPCODE_DCL_GS_INPUT_PRIMITIVE = 93, 194 VGPU10_OPCODE_DCL_MAX_OUTPUT_VERTEX_COUNT = 94, 195 VGPU10_OPCODE_DCL_INPUT = 95, 196 VGPU10_OPCODE_DCL_INPUT_SGV = 96, 197 VGPU10_OPCODE_DCL_INPUT_SIV = 97, 198 VGPU10_OPCODE_DCL_INPUT_PS = 98, 199 VGPU10_OPCODE_DCL_INPUT_PS_SGV = 99, 200 VGPU10_OPCODE_DCL_INPUT_PS_SIV = 100, 201 VGPU10_OPCODE_DCL_OUTPUT = 101, 202 VGPU10_OPCODE_DCL_OUTPUT_SGV = 102, 203 VGPU10_OPCODE_DCL_OUTPUT_SIV = 103, 204 VGPU10_OPCODE_DCL_TEMPS = 104, 205 VGPU10_OPCODE_DCL_INDEXABLE_TEMP = 105, 206 VGPU10_OPCODE_DCL_GLOBAL_FLAGS = 106, 207 208 VGPU10_OPCODE_VMWARE = 107, 209 210 VGPU10_OPCODE_LOD = 108, 211 VGPU10_OPCODE_GATHER4 = 109, 212 VGPU10_OPCODE_SAMPLE_POS = 110, 213 VGPU10_OPCODE_SAMPLE_INFO = 111, 214 215 VGPU10_OPCODE_RESERVED1 = 112, 216 VGPU10_OPCODE_HS_DECLS = 113, 217 VGPU10_OPCODE_HS_CONTROL_POINT_PHASE = 114, 218 VGPU10_OPCODE_HS_FORK_PHASE = 115, 219 VGPU10_OPCODE_HS_JOIN_PHASE = 116, 220 VGPU10_OPCODE_EMIT_STREAM = 117, 221 VGPU10_OPCODE_CUT_STREAM = 118, 222 VGPU10_OPCODE_EMITTHENCUT_STREAM = 119, 223 VGPU10_OPCODE_INTERFACE_CALL = 120, 224 VGPU10_OPCODE_BUFINFO = 121, 225 VGPU10_OPCODE_DERIV_RTX_COARSE = 122, 226 VGPU10_OPCODE_DERIV_RTX_FINE = 123, 227 VGPU10_OPCODE_DERIV_RTY_COARSE = 124, 228 VGPU10_OPCODE_DERIV_RTY_FINE = 125, 229 VGPU10_OPCODE_GATHER4_C = 126, 230 VGPU10_OPCODE_GATHER4_PO = 127, 231 VGPU10_OPCODE_GATHER4_PO_C = 128, 232 VGPU10_OPCODE_RCP = 129, 233 VGPU10_OPCODE_F32TOF16 = 130, 234 VGPU10_OPCODE_F16TOF32 = 131, 235 VGPU10_OPCODE_UADDC = 132, 236 VGPU10_OPCODE_USUBB = 133, 237 VGPU10_OPCODE_COUNTBITS = 134, 238 VGPU10_OPCODE_FIRSTBIT_HI = 135, 239 VGPU10_OPCODE_FIRSTBIT_LO = 136, 240 VGPU10_OPCODE_FIRSTBIT_SHI = 137, 241 VGPU10_OPCODE_UBFE = 138, 242 VGPU10_OPCODE_IBFE = 139, 243 VGPU10_OPCODE_BFI = 140, 244 VGPU10_OPCODE_BFREV = 141, 245 VGPU10_OPCODE_SWAPC = 142, 246 VGPU10_OPCODE_DCL_STREAM = 143, 247 VGPU10_OPCODE_DCL_FUNCTION_BODY = 144, 248 VGPU10_OPCODE_DCL_FUNCTION_TABLE = 145, 249 VGPU10_OPCODE_DCL_INTERFACE = 146, 250 VGPU10_OPCODE_DCL_INPUT_CONTROL_POINT_COUNT = 147, 251 VGPU10_OPCODE_DCL_OUTPUT_CONTROL_POINT_COUNT = 148, 252 VGPU10_OPCODE_DCL_TESS_DOMAIN = 149, 253 VGPU10_OPCODE_DCL_TESS_PARTITIONING = 150, 254 VGPU10_OPCODE_DCL_TESS_OUTPUT_PRIMITIVE = 151, 255 VGPU10_OPCODE_DCL_HS_MAX_TESSFACTOR = 152, 256 VGPU10_OPCODE_DCL_HS_FORK_PHASE_INSTANCE_COUNT = 153, 257 VGPU10_OPCODE_DCL_HS_JOIN_PHASE_INSTANCE_COUNT = 154, 258 VGPU10_OPCODE_DCL_THREAD_GROUP = 155, 259 VGPU10_OPCODE_DCL_UAV_TYPED = 156, 260 VGPU10_OPCODE_DCL_UAV_RAW = 157, 261 VGPU10_OPCODE_DCL_UAV_STRUCTURED = 158, 262 VGPU10_OPCODE_DCL_TGSM_RAW = 159, 263 VGPU10_OPCODE_DCL_TGSM_STRUCTURED = 160, 264 VGPU10_OPCODE_DCL_RESOURCE_RAW = 161, 265 VGPU10_OPCODE_DCL_RESOURCE_STRUCTURED = 162, 266 VGPU10_OPCODE_LD_UAV_TYPED = 163, 267 VGPU10_OPCODE_STORE_UAV_TYPED = 164, 268 VGPU10_OPCODE_LD_RAW = 165, 269 VGPU10_OPCODE_STORE_RAW = 166, 270 VGPU10_OPCODE_LD_STRUCTURED = 167, 271 VGPU10_OPCODE_STORE_STRUCTURED = 168, 272 VGPU10_OPCODE_ATOMIC_AND = 169, 273 VGPU10_OPCODE_ATOMIC_OR = 170, 274 VGPU10_OPCODE_ATOMIC_XOR = 171, 275 VGPU10_OPCODE_ATOMIC_CMP_STORE = 172, 276 VGPU10_OPCODE_ATOMIC_IADD = 173, 277 VGPU10_OPCODE_ATOMIC_IMAX = 174, 278 VGPU10_OPCODE_ATOMIC_IMIN = 175, 279 VGPU10_OPCODE_ATOMIC_UMAX = 176, 280 VGPU10_OPCODE_ATOMIC_UMIN = 177, 281 VGPU10_OPCODE_IMM_ATOMIC_ALLOC = 178, 282 VGPU10_OPCODE_IMM_ATOMIC_CONSUME = 179, 283 VGPU10_OPCODE_IMM_ATOMIC_IADD = 180, 284 VGPU10_OPCODE_IMM_ATOMIC_AND = 181, 285 VGPU10_OPCODE_IMM_ATOMIC_OR = 182, 286 VGPU10_OPCODE_IMM_ATOMIC_XOR = 183, 287 VGPU10_OPCODE_IMM_ATOMIC_EXCH = 184, 288 VGPU10_OPCODE_IMM_ATOMIC_CMP_EXCH = 185, 289 VGPU10_OPCODE_IMM_ATOMIC_IMAX = 186, 290 VGPU10_OPCODE_IMM_ATOMIC_IMIN = 187, 291 VGPU10_OPCODE_IMM_ATOMIC_UMAX = 188, 292 VGPU10_OPCODE_IMM_ATOMIC_UMIN = 189, 293 VGPU10_OPCODE_SYNC = 190, 294 VGPU10_OPCODE_DADD = 191, 295 VGPU10_OPCODE_DMAX = 192, 296 VGPU10_OPCODE_DMIN = 193, 297 VGPU10_OPCODE_DMUL = 194, 298 VGPU10_OPCODE_DEQ = 195, 299 VGPU10_OPCODE_DGE = 196, 300 VGPU10_OPCODE_DLT = 197, 301 VGPU10_OPCODE_DNE = 198, 302 VGPU10_OPCODE_DMOV = 199, 303 VGPU10_OPCODE_DMOVC = 200, 304 VGPU10_OPCODE_DTOF = 201, 305 VGPU10_OPCODE_FTOD = 202, 306 VGPU10_OPCODE_EVAL_SNAPPED = 203, 307 VGPU10_OPCODE_EVAL_SAMPLE_INDEX = 204, 308 VGPU10_OPCODE_EVAL_CENTROID = 205, 309 VGPU10_OPCODE_DCL_GS_INSTANCE_COUNT = 206, 310 VGPU10_OPCODE_ABORT = 207, 311 VGPU10_OPCODE_DEBUG_BREAK = 208, 312 313 VGPU10_OPCODE_RESERVED0 = 209, 314 VGPU10_OPCODE_DDIV = 210, 315 VGPU10_OPCODE_DFMA = 211, 316 VGPU10_OPCODE_DRCP = 212, 317 VGPU10_OPCODE_MSAD = 213, 318 VGPU10_OPCODE_DTOI = 214, 319 VGPU10_OPCODE_DTOU = 215, 320 VGPU10_OPCODE_ITOD = 216, 321 VGPU10_OPCODE_UTOD = 217, 322 323 VGPU10_NUM_OPCODES 324 } VGPU10_OPCODE_TYPE; 325 326 typedef enum { 327 VGPU10_VMWARE_OPCODE_IDIV = 0, 328 VGPU10_VMWARE_OPCODE_DFRC = 1, 329 VGPU10_VMWARE_OPCODE_DRSQ = 2, 330 VGPU10_VMWARE_NUM_OPCODES 331 } VGPU10_VMWARE_OPCODE_TYPE; 332 333 typedef enum { 334 VGPU10_INTERPOLATION_UNDEFINED = 0, 335 VGPU10_INTERPOLATION_CONSTANT = 1, 336 VGPU10_INTERPOLATION_LINEAR = 2, 337 VGPU10_INTERPOLATION_LINEAR_CENTROID = 3, 338 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE = 4, 339 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_CENTROID = 5, 340 VGPU10_INTERPOLATION_LINEAR_SAMPLE = 6, 341 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_SAMPLE = 7 342 } VGPU10_INTERPOLATION_MODE; 343 344 typedef enum { 345 VGPU10_RESOURCE_DIMENSION_UNKNOWN = 0, 346 VGPU10_RESOURCE_DIMENSION_BUFFER = 1, 347 VGPU10_RESOURCE_DIMENSION_TEXTURE1D = 2, 348 VGPU10_RESOURCE_DIMENSION_TEXTURE2D = 3, 349 VGPU10_RESOURCE_DIMENSION_TEXTURE2DMS = 4, 350 VGPU10_RESOURCE_DIMENSION_TEXTURE3D = 5, 351 VGPU10_RESOURCE_DIMENSION_TEXTURECUBE = 6, 352 VGPU10_RESOURCE_DIMENSION_TEXTURE1DARRAY = 7, 353 VGPU10_RESOURCE_DIMENSION_TEXTURE2DARRAY = 8, 354 VGPU10_RESOURCE_DIMENSION_TEXTURE2DMSARRAY = 9, 355 VGPU10_RESOURCE_DIMENSION_TEXTURECUBEARRAY = 10, 356 357 VGPU10_RESOURCE_DIMENSION_RAW_BUFFER = 11, 358 VGPU10_RESOURCE_DIMENSION_STRUCTURED_BUFFER = 12, 359 VGPU10_RESOURCE_DIMENSION_MAX = 12 360 } VGPU10_RESOURCE_DIMENSION; 361 362 typedef enum { 363 VGPU10_SAMPLER_MODE_DEFAULT = 0, 364 VGPU10_SAMPLER_MODE_COMPARISON = 1, 365 VGPU10_SAMPLER_MODE_MONO = 2 366 } VGPU10_SAMPLER_MODE; 367 368 typedef enum { 369 VGPU10_INSTRUCTION_TEST_ZERO = 0, 370 VGPU10_INSTRUCTION_TEST_NONZERO = 1 371 } VGPU10_INSTRUCTION_TEST_BOOLEAN; 372 373 typedef enum { 374 VGPU10_CB_IMMEDIATE_INDEXED = 0, 375 VGPU10_CB_DYNAMIC_INDEXED = 1 376 } VGPU10_CB_ACCESS_PATTERN; 377 378 typedef enum { 379 VGPU10_PRIMITIVE_UNDEFINED = 0, 380 VGPU10_PRIMITIVE_POINT = 1, 381 VGPU10_PRIMITIVE_LINE = 2, 382 VGPU10_PRIMITIVE_TRIANGLE = 3, 383 VGPU10_PRIMITIVE_LINE_ADJ = 6, 384 VGPU10_PRIMITIVE_TRIANGLE_ADJ = 7, 385 VGPU10_PRIMITIVE_SM40_MAX = 7, 386 387 VGPU10_PRIMITIVE_1_CONTROL_POINT_PATCH = 8, 388 VGPU10_PRIMITIVE_2_CONTROL_POINT_PATCH = 9, 389 VGPU10_PRIMITIVE_3_CONTROL_POINT_PATCH = 10, 390 VGPU10_PRIMITIVE_4_CONTROL_POINT_PATCH = 11, 391 VGPU10_PRIMITIVE_5_CONTROL_POINT_PATCH = 12, 392 VGPU10_PRIMITIVE_6_CONTROL_POINT_PATCH = 13, 393 VGPU10_PRIMITIVE_7_CONTROL_POINT_PATCH = 14, 394 VGPU10_PRIMITIVE_8_CONTROL_POINT_PATCH = 15, 395 VGPU10_PRIMITIVE_9_CONTROL_POINT_PATCH = 16, 396 VGPU10_PRIMITIVE_10_CONTROL_POINT_PATCH = 17, 397 VGPU10_PRIMITIVE_11_CONTROL_POINT_PATCH = 18, 398 VGPU10_PRIMITIVE_12_CONTROL_POINT_PATCH = 19, 399 VGPU10_PRIMITIVE_13_CONTROL_POINT_PATCH = 20, 400 VGPU10_PRIMITIVE_14_CONTROL_POINT_PATCH = 21, 401 VGPU10_PRIMITIVE_15_CONTROL_POINT_PATCH = 22, 402 VGPU10_PRIMITIVE_16_CONTROL_POINT_PATCH = 23, 403 VGPU10_PRIMITIVE_17_CONTROL_POINT_PATCH = 24, 404 VGPU10_PRIMITIVE_18_CONTROL_POINT_PATCH = 25, 405 VGPU10_PRIMITIVE_19_CONTROL_POINT_PATCH = 26, 406 VGPU10_PRIMITIVE_20_CONTROL_POINT_PATCH = 27, 407 VGPU10_PRIMITIVE_21_CONTROL_POINT_PATCH = 28, 408 VGPU10_PRIMITIVE_22_CONTROL_POINT_PATCH = 29, 409 VGPU10_PRIMITIVE_23_CONTROL_POINT_PATCH = 30, 410 VGPU10_PRIMITIVE_24_CONTROL_POINT_PATCH = 31, 411 VGPU10_PRIMITIVE_25_CONTROL_POINT_PATCH = 32, 412 VGPU10_PRIMITIVE_26_CONTROL_POINT_PATCH = 33, 413 VGPU10_PRIMITIVE_27_CONTROL_POINT_PATCH = 34, 414 VGPU10_PRIMITIVE_28_CONTROL_POINT_PATCH = 35, 415 VGPU10_PRIMITIVE_29_CONTROL_POINT_PATCH = 36, 416 VGPU10_PRIMITIVE_30_CONTROL_POINT_PATCH = 37, 417 VGPU10_PRIMITIVE_31_CONTROL_POINT_PATCH = 38, 418 VGPU10_PRIMITIVE_32_CONTROL_POINT_PATCH = 39, 419 VGPU10_PRIMITIVE_MAX = 39 420 } VGPU10_PRIMITIVE; 421 422 typedef enum { 423 VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED = 0, 424 VGPU10_PRIMITIVE_TOPOLOGY_POINTLIST = 1, 425 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST = 2, 426 VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP = 3, 427 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST = 4, 428 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP = 5, 429 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST_ADJ = 10, 430 VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP_ADJ = 11, 431 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST_ADJ = 12, 432 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP_ADJ = 13 433 } VGPU10_PRIMITIVE_TOPOLOGY; 434 435 typedef enum { 436 VGPU10_CUSTOMDATA_COMMENT = 0, 437 VGPU10_CUSTOMDATA_DEBUGINFO = 1, 438 VGPU10_CUSTOMDATA_OPAQUE = 2, 439 VGPU10_CUSTOMDATA_DCL_IMMEDIATE_CONSTANT_BUFFER = 3 440 } VGPU10_CUSTOMDATA_CLASS; 441 442 typedef enum { 443 VGPU10_RESINFO_RETURN_FLOAT = 0, 444 VGPU10_RESINFO_RETURN_RCPFLOAT = 1, 445 VGPU10_RESINFO_RETURN_UINT = 2 446 } VGPU10_RESINFO_RETURN_TYPE; 447 448 typedef enum { 449 VGPU10_INSTRUCTION_RETURN_FLOAT = 0, 450 VGPU10_INSTRUCTION_RETURN_UINT = 1 451 } VGPU10_INSTRUCTION_RETURN_TYPE; 452 453 typedef enum { 454 VGPU10_TESSELLATOR_DOMAIN_UNDEFINED = 0, 455 VGPU10_TESSELLATOR_DOMAIN_ISOLINE = 1, 456 VGPU10_TESSELLATOR_DOMAIN_TRI = 2, 457 VGPU10_TESSELLATOR_DOMAIN_QUAD = 3, 458 VGPU10_TESSELLATOR_DOMAIN_MAX = 3 459 } VGPU10_TESSELLATOR_DOMAIN; 460 461 typedef enum { 462 VGPU10_TESSELLATOR_PARTITIONING_UNDEFINED = 0, 463 VGPU10_TESSELLATOR_PARTITIONING_INTEGER = 1, 464 VGPU10_TESSELLATOR_PARTITIONING_POW2 = 2, 465 VGPU10_TESSELLATOR_PARTITIONING_FRACTIONAL_ODD = 3, 466 VGPU10_TESSELLATOR_PARTITIONING_FRACTIONAL_EVEN = 4, 467 VGPU10_TESSELLATOR_PARTITIONING_MAX = 4 468 } VGPU10_TESSELLATOR_PARTITIONING; 469 470 typedef enum { 471 VGPU10_TESSELLATOR_OUTPUT_UNDEFINED = 0, 472 VGPU10_TESSELLATOR_OUTPUT_POINT = 1, 473 VGPU10_TESSELLATOR_OUTPUT_LINE = 2, 474 VGPU10_TESSELLATOR_OUTPUT_TRIANGLE_CW = 3, 475 VGPU10_TESSELLATOR_OUTPUT_TRIANGLE_CCW = 4, 476 VGPU10_TESSELLATOR_OUTPUT_MAX = 4 477 } VGPU10_TESSELLATOR_OUTPUT_PRIMITIVE; 478 479 typedef union { 480 struct { 481 unsigned int opcodeType : 11; 482 unsigned int interpolationMode : 4; 483 unsigned int : 3; 484 unsigned int testBoolean : 1; 485 unsigned int preciseValues : 4; 486 unsigned int : 1; 487 unsigned int instructionLength : 7; 488 unsigned int extended : 1; 489 }; 490 491 struct { 492 unsigned int : 11; 493 unsigned int vmwareOpcodeType : 4; 494 }; 495 struct { 496 unsigned int : 11; 497 unsigned int resourceDimension : 5; 498 unsigned int sampleCount : 7; 499 }; 500 struct { 501 unsigned int : 11; 502 unsigned int samplerMode : 4; 503 }; 504 struct { 505 unsigned int : 11; 506 unsigned int accessPattern : 1; 507 }; 508 struct { 509 unsigned int : 11; 510 unsigned int primitive : 6; 511 }; 512 struct { 513 unsigned int : 11; 514 unsigned int primitiveTopology : 7; 515 }; 516 struct { 517 unsigned int : 11; 518 unsigned int customDataClass : 21; 519 }; 520 struct { 521 unsigned int : 11; 522 unsigned int resinfoReturnType : 2; 523 unsigned int saturate : 1; 524 }; 525 struct { 526 unsigned int : 11; 527 unsigned int refactoringAllowed : 1; 528 529 unsigned int enableDoublePrecisionFloatOps : 1; 530 unsigned int forceEarlyDepthStencil : 1; 531 unsigned int enableRawAndStructuredBuffers : 1; 532 }; 533 struct { 534 unsigned int : 11; 535 unsigned int instReturnType : 2; 536 }; 537 538 struct { 539 unsigned int : 11; 540 unsigned int syncThreadsInGroup : 1; 541 unsigned int syncThreadGroupShared : 1; 542 unsigned int syncUAVMemoryGroup : 1; 543 unsigned int syncUAVMemoryGlobal : 1; 544 }; 545 struct { 546 unsigned int : 11; 547 unsigned int controlPointCount : 6; 548 }; 549 struct { 550 unsigned int : 11; 551 unsigned int tessDomain : 2; 552 }; 553 struct { 554 unsigned int : 11; 555 unsigned int tessPartitioning : 3; 556 }; 557 struct { 558 unsigned int : 11; 559 unsigned int tessOutputPrimitive : 3; 560 }; 561 struct { 562 unsigned int : 11; 563 unsigned int interfaceIndexedDynamically : 1; 564 }; 565 struct { 566 unsigned int : 11; 567 unsigned int uavResourceDimension : 5; 568 unsigned int globallyCoherent : 1; 569 unsigned int : 6; 570 unsigned int uavHasCounter : 1; 571 }; 572 uint32 value; 573 } VGPU10OpcodeToken0; 574 575 typedef enum { 576 VGPU10_EXTENDED_OPCODE_EMPTY = 0, 577 VGPU10_EXTENDED_OPCODE_SAMPLE_CONTROLS = 1, 578 579 VGPU10_EXTENDED_OPCODE_RESOURCE_DIM = 2, 580 VGPU10_EXTENDED_OPCODE_RESOURCE_RETURN_TYPE = 3 581 } VGPU10_EXTENDED_OPCODE_TYPE; 582 583 typedef union { 584 struct { 585 unsigned int opcodeType : 6; 586 unsigned int : 3; 587 unsigned int offsetU : 4; 588 unsigned int offsetV : 4; 589 unsigned int offsetW : 4; 590 unsigned int : 10; 591 unsigned int extended : 1; 592 }; 593 594 struct { 595 unsigned int : 6; 596 unsigned int resourceDimension : 5; 597 }; 598 struct { 599 unsigned int : 6; 600 unsigned int resourceReturnTypeX : 4; 601 unsigned int resourceReturnTypeY : 4; 602 unsigned int resourceReturnTypeZ : 4; 603 unsigned int resourceReturnTypeW : 4; 604 }; 605 uint32 value; 606 } VGPU10OpcodeToken1; 607 608 typedef enum { 609 VGPU10_OPERAND_0_COMPONENT = 0, 610 VGPU10_OPERAND_1_COMPONENT = 1, 611 VGPU10_OPERAND_4_COMPONENT = 2, 612 VGPU10_OPERAND_N_COMPONENT = 3 613 } VGPU10_OPERAND_NUM_COMPONENTS; 614 615 typedef enum { 616 VGPU10_OPERAND_4_COMPONENT_MASK_MODE = 0, 617 VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE = 1, 618 VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE = 2 619 } VGPU10_OPERAND_4_COMPONENT_SELECTION_MODE; 620 621 #define VGPU10_OPERAND_4_COMPONENT_MASK_X 0x1 622 #define VGPU10_OPERAND_4_COMPONENT_MASK_Y 0x2 623 #define VGPU10_OPERAND_4_COMPONENT_MASK_Z 0x4 624 #define VGPU10_OPERAND_4_COMPONENT_MASK_W 0x8 625 626 #define VGPU10_OPERAND_4_COMPONENT_MASK_XY \ 627 (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_Y) 628 #define VGPU10_OPERAND_4_COMPONENT_MASK_XZ \ 629 (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_Z) 630 #define VGPU10_OPERAND_4_COMPONENT_MASK_XW \ 631 (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_W) 632 #define VGPU10_OPERAND_4_COMPONENT_MASK_YZ \ 633 (VGPU10_OPERAND_4_COMPONENT_MASK_Y | VGPU10_OPERAND_4_COMPONENT_MASK_Z) 634 #define VGPU10_OPERAND_4_COMPONENT_MASK_YW \ 635 (VGPU10_OPERAND_4_COMPONENT_MASK_Y | VGPU10_OPERAND_4_COMPONENT_MASK_W) 636 #define VGPU10_OPERAND_4_COMPONENT_MASK_ZW \ 637 (VGPU10_OPERAND_4_COMPONENT_MASK_Z | VGPU10_OPERAND_4_COMPONENT_MASK_W) 638 #define VGPU10_OPERAND_4_COMPONENT_MASK_XYZ \ 639 (VGPU10_OPERAND_4_COMPONENT_MASK_XY | VGPU10_OPERAND_4_COMPONENT_MASK_Z) 640 #define VGPU10_OPERAND_4_COMPONENT_MASK_XYW \ 641 (VGPU10_OPERAND_4_COMPONENT_MASK_XY | VGPU10_OPERAND_4_COMPONENT_MASK_W) 642 #define VGPU10_OPERAND_4_COMPONENT_MASK_XZW \ 643 (VGPU10_OPERAND_4_COMPONENT_MASK_XZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) 644 #define VGPU10_OPERAND_4_COMPONENT_MASK_YZW \ 645 (VGPU10_OPERAND_4_COMPONENT_MASK_YZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) 646 #define VGPU10_OPERAND_4_COMPONENT_MASK_XYZW \ 647 (VGPU10_OPERAND_4_COMPONENT_MASK_XYZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) 648 #define VGPU10_OPERAND_4_COMPONENT_MASK_ALL VGPU10_OPERAND_4_COMPONENT_MASK_XYZW 649 650 #define VGPU10_REGISTER_INDEX_FROM_SEMANTIC 0xffffffff 651 652 typedef enum { 653 VGPU10_COMPONENT_X = 0, 654 VGPU10_COMPONENT_Y = 1, 655 VGPU10_COMPONENT_Z = 2, 656 VGPU10_COMPONENT_W = 3 657 } VGPU10_COMPONENT_NAME; 658 659 typedef enum { 660 VGPU10_OPERAND_TYPE_TEMP = 0, 661 VGPU10_OPERAND_TYPE_INPUT = 1, 662 VGPU10_OPERAND_TYPE_OUTPUT = 2, 663 VGPU10_OPERAND_TYPE_INDEXABLE_TEMP = 3, 664 VGPU10_OPERAND_TYPE_IMMEDIATE32 = 4, 665 VGPU10_OPERAND_TYPE_IMMEDIATE64 = 5, 666 VGPU10_OPERAND_TYPE_SAMPLER = 6, 667 VGPU10_OPERAND_TYPE_RESOURCE = 7, 668 VGPU10_OPERAND_TYPE_CONSTANT_BUFFER = 8, 669 VGPU10_OPERAND_TYPE_IMMEDIATE_CONSTANT_BUFFER = 9, 670 VGPU10_OPERAND_TYPE_LABEL = 10, 671 VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID = 11, 672 VGPU10_OPERAND_TYPE_OUTPUT_DEPTH = 12, 673 VGPU10_OPERAND_TYPE_NULL = 13, 674 VGPU10_OPERAND_TYPE_SM40_MAX = 13, 675 676 VGPU10_OPERAND_TYPE_RASTERIZER = 14, 677 VGPU10_OPERAND_TYPE_OUTPUT_COVERAGE_MASK = 15, 678 VGPU10_OPERAND_TYPE_SM41_MAX = 15, 679 680 VGPU10_OPERAND_TYPE_STREAM = 16, 681 VGPU10_OPERAND_TYPE_FUNCTION_BODY = 17, 682 VGPU10_OPERAND_TYPE_FUNCTION_TABLE = 18, 683 VGPU10_OPERAND_TYPE_INTERFACE = 19, 684 VGPU10_OPERAND_TYPE_FUNCTION_INPUT = 20, 685 VGPU10_OPERAND_TYPE_FUNCTION_OUTPUT = 21, 686 VGPU10_OPERAND_TYPE_OUTPUT_CONTROL_POINT_ID = 22, 687 VGPU10_OPERAND_TYPE_INPUT_FORK_INSTANCE_ID = 23, 688 VGPU10_OPERAND_TYPE_INPUT_JOIN_INSTANCE_ID = 24, 689 VGPU10_OPERAND_TYPE_INPUT_CONTROL_POINT = 25, 690 VGPU10_OPERAND_TYPE_OUTPUT_CONTROL_POINT = 26, 691 VGPU10_OPERAND_TYPE_INPUT_PATCH_CONSTANT = 27, 692 VGPU10_OPERAND_TYPE_INPUT_DOMAIN_POINT = 28, 693 VGPU10_OPERAND_TYPE_THIS_POINTER = 29, 694 VGPU10_OPERAND_TYPE_UAV = 30, 695 VGPU10_OPERAND_TYPE_THREAD_GROUP_SHARED_MEMORY = 31, 696 VGPU10_OPERAND_TYPE_INPUT_THREAD_ID = 32, 697 VGPU10_OPERAND_TYPE_INPUT_THREAD_GROUP_ID = 33, 698 VGPU10_OPERAND_TYPE_INPUT_THREAD_ID_IN_GROUP = 34, 699 VGPU10_OPERAND_TYPE_INPUT_COVERAGE_MASK = 35, 700 VGPU10_OPERAND_TYPE_INPUT_THREAD_ID_IN_GROUP_FLATTENED = 36, 701 VGPU10_OPERAND_TYPE_INPUT_GS_INSTANCE_ID = 37, 702 VGPU10_OPERAND_TYPE_OUTPUT_DEPTH_GREATER_EQUAL = 38, 703 VGPU10_OPERAND_TYPE_OUTPUT_DEPTH_LESS_EQUAL = 39, 704 VGPU10_OPERAND_TYPE_CYCLE_COUNTER = 40, 705 VGPU10_OPERAND_TYPE_SM50_MAX = 40, 706 707 VGPU10_NUM_OPERANDS 708 } VGPU10_OPERAND_TYPE; 709 710 typedef enum { 711 VGPU10_OPERAND_INDEX_0D = 0, 712 VGPU10_OPERAND_INDEX_1D = 1, 713 VGPU10_OPERAND_INDEX_2D = 2, 714 VGPU10_OPERAND_INDEX_3D = 3 715 } VGPU10_OPERAND_INDEX_DIMENSION; 716 717 typedef enum { 718 VGPU10_OPERAND_INDEX_IMMEDIATE32 = 0, 719 VGPU10_OPERAND_INDEX_IMMEDIATE64 = 1, 720 VGPU10_OPERAND_INDEX_RELATIVE = 2, 721 VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE = 3, 722 VGPU10_OPERAND_INDEX_IMMEDIATE64_PLUS_RELATIVE = 4 723 } VGPU10_OPERAND_INDEX_REPRESENTATION; 724 725 typedef union { 726 struct { 727 unsigned int numComponents : 2; 728 unsigned int selectionMode : 2; 729 unsigned int mask : 4; 730 unsigned int : 4; 731 unsigned int operandType : 8; 732 unsigned int indexDimension : 2; 733 unsigned int index0Representation : 3; 734 unsigned int index1Representation : 3; 735 unsigned int : 3; 736 unsigned int extended : 1; 737 }; 738 struct { 739 unsigned int : 4; 740 unsigned int swizzleX : 2; 741 unsigned int swizzleY : 2; 742 unsigned int swizzleZ : 2; 743 unsigned int swizzleW : 2; 744 }; 745 struct { 746 unsigned int : 4; 747 unsigned int selectMask : 2; 748 }; 749 uint32 value; 750 } VGPU10OperandToken0; 751 752 typedef enum { 753 VGPU10_EXTENDED_OPERAND_EMPTY = 0, 754 VGPU10_EXTENDED_OPERAND_MODIFIER = 1 755 } VGPU10_EXTENDED_OPERAND_TYPE; 756 757 typedef enum { 758 VGPU10_OPERAND_MODIFIER_NONE = 0, 759 VGPU10_OPERAND_MODIFIER_NEG = 1, 760 VGPU10_OPERAND_MODIFIER_ABS = 2, 761 VGPU10_OPERAND_MODIFIER_ABSNEG = 3 762 } VGPU10_OPERAND_MODIFIER; 763 764 typedef union { 765 struct { 766 unsigned int extendedOperandType : 6; 767 unsigned int operandModifier : 8; 768 unsigned int : 17; 769 unsigned int extended : 1; 770 }; 771 uint32 value; 772 } VGPU10OperandToken1; 773 774 typedef enum { 775 VGPU10_RETURN_TYPE_MIN = 1, 776 777 VGPU10_RETURN_TYPE_UNORM = 1, 778 VGPU10_RETURN_TYPE_SNORM = 2, 779 VGPU10_RETURN_TYPE_SINT = 3, 780 VGPU10_RETURN_TYPE_UINT = 4, 781 VGPU10_RETURN_TYPE_FLOAT = 5, 782 VGPU10_RETURN_TYPE_MIXED = 6, 783 VGPU10_RETURN_TYPE_SM40_MAX = 6, 784 785 VGPU10_RETURN_TYPE_DOUBLE = 7, 786 VGPU10_RETURN_TYPE_CONTINUED = 8, 787 VGPU10_RETURN_TYPE_UNUSED = 9, 788 789 VGPU10_RETURN_TYPE_MAX = 9 790 } VGPU10_RESOURCE_RETURN_TYPE; 791 792 typedef union { 793 struct { 794 unsigned int component0 : 4; 795 unsigned int component1 : 4; 796 unsigned int component2 : 4; 797 unsigned int component3 : 4; 798 }; 799 uint32 value; 800 } VGPU10ResourceReturnTypeToken; 801 802 typedef enum { 803 VGPU10_NAME_MIN = 0, 804 805 VGPU10_NAME_UNDEFINED = 0, 806 VGPU10_NAME_POSITION = 1, 807 VGPU10_NAME_CLIP_DISTANCE = 2, 808 VGPU10_NAME_CULL_DISTANCE = 3, 809 VGPU10_NAME_RENDER_TARGET_ARRAY_INDEX = 4, 810 VGPU10_NAME_VIEWPORT_ARRAY_INDEX = 5, 811 VGPU10_NAME_VERTEX_ID = 6, 812 VGPU10_NAME_PRIMITIVE_ID = 7, 813 VGPU10_NAME_INSTANCE_ID = 8, 814 VGPU10_NAME_IS_FRONT_FACE = 9, 815 VGPU10_NAME_SAMPLE_INDEX = 10, 816 VGPU10_NAME_SM40_MAX = 10, 817 818 VGPU10_NAME_FINAL_QUAD_U_EQ_0_EDGE_TESSFACTOR = 11, 819 VGPU10_NAME_FINAL_QUAD_V_EQ_0_EDGE_TESSFACTOR = 12, 820 VGPU10_NAME_FINAL_QUAD_U_EQ_1_EDGE_TESSFACTOR = 13, 821 VGPU10_NAME_FINAL_QUAD_V_EQ_1_EDGE_TESSFACTOR = 14, 822 VGPU10_NAME_FINAL_QUAD_U_INSIDE_TESSFACTOR = 15, 823 VGPU10_NAME_FINAL_QUAD_V_INSIDE_TESSFACTOR = 16, 824 VGPU10_NAME_FINAL_TRI_U_EQ_0_EDGE_TESSFACTOR = 17, 825 VGPU10_NAME_FINAL_TRI_V_EQ_0_EDGE_TESSFACTOR = 18, 826 VGPU10_NAME_FINAL_TRI_W_EQ_0_EDGE_TESSFACTOR = 19, 827 VGPU10_NAME_FINAL_TRI_INSIDE_TESSFACTOR = 20, 828 VGPU10_NAME_FINAL_LINE_DETAIL_TESSFACTOR = 21, 829 VGPU10_NAME_FINAL_LINE_DENSITY_TESSFACTOR = 22, 830 831 VGPU10_NAME_MAX = 22 832 } VGPU10_SYSTEM_NAME; 833 834 typedef union { 835 struct { 836 unsigned int name : 16; 837 }; 838 uint32 value; 839 } VGPU10NameToken; 840 841 #ifdef __cplusplus 842 } 843 #endif 844 845 #endif 846