1 /*
2 * Copyright (c) 2008-2024 Broadcom. All Rights Reserved.
3 * The term “Broadcom” refers to Broadcom Inc.
4 * and/or its subsidiaries.
5 * SPDX-License-Identifier: MIT
6 */
7
8 #ifndef SVGA_TGSI_EMIT_H
9 #define SVGA_TGSI_EMIT_H
10
11 #include "tgsi/tgsi_scan.h"
12 #include "svga_hw_reg.h"
13 #include "svga_shader.h"
14 #include "svga_tgsi.h"
15 #include "vm_basic_types.h"
16 #include "svga3d_shaderdefs.h"
17
18 struct src_register
19 {
20 SVGA3dShaderSrcToken base;
21 SVGA3dShaderSrcToken indirect;
22 };
23
24
25 struct svga_arl_consts
26 {
27 int number;
28 int idx;
29 int swizzle;
30 int arl_num;
31 };
32
33
34 /**
35 * This is the context/state used during TGSI->SVGA shader translation.
36 */
37 struct svga_shader_emitter
38 {
39 unsigned size;
40 char *buf;
41 char *ptr;
42
43 struct svga_compile_key key;
44 struct tgsi_shader_info info;
45 int unit;
46
47 int imm_start;
48
49 int nr_hw_float_const;
50 int nr_hw_int_const;
51 int nr_hw_temp;
52
53 int insn_offset;
54
55 int internal_temp_count;
56 int internal_imm_count;
57
58 int internal_color_idx[2]; /* diffuse, specular */
59 int internal_color_count;
60
61 bool emitted_vface;
62 bool emit_frontface;
63 int internal_frontface_idx;
64
65 int ps30_input_count;
66 int vs30_output_count;
67
68 int dynamic_branching_level;
69
70 unsigned num_output_writes;
71 bool constant_color_output;
72
73 bool in_main_func;
74
75 bool created_common_immediate;
76 int common_immediate_idx[2];
77
78 bool created_loop_const;
79 int loop_const_idx;
80
81 unsigned inverted_texcoords; /**< bitmask of which texcoords are flipped */
82 struct src_register ps_true_texcoord[PIPE_MAX_ATTRIBS];
83 struct src_register ps_inverted_texcoord[PIPE_MAX_ATTRIBS];
84 unsigned ps_inverted_texcoord_input[PIPE_MAX_ATTRIBS];
85
86 unsigned label[32];
87 unsigned nr_labels;
88
89 /** input/output register mappings, indexed by register number */
90 struct src_register input_map[PIPE_MAX_ATTRIBS];
91 SVGA3dShaderDestToken output_map[PIPE_MAX_ATTRIBS];
92
93 bool ps_reads_pos;
94 bool emitted_depth_fog;
95 struct src_register ps_true_pos;
96 struct src_register ps_depth_pos;
97 SVGA3dShaderDestToken ps_temp_pos;
98
99 /* shared input for depth and fog */
100 struct src_register ps_depth_fog;
101
102 struct src_register imm_0055;
103 SVGA3dShaderDestToken temp_pos;
104 SVGA3dShaderDestToken true_pos;
105 SVGA3dShaderDestToken depth_pos;
106
107 /* shared output for depth and fog */
108 SVGA3dShaderDestToken vs_depth_fog;
109
110 /* PS output colors (indexed by color semantic index) */
111 SVGA3dShaderDestToken temp_color_output[PIPE_MAX_COLOR_BUFS];
112 SVGA3dShaderDestToken true_color_output[PIPE_MAX_COLOR_BUFS];
113
114 SVGA3dShaderDestToken temp_psiz;
115 SVGA3dShaderDestToken true_psiz;
116
117 struct svga_arl_consts arl_consts[12];
118 int num_arl_consts;
119 int current_arl;
120
121 unsigned pstipple_sampler_unit;
122
123 int num_samplers;
124 uint8_t sampler_target[PIPE_MAX_SAMPLERS];
125 };
126
127
128 bool
129 svga_shader_emit_dword(struct svga_shader_emitter *emit, unsigned dword);
130
131 bool
132 svga_shader_emit_dwords(struct svga_shader_emitter *emit,
133 const unsigned *dwords, unsigned nr);
134
135 bool
136 svga_shader_emit_opcode(struct svga_shader_emitter *emit,
137 unsigned opcode);
138
139 bool
140 svga_shader_emit_instructions(struct svga_shader_emitter *emit,
141 const struct tgsi_token *tokens);
142
143 bool
144 svga_shader_emit_samplers_decl(struct svga_shader_emitter *emit);
145
146 bool
147 svga_translate_decl_sm30(struct svga_shader_emitter *emit,
148 const struct tgsi_full_declaration *decl);
149
150
151 #define TRANSLATE_SWIZZLE(x,y,z,w) ((x) | ((y) << 2) | ((z) << 4) | ((w) << 6))
152 #define SWIZZLE_XYZW \
153 TRANSLATE_SWIZZLE(TGSI_SWIZZLE_X,TGSI_SWIZZLE_Y,TGSI_SWIZZLE_Z,TGSI_SWIZZLE_W)
154 #define SWIZZLE_XXXX \
155 TRANSLATE_SWIZZLE(TGSI_SWIZZLE_X,TGSI_SWIZZLE_X,TGSI_SWIZZLE_X,TGSI_SWIZZLE_X)
156 #define SWIZZLE_YYYY \
157 TRANSLATE_SWIZZLE(TGSI_SWIZZLE_Y,TGSI_SWIZZLE_Y,TGSI_SWIZZLE_Y,TGSI_SWIZZLE_Y)
158 #define SWIZZLE_ZZZZ \
159 TRANSLATE_SWIZZLE(TGSI_SWIZZLE_Z,TGSI_SWIZZLE_Z,TGSI_SWIZZLE_Z,TGSI_SWIZZLE_Z)
160 #define SWIZZLE_WWWW \
161 TRANSLATE_SWIZZLE(TGSI_SWIZZLE_W,TGSI_SWIZZLE_W,TGSI_SWIZZLE_W,TGSI_SWIZZLE_W)
162
163
164 /** Emit the given SVGA3dShaderInstToken opcode */
165 static inline bool
emit_instruction(struct svga_shader_emitter * emit,SVGA3dShaderInstToken opcode)166 emit_instruction(struct svga_shader_emitter *emit,
167 SVGA3dShaderInstToken opcode)
168 {
169 return svga_shader_emit_opcode(emit, opcode.value);
170 }
171
172
173 /** Generate a SVGA3dShaderInstToken for the given SVGA3D shader opcode */
174 static inline SVGA3dShaderInstToken
inst_token(SVGA3dShaderOpCodeType opcode)175 inst_token(SVGA3dShaderOpCodeType opcode)
176 {
177 SVGA3dShaderInstToken inst;
178
179 inst.value = 0;
180 inst.op = opcode;
181
182 return inst;
183 }
184
185
186 /**
187 * Generate a SVGA3dShaderInstToken for the given SVGA3D shader opcode
188 * with the predication flag set.
189 */
190 static inline SVGA3dShaderInstToken
inst_token_predicated(SVGA3dShaderOpCodeType opcode)191 inst_token_predicated(SVGA3dShaderOpCodeType opcode)
192 {
193 SVGA3dShaderInstToken inst;
194
195 inst.value = 0;
196 inst.op = opcode;
197 inst.predicated = 1;
198
199 return inst;
200 }
201
202
203 /**
204 * Generate a SVGA3dShaderInstToken for a SETP instruction (set predicate)
205 * using the given comparison operator (one of SVGA3DOPCOMP_xx).
206 */
207 static inline SVGA3dShaderInstToken
inst_token_setp(SVGA3dShaderOpCodeCompFnType operator)208 inst_token_setp(SVGA3dShaderOpCodeCompFnType operator)
209 {
210 SVGA3dShaderInstToken inst;
211
212 inst.value = 0;
213 inst.op = SVGA3DOP_SETP;
214 inst.control = operator;
215
216 return inst;
217 }
218
219
220 /**
221 * Create an instance of a SVGA3dShaderDestToken.
222 * Note that this function is used to create tokens for output registers,
223 * temp registers AND constants (see emit_def_const()).
224 */
225 static inline SVGA3dShaderDestToken
dst_register(SVGA3dShaderRegType file,int number)226 dst_register(SVGA3dShaderRegType file, int number)
227 {
228 SVGA3dShaderDestToken dest;
229
230 /* check values against bitfield sizes */
231 assert(number < (1 << 11));
232 assert(file <= SVGA3DREG_PREDICATE);
233
234 dest.value = 0;
235 dest.num = number;
236 dest.type_upper = file >> 3;
237 dest.relAddr = 0;
238 dest.reserved1 = 0;
239 dest.mask = 0xf;
240 dest.dstMod = 0;
241 dest.shfScale = 0;
242 dest.type_lower = file & 0x7;
243 dest.reserved0 = 1; /* is_reg */
244
245 return dest;
246 }
247
248
249 /**
250 * Apply a writemask to the given SVGA3dShaderDestToken, returning a
251 * new SVGA3dShaderDestToken.
252 */
253 static inline SVGA3dShaderDestToken
writemask(SVGA3dShaderDestToken dest,unsigned mask)254 writemask(SVGA3dShaderDestToken dest, unsigned mask)
255 {
256 assert(dest.mask & mask);
257 dest.mask &= mask;
258 return dest;
259 }
260
261
262 /** Create a SVGA3dShaderSrcToken given a register file and number */
263 static inline SVGA3dShaderSrcToken
src_token(SVGA3dShaderRegType file,int number)264 src_token(SVGA3dShaderRegType file, int number)
265 {
266 SVGA3dShaderSrcToken src;
267
268 /* check values against bitfield sizes */
269 assert(number < (1 << 11));
270 assert(file <= SVGA3DREG_PREDICATE);
271
272 src.value = 0;
273 src.num = number;
274 src.type_upper = file >> 3;
275 src.relAddr = 0;
276 src.reserved1 = 0;
277 src.swizzle = SWIZZLE_XYZW;
278 src.srcMod = 0;
279 src.type_lower = file & 0x7;
280 src.reserved0 = 1; /* is_reg */
281
282 return src;
283 }
284
285
286 /** Create a src_register given a register file and register number */
287 static inline struct src_register
src_register(SVGA3dShaderRegType file,int number)288 src_register(SVGA3dShaderRegType file, int number)
289 {
290 struct src_register src;
291
292 src.base = src_token(file, number);
293 src.indirect.value = 0;
294
295 return src;
296 }
297
298 /** Translate src_register into SVGA3dShaderDestToken */
299 static inline SVGA3dShaderDestToken
dst(struct src_register src)300 dst(struct src_register src)
301 {
302 return dst_register(SVGA3dShaderGetRegType(src.base.value), src.base.num);
303 }
304
305
306 /** Translate SVGA3dShaderDestToken to a src_register */
307 static inline struct src_register
src(SVGA3dShaderDestToken dst)308 src(SVGA3dShaderDestToken dst)
309 {
310 return src_register(SVGA3dShaderGetRegType(dst.value), dst.num);
311 }
312
313 #endif
314