1# Copyright © 2024 Imagination Technologies Ltd. 2# SPDX-License-Identifier: MIT 3 4from pco_isa import * 5from pco_ops import * 6 7# Enum mappings. 8 9class EnumMap(object): 10 def __init__(self, name, type_from, type_to, mappings): 11 self.name = name 12 self.type_from = type_from 13 self.type_to = type_to 14 self.mappings = mappings 15 16enum_maps = {} 17 18def enum_map(enum_from, enum_to, mappings): 19 key = (enum_from, enum_to) 20 assert key not in enum_maps.keys(), f'Duplicate enum mapping for "{enum_from.tname}" to "{enum_to.tname}".' 21 22 assert enum_from.base_type == BaseType.enum 23 assert enum_to.base_type == BaseType.enum 24 25 # Ensure the validity of the enum_from elements. 26 assert set([from_elem for from_elem, to_elem in mappings]).issubset(set(enum_from.enum.elems.keys())), f'Invalid enum_from spec in enum mapping for "{enum_from.tname}" to "{enum_to.tname}".' 27 28 # Ensure the validity of the enum_to elements. 29 assert set([to_elem for from_elem, to_elem in mappings]).issubset(set(enum_to.enum.elems.keys())), f'Invalid enum_to spec in enum mapping for "{enum_from.tname}" to "{enum_to.tname}".' 30 31 _mappings = [] 32 for elem_from, elem_to in mappings: 33 _mappings.append((enum_from.enum.elems[elem_from].cname, enum_to.enum.elems[elem_to].cname)) 34 35 name = f'{prefix}_map_{enum_from.tname}_to_{enum_to.tname}' 36 enum_maps[key] = EnumMap(name, enum_from.name, enum_to.name, _mappings) 37 38enum_map(OM_EXEC_CND.t, F_CC, [ 39 ('e1_zx', 'e1_zx'), 40 ('e1_z1', 'e1_z1'), 41 ('ex_zx', 'ex_zx'), 42 ('e1_z0', 'e1_z0'), 43]) 44 45enum_map(REG_CLASS, F_REGBANK, [ 46 ('temp', 'temp'), 47 ('vtxin', 'vtxin'), 48 ('coeff', 'coeff'), 49 ('shared', 'shared'), 50 ('index', 'idx0'), 51 ('spec', 'special'), 52 ('intern', 'special'), 53 ('const', 'special'), 54 ('pixout', 'special'), 55 ('global', 'special'), 56 ('slot', 'special'), 57]) 58 59enum_map(REG_CLASS, F_IDXBANK, [ 60 ('temp', 'temp'), 61 ('vtxin', 'vtxin'), 62 ('coeff', 'coeff'), 63 ('shared', 'shared'), 64 ('index', 'idx'), 65 ('pixout', 'pixout'), 66]) 67 68enum_map(IO, F_IS0_SEL, [ 69 ('s0', 's0'), 70 ('s1', 's1'), 71 ('s2', 's2'), 72 ('s3', 's3'), 73 ('s4', 's4'), 74 ('s5', 's5'), 75]) 76 77enum_map(IO, F_IS1_SEL, [ 78 ('ft0', 'ft0'), 79 ('fte', 'fte'), 80]) 81 82enum_map(IO, F_IS2_SEL, [ 83 ('ft1', 'ft1'), 84 ('fte', 'fte'), 85]) 86 87enum_map(IO, F_IS3_SEL, [ 88 ('ft0', 'ft0'), 89 ('ft1', 'ft1'), 90 ('fte', 'fte'), 91]) 92 93enum_map(IO, F_IS4_SEL, [ 94 ('ft0', 'ft0'), 95 ('ft1', 'ft1'), 96 ('ft2', 'ft2'), 97 ('fte', 'fte'), 98]) 99 100enum_map(IO, F_IS5_SEL, [ 101 ('ft0', 'ft0'), 102 ('ft1', 'ft1'), 103 ('ft2', 'ft2'), 104 ('fte', 'fte'), 105]) 106 107enum_map(OM_ITR_MODE.t, F_ITER_MODE, [ 108 ('pixel', 'pixel'), 109 ('sample', 'sample'), 110 ('centroid', 'centroid'), 111]) 112 113enum_map(OM_PCK_FMT.t, F_PCK_FORMAT, [ 114 ('u8888', 'u8888'), 115 ('s8888', 's8888'), 116 ('o8888', 'o8888'), 117 ('u1616', 'u1616'), 118 ('s1616', 's1616'), 119 ('o1616', 'o1616'), 120 ('u32', 'u32'), 121 ('s32', 's32'), 122 ('u1010102', 'u1010102'), 123 ('s1010102', 's1010102'), 124 ('u111110', 'u111110'), 125 ('s111110', 's111110'), 126 ('f111110', 'f111110'), 127 ('f16f16', 'f16f16'), 128 ('f32', 'f32'), 129 ('cov', 'cov'), 130 ('u565u565', 'u565u565'), 131 ('d24s8', 'd24s8'), 132 ('s8d24', 's8d24'), 133 ('f32_mask', 'f32_mask'), 134 ('2f10f10f10', '2f10f10f10'), 135 ('s8888ogl', 's8888ogl'), 136 ('s1616ogl', 's1616ogl'), 137 ('zero', 'zero'), 138 ('one', 'one'), 139]) 140 141enum_map(OM_SCHED.t, F_SCHED_CTRL, [ 142 ('none', 'none'), 143 ('swap', 'swap'), 144 ('wdf', 'wdf'), 145]) 146 147# Op/ISA mapping. 148class OpMap(object): 149 def __init__(self, name, cop_name, igrp_mappings, encode_variants): 150 self.name = name 151 self.cop_name = cop_name 152 self.igrp_mappings = igrp_mappings 153 self.encode_variants = encode_variants 154 155op_maps = {} 156encode_maps = {} 157 158def op_map(op, hdr, isa_ops, srcs=[], iss=[], dests=[]): 159 assert op not in op_maps.keys(), f'Duplicate op mapping for op "{op.name}".' 160 161 hdr_variant, hdr_fields = hdr 162 163 # Ensure we're speccing everything in the header except length and da (need to be set later). 164 assert set(hdr_variant.struct_fields.keys()) == set([hdr_field for hdr_field, val_spec in hdr_fields] + ['length', 'da']), f'Invalid field spec in hdr mapping for op "{op.name}".' 165 166 # Add alutype setting after the check above, as it's actually a fixed value. 167 hdr_fields.append(('alutype', hdr_variant.bsname)) 168 169 igrp_mappings = [] 170 encode_variants = [] 171 172 hdr_mappings = [] 173 for hdr_field, val_spec in hdr_fields: 174 field = hdr_variant.bit_set.fields[hdr_field] 175 if isinstance(val_spec, bool): 176 value = str(val_spec).lower() 177 hdr_mappings.append(f'{{}}->hdr.{hdr_field} = {str(val_spec).lower()};') 178 elif isinstance(val_spec, int): 179 value = val_spec 180 hdr_mappings.append(f'{{}}->hdr.{hdr_field} = {val_spec};') 181 elif isinstance(val_spec, str): 182 assert field.field_type.base_type == BaseType.enum 183 184 enum = field.field_type.enum 185 assert enum.parent is None 186 assert val_spec in enum.elems.keys(), f'Invalid enum element "{val_spec}" in field "{hdr_field}" in hdr mapping for op "{op.name}".' 187 188 hdr_mappings.append(f'{{}}->hdr.{hdr_field} = {enum.elems[val_spec].cname};') 189 elif isinstance(val_spec, OpMod): 190 assert val_spec in op.op_mods, f'Op mod "{val_spec.t.tname}" was specified but not valid in hdr mapping for op "{op.name}".' 191 192 if field.field_type.base_type == BaseType.enum: 193 enum_map_key = (val_spec.t, field.field_type) 194 assert enum_map_key in enum_maps.keys(), f'Op mod enum "{val_spec.t.tname}" was specified but no mapping from enum "{field.field_type.tname}" was found in hdr mapping for op "{op.name}".' 195 enum_mapping = enum_maps[enum_map_key] 196 hdr_mappings.append(f'{{}}->hdr.{hdr_field} = {enum_mapping.name}(pco_instr_get_mod({{}}, {val_spec.cname}));') 197 else: 198 hdr_mappings.append(f'{{}}->hdr.{hdr_field} = pco_instr_get_mod({{}}, {val_spec.cname});') 199 200 if val_spec.t.unset: 201 reset_val = 0 if val_spec.t.nzdefault is None else val_spec.t.nzdefault 202 hdr_mappings.append(f'pco_instr_set_mod({{1}}, {val_spec.cname}, {reset_val});') 203 elif isinstance(val_spec, tuple): 204 mod, origin = val_spec 205 assert isinstance(mod, str) and isinstance(origin, str) 206 hdr_mappings.append(f'{{}}->hdr.{hdr_field} = {mod}({{}}->{origin});') 207 else: 208 assert False, f'Invalid value spec for field "{hdr_field}" in hdr mapping for op "{op.name}".' 209 210 if bool(hdr_mappings): 211 igrp_mappings.append(hdr_mappings); 212 213 repl_op_mappings = [] 214 op_mappings = [] 215 for phase, isa_op_map_variants, *_repl_op in isa_ops: 216 assert phase in OP_PHASE.enum.elems.keys() 217 default_variant = isa_op_map_variants[0] 218 first_variant = isa_op_map_variants[1] if len(isa_op_map_variants) > 1 else None 219 repl_op_spec = _repl_op[0] if len(_repl_op) > 0 else None 220 221 op_mappings.append(f'list_del(&{{1}}->link);') 222 223 if repl_op_spec is None: 224 op_mappings.append(f'{{}}->instrs[{OP_PHASE.enum.elems[phase].cname}] = {{}};') 225 op_mappings.append(f'ralloc_steal(igrp, {{1}});') 226 227 for isa_op_map_variant in isa_op_map_variants: 228 isa_op, isa_op_fields, *_ = isa_op_map_variant 229 230 # Ensure we're speccing everything in the op fields. 231 assert set(isa_op.struct_fields.keys()) == set([field for field, val_spec in isa_op_fields]), f'Invalid field spec in isa op "{isa_op.bsname}" mapping for op "{op.name}".' 232 233 variant = isa_op.name.upper() 234 variant_set = '' 235 if isa_op_map_variant != default_variant: 236 variant_set = ' ' 237 isa_op_conds = isa_op_map_variant[2] 238 if_str = 'if (' if isa_op_map_variant == first_variant else 'else if(' 239 for i, isa_op_cond in enumerate(isa_op_conds): 240 if i > 0: 241 if_str += ' && ' 242 243 if isinstance(isa_op_cond, tuple) and len(isa_op_cond) == 3: 244 mod, origin, cond = isa_op_cond 245 assert isinstance(mod, RefMod) 246 if_str += f'{{1}}->{origin}.{mod.t.tname} {cond}' 247 elif isinstance(isa_op_cond, tuple) and len(isa_op_cond) == 2: 248 mod, cond = isa_op_cond 249 assert isinstance(mod, OpMod) 250 if_str += f'pco_instr_get_mod({{1}}, {mod.cname}) {cond}' 251 else: 252 assert False 253 if_str += ')' 254 op_mappings.append(if_str) 255 256 variant_set += f'{{}}->variant.instr[{OP_PHASE.enum.elems[phase].cname}].{isa_op.bit_set.bsname} = {variant};' 257 op_mappings.append(variant_set) 258 259 encode_variant = f'{isa_op.name}_encode({{0}}' 260 for isa_op_field, val_spec in isa_op_fields: 261 struct_field = isa_op.struct_fields[isa_op_field] 262 encode_variant += f', .{isa_op_field} = ' 263 if isinstance(val_spec, bool): 264 encode_variant += str(val_spec).lower() 265 elif isinstance(val_spec, int): 266 encode_variant += str(val_spec) 267 elif isinstance(val_spec, str): 268 assert struct_field.type.base_type == BaseType.enum 269 270 enum = struct_field.type.enum 271 assert enum.parent is None 272 assert val_spec in enum.elems.keys(), f'Invalid enum element "{val_spec}" in field "{isa_op_field}" in isa op "{isa_op.bsname}" mapping for op "{op.name}".' 273 274 encode_variant += enum.elems[val_spec].cname 275 elif isinstance(val_spec, OpMod): 276 assert val_spec in op.op_mods, f'Op mod "{val_spec.t.tname}" was specified but not valid in isa op "{isa_op.bsname}" mapping for op "{op.name}".' 277 278 if struct_field.type.base_type == BaseType.enum: 279 enum_map_key = (val_spec.t, struct_field.type) 280 assert enum_map_key in enum_maps.keys(), f'Op mod enum "{val_spec.t.tname}" was specified but no mapping from enum "{struct_field.type.tname}" was found in hdr mapping for op "{op.name}".' 281 enum_mapping = enum_maps[enum_map_key] 282 encode_variant += f'{enum_mapping.name}(pco_instr_get_mod({{1}}, {val_spec.cname}))' 283 else: 284 encode_variant += f'pco_instr_get_mod({{1}}, {val_spec.cname})' 285 286 elif isinstance(val_spec, tuple): 287 mod, origin = val_spec 288 if isinstance(mod, RefMod): 289 encode_variant += f'{{1}}->{origin}.{mod.t.tname}' 290 elif isinstance(mod, str): 291 encode_variant += f'{mod}({{1}}->{origin})' 292 else: 293 assert False 294 else: 295 assert False, f'Invalid value spec for field "{isa_op_field}" in isa op "{isa_op.bsname}" mapping for op "{op.name}".' 296 encode_variant += ')' 297 encode_variants.append((variant, encode_variant)) 298 299 enc_bname = op.bname 300 enc_cname = op.cname 301 if repl_op_spec is not None: 302 repl_op, repl_dests, repl_srcs = repl_op_spec 303 304 enc_bname = repl_op.bname 305 enc_cname = repl_op.cname 306 307 assert len(repl_dests) == repl_op.num_dests 308 assert len(repl_srcs) == repl_op.num_srcs 309 repl_set = f'{{0}}->instrs[{OP_PHASE.enum.elems[phase].cname}] = {repl_op.bname}({{1}}->parent_func' 310 311 for ref in repl_dests + repl_srcs: 312 if ref in IO.enum.elems.keys(): 313 io = IO.enum.elems[ref] 314 repl_set += f', pco_ref_io({io.cname})' 315 else: 316 repl_set += f', {{1}}->{ref}' 317 318 repl_set += ');' 319 320 repl_op_mappings.append(repl_set) 321 322 repl_op_mappings.append(f'ralloc_free({{1}});') 323 324 encode_maps[enc_bname] = OpMap(enc_bname, enc_cname.upper(), None, encode_variants) 325 326 igrp_mappings.append(op_mappings); 327 328 src_mappings = [] 329 for src, val_spec, _io in srcs: 330 assert _io in IO.enum.elems.keys() 331 io = IO.enum.elems[_io] 332 src_mappings.append(f'{{}}->srcs.{src} = {{}}->{val_spec};') 333 src_mappings.append(f'{{1}}->{val_spec} = pco_ref_io({io.cname});') 334 src_mappings.append(f'pco_ref_xfer_mods(&{{1}}->{val_spec}, &{{0}}->srcs.{src}, true);') 335 336 if bool(src_mappings): 337 igrp_mappings.append(src_mappings); 338 339 iss_mappings = [] 340 for iss, _io in iss: 341 assert _io in IO.enum.elems.keys() 342 io = IO.enum.elems[_io] 343 iss_mappings.append(f'{{}}->iss.{iss} = pco_ref_io({io.cname});') 344 345 if bool(iss_mappings): 346 igrp_mappings.append(iss_mappings); 347 348 dest_mappings = [] 349 for dest, val_spec, _io in dests: 350 assert _io in IO.enum.elems.keys() 351 io = IO.enum.elems[_io] 352 dest_mappings.append(f'{{}}->dests.{dest} = {{}}->{val_spec};') 353 dest_mappings.append(f'{{1}}->{val_spec} = pco_ref_io({io.cname});') 354 dest_mappings.append(f'pco_ref_xfer_mods(&{{1}}->{val_spec}, &{{0}}->dests.{dest}, true);') 355 356 if bool(dest_mappings): 357 igrp_mappings.append(dest_mappings); 358 359 if bool(repl_op_mappings): 360 igrp_mappings.append(repl_op_mappings); 361 362 name = op.bname 363 cop_name = op.cname.upper() 364 op_maps[name] = OpMap(name, cop_name, igrp_mappings, None) 365 366# Main. 367op_map(O_FADD, 368 hdr=(I_IGRP_HDR_MAIN, [ 369 ('oporg', 'p0'), 370 ('olchk', OM_OLCHK), 371 ('w1p', False), 372 ('w0p', True), 373 ('cc', OM_EXEC_CND), 374 ('end', OM_END), 375 ('atom', OM_ATOM), 376 ('rpt', OM_RPT), 377 ]), 378 isa_ops=[ 379 ('0', [ 380 (I_FADD, [ 381 ('sat', OM_SAT), 382 ('s0neg', (RM_NEG, 'src[0]')), 383 ('s0abs', (RM_ABS, 'src[0]')), 384 ('s1abs', (RM_ABS, 'src[1]')), 385 ('s0flr', (RM_FLR, 'src[0]')), 386 ]) 387 ]) 388 ], 389 srcs=[ 390 ('s[0]', 'src[0]', 's0'), 391 ('s[1]', 'src[1]', 's1'), 392 ], 393 iss=[ 394 ('is[4]', 'ft0'), 395 ], 396 dests=[ 397 ('w[0]', 'dest[0]', 'ft0'), 398 ] 399) 400 401op_map(O_FMUL, 402 hdr=(I_IGRP_HDR_MAIN, [ 403 ('oporg', 'p0'), 404 ('olchk', OM_OLCHK), 405 ('w1p', False), 406 ('w0p', True), 407 ('cc', OM_EXEC_CND), 408 ('end', OM_END), 409 ('atom', OM_ATOM), 410 ('rpt', OM_RPT), 411 ]), 412 isa_ops=[ 413 ('0', [ 414 (I_FMUL, [ 415 ('sat', OM_SAT), 416 ('s0neg', (RM_NEG, 'src[0]')), 417 ('s0abs', (RM_ABS, 'src[0]')), 418 ('s1abs', (RM_ABS, 'src[1]')), 419 ('s0flr', (RM_FLR, 'src[0]')), 420 ]) 421 ]) 422 ], 423 srcs=[ 424 ('s[0]', 'src[0]', 's0'), 425 ('s[1]', 'src[1]', 's1'), 426 ], 427 iss=[ 428 ('is[4]', 'ft0'), 429 ], 430 dests=[ 431 ('w[0]', 'dest[0]', 'ft0'), 432 ] 433) 434 435op_map(O_FMAD, 436 hdr=(I_IGRP_HDR_MAIN, [ 437 ('oporg', 'p0'), 438 ('olchk', OM_OLCHK), 439 ('w1p', False), 440 ('w0p', True), 441 ('cc', OM_EXEC_CND), 442 ('end', OM_END), 443 ('atom', OM_ATOM), 444 ('rpt', OM_RPT), 445 ]), 446 isa_ops=[ 447 ('0', [ 448 (I_FMAD_EXT, [ 449 ('s0neg', (RM_NEG, 'src[0]')), 450 ('s0abs', (RM_ABS, 'src[0]')), 451 ('s2neg', (RM_NEG, 'src[2]')), 452 ('sat', OM_SAT), 453 454 ('lp', OM_LP), 455 ('s1abs', (RM_ABS, 'src[1]')), 456 ('s1neg', (RM_NEG, 'src[1]')), 457 ('s2flr', (RM_FLR, 'src[2]')), 458 ('s2abs', (RM_ABS, 'src[2]')), 459 ]), 460 (I_FMAD, [ 461 ('s0neg', (RM_NEG, 'src[0]')), 462 ('s0abs', (RM_ABS, 'src[0]')), 463 ('s2neg', (RM_NEG, 'src[2]')), 464 ('sat', OM_SAT), 465 ], [ 466 (OM_LP, '== false'), 467 (RM_ABS, 'src[1]', '== false'), 468 (RM_NEG, 'src[1]', '== false'), 469 (RM_FLR, 'src[2]', '== false'), 470 (RM_ABS, 'src[2]', '== false'), 471 ]) 472 ]) 473 ], 474 srcs=[ 475 ('s[0]', 'src[0]', 's0'), 476 ('s[1]', 'src[1]', 's1'), 477 ('s[2]', 'src[2]', 's2'), 478 ], 479 iss=[ 480 ('is[4]', 'ft0'), 481 ], 482 dests=[ 483 ('w[0]', 'dest[0]', 'ft0'), 484 ] 485) 486 487op_map(O_MBYP0, 488 hdr=(I_IGRP_HDR_MAIN, [ 489 ('oporg', 'p0'), 490 ('olchk', OM_OLCHK), 491 ('w1p', False), 492 ('w0p', True), 493 ('cc', OM_EXEC_CND), 494 ('end', OM_END), 495 ('atom', OM_ATOM), 496 ('rpt', OM_RPT), 497 ]), 498 isa_ops=[ 499 ('0', [ 500 (I_SNGL_EXT, [ 501 ('sngl_op', 'byp'), 502 ('s0neg', (RM_NEG, 'src[0]')), 503 ('s0abs', (RM_ABS, 'src[0]')), 504 ]), 505 (I_SNGL, [('sngl_op', 'byp')], [ 506 (RM_NEG, 'src[0]', '== false'), 507 (RM_ABS, 'src[0]', '== false'), 508 ]) 509 ]) 510 ], 511 srcs=[ 512 ('s[0]', 'src[0]', 's0'), 513 ], 514 iss=[ 515 ('is[4]', 'ft0'), 516 ], 517 dests=[ 518 ('w[0]', 'dest[0]', 'ft0'), 519 ] 520) 521 522op_map(O_PCK, 523 hdr=(I_IGRP_HDR_MAIN, [ 524 ('oporg', 'p2'), 525 ('olchk', OM_OLCHK), 526 ('w1p', False), 527 ('w0p', True), 528 ('cc', OM_EXEC_CND), 529 ('end', OM_END), 530 ('atom', OM_ATOM), 531 ('rpt', OM_RPT), 532 ]), 533 isa_ops=[ 534 ('2_pck', [ 535 (I_PCK, [ 536 ('prog', False), 537 ('rtz', OM_ROUNDZERO), 538 ('scale', OM_SCALE), 539 ('pck_format', OM_PCK_FMT), 540 ]) 541 ]) 542 ], 543 srcs=[ 544 ('s[0]', 'src[0]', 'is3'), 545 ], 546 iss=[ 547 ('is[0]', 's0'), 548 ('is[3]', 'fte'), 549 ('is[4]', 'ft2'), 550 ], 551 dests=[ 552 ('w[0]', 'dest[0]', 'ft2'), 553 ] 554) 555 556# Backend. 557op_map(O_UVSW_WRITE, 558 hdr=(I_IGRP_HDR_MAIN, [ 559 ('oporg', 'be'), 560 ('olchk', False), 561 ('w1p', False), 562 ('w0p', False), 563 ('cc', OM_EXEC_CND), 564 ('end', False), 565 ('atom', False), 566 ('rpt', OM_RPT), 567 ]), 568 isa_ops=[ 569 ('backend', [ 570 (I_UVSW_WRITE_IMM, [ 571 ('dsel', 'w0'), 572 ('imm_addr', ('pco_ref_get_imm', 'src[1]')), 573 ]) 574 ]) 575 ], 576 srcs=[ 577 ('s[0]', 'src[0]', 'w0'), 578 ], 579 iss=[ 580 ('is[0]', 's0'), 581 ('is[4]', 'fte'), 582 ] 583) 584 585op_map(O_UVSW_EMIT, 586 hdr=(I_IGRP_HDR_MAIN, [ 587 ('oporg', 'be'), 588 ('olchk', False), 589 ('w1p', False), 590 ('w0p', False), 591 ('cc', OM_EXEC_CND), 592 ('end', False), 593 ('atom', False), 594 ('rpt', 1), 595 ]), 596 isa_ops=[ 597 ('backend', [(I_UVSW_EMIT, [])]) 598 ], 599) 600 601op_map(O_UVSW_EMIT_ENDTASK, 602 hdr=(I_IGRP_HDR_MAIN, [ 603 ('oporg', 'be'), 604 ('olchk', False), 605 ('w1p', False), 606 ('w0p', False), 607 ('cc', 'e1_zx'), 608 ('end', OM_END), 609 ('atom', False), 610 ('rpt', 1), 611 ]), 612 isa_ops=[ 613 ('backend', [(I_UVSW_EMIT_ENDTASK, [])]) 614 ], 615) 616 617op_map(O_UVSW_ENDTASK, 618 hdr=(I_IGRP_HDR_MAIN, [ 619 ('oporg', 'be'), 620 ('olchk', False), 621 ('w1p', False), 622 ('w0p', False), 623 ('cc', 'e1_zx'), 624 ('end', OM_END), 625 ('atom', False), 626 ('rpt', 1), 627 ]), 628 isa_ops=[ 629 ('backend', [(I_UVSW_ENDTASK, [])]) 630 ], 631) 632 633op_map(O_UVSW_WRITE_EMIT_ENDTASK, 634 hdr=(I_IGRP_HDR_MAIN, [ 635 ('oporg', 'be'), 636 ('olchk', False), 637 ('w1p', False), 638 ('w0p', False), 639 ('cc', 'e1_zx'), 640 ('end', OM_END), 641 ('atom', False), 642 ('rpt', 1), 643 ]), 644 isa_ops=[ 645 ('backend', [ 646 (I_UVSW_WRITE_EMIT_ENDTASK_IMM, [ 647 ('dsel', 'w0'), 648 ('imm_addr', ('pco_ref_get_imm', 'src[1]')), 649 ]) 650 ]) 651 ], 652 srcs=[ 653 ('s[0]', 'src[0]', 'w0'), 654 ], 655 iss=[ 656 ('is[0]', 's0'), 657 ('is[4]', 'fte'), 658 ] 659) 660 661op_map(O_FITRP, 662 hdr=(I_IGRP_HDR_MAIN, [ 663 ('oporg', 'be'), 664 ('olchk', OM_OLCHK), 665 ('w1p', False), 666 ('w0p', False), 667 ('cc', OM_EXEC_CND), 668 ('end', OM_END), 669 ('atom', OM_ATOM), 670 ('rpt', OM_RPT), 671 ]), 672 isa_ops=[ 673 ('backend', [ 674 (I_FITR, [ 675 ('p', True), 676 ('drc', ('pco_ref_get_drc', 'src[0]')), 677 ('iter_mode', OM_ITR_MODE), 678 ('sat', OM_SAT), 679 ('count', ('pco_ref_get_imm', 'src[3]')), 680 ]) 681 ]) 682 ], 683 srcs=[ 684 ('s[0]', 'src[1]', 's0'), 685 ('s[2]', 'src[2]', 's2'), 686 ('s[3]', 'dest[0]', 's3'), 687 ] 688) 689 690# Bitwise 691op_map(O_MOVI32, 692 hdr=(I_IGRP_HDR_BITWISE, [ 693 ('opcnt', 'p0'), 694 ('olchk', OM_OLCHK), 695 ('w1p', False), 696 ('w0p', True), 697 ('cc', OM_EXEC_CND), 698 ('end', OM_END), 699 ('atom', OM_ATOM), 700 ('rpt', OM_RPT), 701 ]), 702 isa_ops=[ 703 ('0', [ 704 (I_PHASE0_IMM32, [ 705 ('count_src', 's2'), 706 ('count_op', 'byp'), 707 ('shift1_op', 'byp'), 708 ('imm32', ('pco_ref_get_imm', 'src[1]')), 709 ]) 710 ], (O_BBYP0BM, ('ft0', 'dest[0]'), ('s0', 'src[0]'))) 711 ], 712 dests=[ 713 ('w[0]', 'dest[0]', 'ft1'), 714 ] 715) 716 717# Control. 718op_map(O_WOP, 719 hdr=(I_IGRP_HDR_CONTROL, [ 720 ('olchk', False), 721 ('w1p', False), 722 ('w0p', False), 723 ('cc', 'e1_zx'), 724 ('miscctl', 0), 725 ('ctrlop', 'wop'), 726 ]), 727 isa_ops=[ 728 ('ctrl', [(I_WOP, [])]), 729 ] 730) 731 732op_map(O_WDF, 733 hdr=(I_IGRP_HDR_CONTROL, [ 734 ('olchk', False), 735 ('w1p', False), 736 ('w0p', False), 737 ('cc', 'e1_zx'), 738 ('miscctl', ('pco_ref_get_drc', 'src[0]')), 739 ('ctrlop', 'wdf'), 740 ]), 741 isa_ops=[ 742 ('ctrl', [(I_WDF, [])]), 743 ] 744) 745 746op_map(O_NOP, 747 hdr=(I_IGRP_HDR_CONTROL, [ 748 ('olchk', False), 749 ('w1p', False), 750 ('w0p', False), 751 ('cc', OM_EXEC_CND), 752 ('miscctl', False), 753 ('ctrlop', 'nop'), 754 ]), 755 isa_ops=[ 756 ('ctrl', [(I_NOP, [])]), 757 ] 758) 759 760op_map(O_NOP_END, 761 hdr=(I_IGRP_HDR_CONTROL, [ 762 ('olchk', False), 763 ('w1p', False), 764 ('w0p', False), 765 ('cc', OM_EXEC_CND), 766 ('miscctl', True), 767 ('ctrlop', 'nop'), 768 ]), 769 isa_ops=[ 770 ('ctrl', [(I_NOP, [])]), 771 ] 772) 773 774op_map(O_DITR, 775 hdr=(I_IGRP_HDR_CONTROL, [ 776 ('olchk', False), 777 ('w1p', False), 778 ('w0p', False), 779 ('cc', OM_EXEC_CND), 780 ('miscctl', False), 781 ('ctrlop', 'ditr'), 782 ]), 783 isa_ops=[ 784 ('ctrl', [ 785 (I_DITR, [ 786 ('dest', ('pco_ref_get_temp', 'dest[0]')), # TODO NEXT: validate whether or not indexed registers can be used for srcs/dests. 787 788 ('coff', ('pco_ref_get_coeff', 'src[1]')), 789 ('p', 'none'), 790 791 ('woff', 0), 792 ('mode', OM_ITR_MODE), 793 794 ('count', ('pco_ref_get_imm', 'src[2]')), 795 ('coff_idx_ctrl', ('pco_ref_get_reg_idx_ctrl', 'src[1]')), 796 ('woff_idx_ctrl', 'none'), 797 798 ('f16', OM_F16), 799 ('sched_ctrl', OM_SCHED), 800 ('drc', ('pco_ref_get_drc', 'src[0]')), 801 ('sat', OM_SAT), 802 ]) 803 ]) 804 ], 805) 806 807op_map(O_DITRP, 808 hdr=(I_IGRP_HDR_CONTROL, [ 809 ('olchk', False), 810 ('w1p', False), 811 ('w0p', False), 812 ('cc', OM_EXEC_CND), 813 ('miscctl', False), 814 ('ctrlop', 'ditr'), 815 ]), 816 isa_ops=[ 817 ('ctrl', [ 818 (I_DITR, [ 819 ('dest', ('pco_ref_get_temp', 'dest[0]')), # TODO NEXT: validate whether or not indexed registers can be used for srcs/dests. 820 821 ('coff', ('pco_ref_get_coeff', 'src[1]')), 822 ('p', 'iter_mul'), 823 824 ('woff', ('pco_ref_get_coeff', 'src[2]')), 825 ('mode', OM_ITR_MODE), 826 827 ('count', ('pco_ref_get_imm', 'src[3]')), 828 ('coff_idx_ctrl', ('pco_ref_get_reg_idx_ctrl', 'src[1]')), 829 ('woff_idx_ctrl', ('pco_ref_get_reg_idx_ctrl', 'src[2]')), 830 831 ('f16', OM_F16), 832 ('sched_ctrl', OM_SCHED), 833 ('drc', ('pco_ref_get_drc', 'src[0]')), 834 ('sat', OM_SAT), 835 ]) 836 ]) 837 ], 838) 839