1 // Copyright 2022 The Pigweed Authors 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); you may not 4 // use this file except in compliance with the License. You may obtain a copy of 5 // the License at 6 // 7 // https://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 11 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 12 // License for the specific language governing permissions and limitations under 13 // the License. 14 15 #include "pw_boot/boot.h" 16 17 #include <array> 18 19 #include "FreeRTOS.h" 20 #include "config/sf2_mss_hal_conf.h" 21 #include "m2sxxx.h" 22 #include "pw_boot_cortex_m/boot.h" 23 #include "pw_malloc/malloc.h" 24 #include "pw_preprocessor/compiler.h" 25 #include "pw_string/util.h" 26 #include "pw_sys_io_emcraft_sf2/init.h" 27 #include "pw_system/init.h" 28 #include "pw_toolchain/infinite_loop.h" 29 #include "system_m2sxxx.h" 30 #include "task.h" 31 32 #include liberosoc_CONFIG_FILE 33 34 extern "C" void Reset_Handler(void); 35 36 // Functions needed when configGENERATE_RUN_TIME_STATS is on. configureTimerForRunTimeStats(void)37extern "C" void configureTimerForRunTimeStats(void) {} getRunTimeCounterValue(void)38extern "C" unsigned long getRunTimeCounterValue(void) { 39 // The AngleProcessingUnit (APU) IP has a clock counter register that is tied 40 // to the Cortex-M clock running at 142Mhz. The 32-bit APU 'TCNT' register is 41 // connected to the AHBlite bus at address 0x70000000 with offset 0. 42 43 volatile unsigned long* counter_register = (unsigned long*)0x70000000; 44 45 // Read the value from the counter register 46 return *counter_register; 47 } 48 pw_boot_PreStaticMemoryInit()49extern "C" void pw_boot_PreStaticMemoryInit() { 50 #if SF2_MSS_NO_BOOTLOADER 51 SystemInit(); 52 // Initialize DDR 53 // inclusive-language: disable 54 MDDR->core.ddrc.DYN_SOFT_RESET_CR = 0x0000; 55 MDDR->core.ddrc.DYN_REFRESH_1_CR = 0x27de; 56 MDDR->core.ddrc.DYN_REFRESH_2_CR = 0x030f; 57 MDDR->core.ddrc.DYN_POWERDOWN_CR = 0x0002; 58 MDDR->core.ddrc.DYN_DEBUG_CR = 0x0000; 59 MDDR->core.ddrc.MODE_CR = 0x00C1; 60 MDDR->core.ddrc.ADDR_MAP_BANK_CR = 0x099f; 61 MDDR->core.ddrc.ECC_DATA_MASK_CR = 0x0000; 62 MDDR->core.ddrc.ADDR_MAP_COL_1_CR = 0x3333; 63 MDDR->core.ddrc.ADDR_MAP_COL_2_CR = 0xffff; 64 MDDR->core.ddrc.ADDR_MAP_ROW_1_CR = 0x7777; 65 MDDR->core.ddrc.ADDR_MAP_ROW_2_CR = 0x0fff; 66 MDDR->core.ddrc.INIT_1_CR = 0x0001; 67 MDDR->core.ddrc.CKE_RSTN_CYCLES_CR[0] = 0x4242; 68 MDDR->core.ddrc.CKE_RSTN_CYCLES_CR[1] = 0x0008; 69 MDDR->core.ddrc.INIT_MR_CR = 0x0033; 70 MDDR->core.ddrc.INIT_EMR_CR = 0x0020; 71 MDDR->core.ddrc.INIT_EMR2_CR = 0x0000; 72 MDDR->core.ddrc.INIT_EMR3_CR = 0x0000; 73 MDDR->core.ddrc.DRAM_BANK_TIMING_PARAM_CR = 0x00c0; 74 MDDR->core.ddrc.DRAM_RD_WR_LATENCY_CR = 0x0023; 75 MDDR->core.ddrc.DRAM_RD_WR_PRE_CR = 0x0235; 76 MDDR->core.ddrc.DRAM_MR_TIMING_PARAM_CR = 0x0064; 77 MDDR->core.ddrc.DRAM_RAS_TIMING_CR = 0x0108; 78 MDDR->core.ddrc.DRAM_RD_WR_TRNARND_TIME_CR = 0x0178; 79 MDDR->core.ddrc.DRAM_T_PD_CR = 0x0033; 80 MDDR->core.ddrc.DRAM_BANK_ACT_TIMING_CR = 0x1947; 81 MDDR->core.ddrc.ODT_PARAM_1_CR = 0x0010; 82 MDDR->core.ddrc.ODT_PARAM_2_CR = 0x0000; 83 MDDR->core.ddrc.ADDR_MAP_COL_3_CR = 0x3300; 84 MDDR->core.ddrc.MODE_REG_RD_WR_CR = 0x0000; 85 MDDR->core.ddrc.MODE_REG_DATA_CR = 0x0000; 86 MDDR->core.ddrc.PWR_SAVE_1_CR = 0x0514; 87 MDDR->core.ddrc.PWR_SAVE_2_CR = 0x0000; 88 MDDR->core.ddrc.ZQ_LONG_TIME_CR = 0x0200; 89 MDDR->core.ddrc.ZQ_SHORT_TIME_CR = 0x0040; 90 MDDR->core.ddrc.ZQ_SHORT_INT_REFRESH_MARGIN_CR[0] = 0x0012; 91 MDDR->core.ddrc.ZQ_SHORT_INT_REFRESH_MARGIN_CR[1] = 0x0002; 92 MDDR->core.ddrc.PERF_PARAM_1_CR = 0x4000; 93 MDDR->core.ddrc.HPR_QUEUE_PARAM_CR[0] = 0x80f8; 94 MDDR->core.ddrc.HPR_QUEUE_PARAM_CR[1] = 0x0007; 95 MDDR->core.ddrc.LPR_QUEUE_PARAM_CR[0] = 0x80f8; 96 MDDR->core.ddrc.LPR_QUEUE_PARAM_CR[1] = 0x0007; 97 MDDR->core.ddrc.WR_QUEUE_PARAM_CR = 0x0200; 98 MDDR->core.ddrc.PERF_PARAM_2_CR = 0x0001; 99 MDDR->core.ddrc.PERF_PARAM_3_CR = 0x0000; 100 MDDR->core.ddrc.DFI_RDDATA_EN_CR = 0x0003; 101 MDDR->core.ddrc.DFI_MIN_CTRLUPD_TIMING_CR = 0x0003; 102 MDDR->core.ddrc.DFI_MAX_CTRLUPD_TIMING_CR = 0x0040; 103 MDDR->core.ddrc.DFI_WR_LVL_CONTROL_CR[0] = 0x0000; 104 MDDR->core.ddrc.DFI_WR_LVL_CONTROL_CR[1] = 0x0000; 105 MDDR->core.ddrc.DFI_RD_LVL_CONTROL_CR[0] = 0x0000; 106 MDDR->core.ddrc.DFI_RD_LVL_CONTROL_CR[1] = 0x0000; 107 MDDR->core.ddrc.DFI_CTRLUPD_TIME_INTERVAL_CR = 0x0309; 108 MDDR->core.ddrc.AXI_FABRIC_PRI_ID_CR = 0x0000; 109 MDDR->core.ddrc.ECC_INT_CLR_REG = 0x0000; 110 111 MDDR->core.phy.LOOPBACK_TEST_CR = 0x0000; 112 MDDR->core.phy.CTRL_SLAVE_RATIO_CR = 0x0080; 113 MDDR->core.phy.DATA_SLICE_IN_USE_CR = 0x0003; 114 MDDR->core.phy.DQ_OFFSET_CR[0] = 0x00000000; 115 MDDR->core.phy.DQ_OFFSET_CR[2] = 0x0000; 116 MDDR->core.phy.DLL_LOCK_DIFF_CR = 0x000B; 117 MDDR->core.phy.FIFO_WE_SLAVE_RATIO_CR[0] = 0x0040; 118 MDDR->core.phy.FIFO_WE_SLAVE_RATIO_CR[1] = 0x0401; 119 MDDR->core.phy.FIFO_WE_SLAVE_RATIO_CR[2] = 0x4010; 120 MDDR->core.phy.FIFO_WE_SLAVE_RATIO_CR[3] = 0x0000; 121 MDDR->core.phy.LOCAL_ODT_CR = 0x0001; 122 MDDR->core.phy.RD_DQS_SLAVE_RATIO_CR[0] = 0x0040; 123 MDDR->core.phy.RD_DQS_SLAVE_RATIO_CR[1] = 0x0401; 124 MDDR->core.phy.RD_DQS_SLAVE_RATIO_CR[2] = 0x4010; 125 MDDR->core.phy.WR_DATA_SLAVE_RATIO_CR[0] = 0x0040; 126 MDDR->core.phy.WR_DATA_SLAVE_RATIO_CR[1] = 0x0401; 127 MDDR->core.phy.WR_DATA_SLAVE_RATIO_CR[2] = 0x4010; 128 MDDR->core.phy.WR_RD_RL_CR = 0x0021; 129 MDDR->core.phy.RDC_WE_TO_RE_DELAY_CR = 0x0003; 130 MDDR->core.phy.USE_FIXED_RE_CR = 0x0001; 131 MDDR->core.phy.USE_RANK0_DELAYS_CR = 0x0001; 132 MDDR->core.phy.CONFIG_CR = 0x0009; 133 MDDR->core.phy.DYN_RESET_CR = 0x01; 134 MDDR->core.ddrc.DYN_SOFT_RESET_CR = 0x01; 135 // inclusive-language: enable 136 // Wait for config 137 while ((MDDR->core.ddrc.DDRC_SR) == 0x0000) { 138 } 139 #endif 140 } 141 pw_boot_PreStaticConstructorInit()142extern "C" void pw_boot_PreStaticConstructorInit() { 143 // TODO(skeys) add "#if no_bootLoader" and the functions needed for init. 144 145 #if PW_MALLOC_ACTIVE 146 pw_MallocInit(&pw_boot_heap_low_addr, &pw_boot_heap_high_addr); 147 #endif // PW_MALLOC_ACTIVE 148 pw_sys_io_Init(); 149 } 150 151 // TODO(amontanez): pw_boot_PreMainInit() should get renamed to 152 // pw_boot_FinalizeBoot or similar when main() is removed. pw_boot_PreMainInit()153extern "C" void pw_boot_PreMainInit() { 154 pw::system::Init(); 155 vTaskStartScheduler(); 156 PW_UNREACHABLE; 157 } 158 sf2_SocInit()159extern "C" void sf2_SocInit() { 160 #if SF2_MSS_NO_BOOTLOADER 161 Reset_Handler(); 162 #endif 163 pw_boot_Entry(); 164 } 165 166 // This `main()` stub prevents another main function from being linked since 167 // this target deliberately doesn't run `main()`. main()168int main() {} 169 pw_boot_PostMain()170extern "C" PW_NO_RETURN void pw_boot_PostMain() { 171 // In case main() returns, just sit here until the device is reset. 172 pw::InfiniteLoop(); 173 } 174