1 // Copyright 2024 The Pigweed Authors
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License"); you may not
4 // use this file except in compliance with the License. You may obtain a copy of
5 // the License at
6 //
7 // https://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
11 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
12 // License for the specific language governing permissions and limitations under
13 // the License.
14
15 #include "board.h"
16
17 #include <stdint.h>
18
19 #include "fsl_clock.h"
20 #include "fsl_debug_console.h"
21
22 #define BOARD_FLEXSPI_DLL_LOCK_RETRY (10)
23
BOARD_InitDebugConsole(void)24 void BOARD_InitDebugConsole(void) {
25 uint32_t uartClkSrcFreq;
26
27 /* attach FRG0 clock to FLEXCOMM0 (debug console) */
28 CLOCK_SetFRGClock(BOARD_DEBUG_UART_FRG_CLK);
29 CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
30
31 uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
32
33 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE,
34 BOARD_DEBUG_UART_BAUDRATE,
35 BOARD_DEBUG_UART_TYPE,
36 uartClkSrcFreq);
37 }
38
BOARD_SetFlexspiClock(FLEXSPI_Type * base,uint32_t src,uint32_t divider)39 void BOARD_SetFlexspiClock(FLEXSPI_Type* base, uint32_t src, uint32_t divider) {
40 if (base == FLEXSPI0) {
41 if ((CLKCTL0->FLEXSPI0FCLKSEL != CLKCTL0_FLEXSPI0FCLKSEL_SEL(src)) ||
42 ((CLKCTL0->FLEXSPI0FCLKDIV & CLKCTL0_FLEXSPI0FCLKDIV_DIV_MASK) !=
43 (divider - 1))) {
44 BOARD_DeinitFlash(base);
45
46 CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK_MASK;
47 CLKCTL0->FLEXSPI0FCLKSEL = CLKCTL0_FLEXSPI0FCLKSEL_SEL(src);
48 CLKCTL0->FLEXSPI0FCLKDIV |= CLKCTL0_FLEXSPI0FCLKDIV_RESET_MASK;
49 CLKCTL0->FLEXSPI0FCLKDIV = CLKCTL0_FLEXSPI0FCLKDIV_DIV(divider - 1);
50 while ((CLKCTL0->FLEXSPI0FCLKDIV) &
51 CLKCTL0_FLEXSPI0FCLKDIV_REQFLAG_MASK) {
52 }
53 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK;
54
55 BOARD_InitFlash(base);
56 }
57 } else if (base == FLEXSPI1) {
58 if ((CLKCTL0->FLEXSPI1FCLKSEL != CLKCTL0_FLEXSPI1FCLKSEL_SEL(src)) ||
59 ((CLKCTL0->FLEXSPI1FCLKDIV & CLKCTL0_FLEXSPI1FCLKDIV_DIV_MASK) !=
60 (divider - 1))) {
61 BOARD_DeinitFlash(base);
62
63 CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK_MASK;
64 CLKCTL0->FLEXSPI1FCLKSEL = CLKCTL0_FLEXSPI1FCLKSEL_SEL(src);
65 CLKCTL0->FLEXSPI1FCLKDIV |= CLKCTL0_FLEXSPI1FCLKDIV_RESET_MASK;
66 CLKCTL0->FLEXSPI1FCLKDIV = CLKCTL0_FLEXSPI1FCLKDIV_DIV(divider - 1);
67 while ((CLKCTL0->FLEXSPI1FCLKDIV) &
68 CLKCTL0_FLEXSPI1FCLKDIV_REQFLAG_MASK) {
69 }
70 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_MASK;
71
72 BOARD_InitFlash(base);
73 }
74 } else {
75 return;
76 }
77 }
78
BOARD_DeinitFlash(FLEXSPI_Type * base)79 void BOARD_DeinitFlash(FLEXSPI_Type* base) {
80 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK;
81
82 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
83
84 while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) &&
85 (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) {
86 }
87 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
88 }
89
BOARD_InitFlash(FLEXSPI_Type * base)90 void BOARD_InitFlash(FLEXSPI_Type* base) {
91 uint32_t status;
92 uint32_t lastStatus;
93 uint32_t retry;
94
95 base->DLLCR[0] = 0x1U;
96
97 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
98
99 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
100 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) {
101 }
102
103 if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK)) {
104 lastStatus = base->STS2;
105 retry = BOARD_FLEXSPI_DLL_LOCK_RETRY;
106 do {
107 status = base->STS2;
108 if ((status &
109 (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) ==
110 (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) {
111 retry = 100;
112 break;
113 } else if (status == lastStatus) {
114 retry--;
115 } else {
116 retry = BOARD_FLEXSPI_DLL_LOCK_RETRY;
117 lastStatus = status;
118 }
119 } while (retry > 0);
120 for (; retry > 0U; retry--) {
121 __NOP();
122 }
123 }
124 }
125