1 // SPDX-License-Identifier: Apache-2.0 OR MIT
2
3 /*
4 Refs:
5 - Xtensa Instruction Set Architecture (ISA) Reference Manual https://0x04.net/~mwk/doc/xtensa.pdf
6 - Linux kernel's Xtensa atomic implementation https://github.com/torvalds/linux/blob/v6.11/arch/xtensa/include/asm/atomic.h
7 */
8
9 use core::arch::asm;
10
11 pub(super) use core::sync::atomic;
12
13 pub(super) type State = u32;
14
15 /// Disables interrupts and returns the previous interrupt state.
16 #[inline(always)]
disable() -> State17 pub(super) fn disable() -> State {
18 let r: State;
19 // SAFETY: reading the PS special register and disabling all interrupts is safe.
20 // (see module-level comments of interrupt/mod.rs on the safety of using privileged instructions)
21 unsafe {
22 // Do not use `nomem` and `readonly` because prevent subsequent memory accesses from being reordered before interrupts are disabled.
23 // Interrupt level 15 to disable all interrupts.
24 // SYNC after RSIL is not required.
25 asm!("rsil {0}, 15", out(reg) r, options(nostack));
26 }
27 r
28 }
29
30 /// Restores the previous interrupt state.
31 ///
32 /// # Safety
33 ///
34 /// The state must be the one retrieved by the previous `disable`.
35 #[inline(always)]
restore(r: State)36 pub(super) unsafe fn restore(r: State) {
37 // SAFETY: the caller must guarantee that the state was retrieved by the previous `disable`,
38 // and we've checked that interrupts were enabled before disabling interrupts.
39 unsafe {
40 // Do not use `nomem` and `readonly` because prevent preceding memory accesses from being reordered after interrupts are enabled.
41 // SYNC after WSR is required to guarantee that subsequent RSIL read the written value.
42 asm!(
43 "wsr.ps {0}",
44 "rsync",
45 in(reg) r,
46 options(nostack),
47 );
48 }
49 }
50